Hafez; Walid M.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Hafez; Walid M..The latest application filed is for "non-planar i/o and logic semiconductor devices having different workfunction on common substrate".

Company Profile

82.110.169

Hafez; Walid M. - Portland OR
Hafez; Walid M - Portland OR
- Portland OR US

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Transmission line structures for III-N devices Grant 11,450,617 - Then , et al. September 20, 2	2022-09-20
Self-aligned gate endcap (SAGE) architecture having gate or contact plugs Grant 11,444,171 - Subramanian , et al. September 13, 2	2022-09-13
Gate-all-around integrated circuit structures having dual nanoribbon channel structures Grant 11,437,483 - Trivedi , et al. September 6, 2	2022-09-06
Self-aligned gate endcap (SAGE) architecture having gate contacts Grant 11,424,245 - Subramanian , et al. August 23, 2	2022-08-23
Non-planar I/o And Logic Semiconductor Devices Having Different Workfunction On Common Substrate App 20220238383 - OLAC-VAW; Roman W. ; et al.	2022-07-28
III-N tunnel device architectures and high frequency mixers employing a III-N tunnel device Grant 11,387,328 - Ramaswamy , et al. July 12, 2	2022-07-12
Metal Fuse And Self-aligned Gate Edge (sage) Architecture Having A Metal Fuse App 20220173105 - BAMBERY; Rohan K. ; et al.	2022-06-02
Non-planar I/O and logic semiconductor devices having different workfunction on common substrate Grant 11,335,601 - Olac-Vaw , et al. May 17, 2	2022-05-17
Self-aligned gate endcap (SAGE) architecture having endcap plugs Grant 11,329,138 - Subramanian , et al. May 10, 2	2022-05-10
Non-planar Semiconductor Device Having Omega-fin With Doped Sub-fin Region And Method To Fabricate Same App 20220130962 - BHIMARASETTI; Gopinath ; et al.	2022-04-28
High Voltage Three-dimensional Devices Having Dielectric Liners App 20220130871 - HAFEZ; Walid M. ; et al.	2022-04-28
Device Terminal Interconnect Structures App 20220122911 - Subramanian; Sairam ; et al.	2022-04-21
Dielectric And Isolation Lower Fin Material For Fin-based Electronics App 20220102488 - HAFEZ; Walid M. ; et al.	2022-03-31
Metal fuse and self-aligned gate edge (SAGE) architecture having a metal fuse Grant 11,289,483 - Bambery , et al. March 29, 2	2022-03-29
Adjacent Gate-all-around Integrated Circuit Structures Having Non-merged Epitaxial Source Or Drain Regions App 20220093588 - SUBRAMANIAN; Sairam ; et al.	2022-03-24
Non-planar semiconductor device having omega-fin with doped sub-fin region and method to fabricate same Grant 11,276,760 - Bhimarasetti , et al. March 15, 2	2022-03-15
Unidirectional Self-aligned Gate Endcap (sage) Architectures With Gate-orthogonal Walls App 20220077145 - HAFEZ; Walid M. ; et al.	2022-03-10
Dual Self-aligned Gate Endcap (sage) Architectures App 20220077302 - SUBRAMANIAN; Sairam ; et al.	2022-03-10
Iii-n Transistors With Integrated Linearization Devices App 20220068910 - Then; Han Wui ; et al.	2022-03-03
High voltage three-dimensional devices having dielectric liners Grant 11,251,201 - Hafez , et al. February 15, 2	2022-02-15
Gate isolation in non-planar transistors Grant 11,227,863 - Guler , et al. January 18, 2	2022-01-18
Device terminal interconnect structures Grant 11,227,829 - Subramanian , et al. January 18, 2	2022-01-18
Unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls Grant 11,217,582 - Hafez , et al. January 4, 2	2022-01-04
Self-aligned Front-end Charge Trap Flash Memory Cell And Capacitor Design For Integrated High-density Scaled Devices App 20210399002 - TRIVEDI; Tanuj ; et al.	2021-12-23
Dual self-aligned gate endcap (SAGE) architectures Grant 11,205,708 - Subramanian , et al. December 21, 2	2021-12-21
Dielectric and isolation lower fin material for fin-based electronics Grant 11,139,370 - Hafez , et al. October 5, 2	2021-10-05
Gate Endcap Architectures Having Relatively Short Vertical Stack App 20210305243 - SUBRAMANIAN; Sairam ; et al.	2021-09-30
Multi voltage threshold transistors through process and design-induced multiple work functions Grant 11,121,040 - Lee , et al. September 14, 2	2021-09-14
Gate-all-around Integrated Circuit Structures Having Dual Nanoribbon Channel Structures App 20210280683 - TRIVEDI; Tanuj ; et al.	2021-09-09
Transistor with an airgap spacer adjacent to a transistor gate Grant 11,114,538 - Lee , et al. September 7, 2	2021-09-07
Gate-all-around Integrated Circuit Structures Having Depopulated Channel Structures App 20210257453 - TRIVEDI; Tanuj ; et al.	2021-08-19
Gate-all-around Integrated Circuit Structures Having Depopulated Channel Structures App 20210257452 - TRIVEDI; Tanuj ; et al.	2021-08-19
Gate-all-around integrated circuit structures having depopulated channel structures Grant 11,094,782 - Trivedi , et al. August 17, 2	2021-08-17
Hybrid finfet structure with bulk source/drain regions Grant 11,075,286 - Jan , et al. July 27, 2	2021-07-27
Asymmetric spacer for low capacitance applications Grant 11,063,137 - Lin , et al. July 13, 2	2021-07-13
Strain Based Performance Enhancement Using Selective Metal Oxidation Inside Gate App 20210193844 - RAMASWAMY; Rahul ; et al.	2021-06-24
Esd Diode Solution For Nanoribbon Architectures App 20210183850 - NIDHI; Nidhi ; et al.	2021-06-17
Nanoribbon Thick Gate Device With Hybrid Dielectric Tuning For High Breakdown And Vt Modulation App 20210183857 - HAFEZ; Walid M. ; et al.	2021-06-17
High Voltage Ultra-low Power Thick Gate Nanoribbon Transistors For Soc Applications App 20210184045 - RAMASWAMY; Rahul ; et al.	2021-06-17
Nanoribbon Thick Gate Devices With Differential Ribbon Spacing And Width For Soc Applications App 20210184001 - TRIVEDI; Tanuj ; et al.	2021-06-17
Co-integrated High Performance Nanoribbon Transistors With High Voltage Thick Gate Finfet Devices App 20210184051 - TRIVEDI; Tanuj ; et al.	2021-06-17
High Voltage Extended-drain Mos (edmos) Nanowire Transistors App 20210184032 - NIDHI; Nidhi ; et al.	2021-06-17
Single Gated 3d Nanowire Inverter For High Density Thick Gate Soc Applications App 20210184000 - RAMASWAMY; Rahul ; et al.	2021-06-17
Resistor between gates in self-aligned gate edge architecture Grant 10,964,690 - Olac-Vaw , et al. March 30, 2	2021-03-30
Non-planar I/o And Logic Semiconductor Devices Having Different Workfunction On Common Substrate App 20210090956 - OLAC-VAW; Roman W. ; et al.	2021-03-25
Dual fin endcap for self-aligned gate edge (SAGE) architectures Grant 10,950,606 - Hafez , et al. March 16, 2	2021-03-16
Fin-based thin film resistor Grant 10,930,729 - Jan , et al. February 23, 2	2021-02-23
High Voltage Three-dimensional Devices Having Dielectric Liners App 20210036026 - HAFEZ; Walid M. ; et al.	2021-02-04
Non-planar I/O and logic semiconductor devices having different workfunction on common substrate Grant 10,892,192 - Olac-Vaw , et al. January 12, 2	2021-01-12
Metal resistor and self-aligned gate edge (SAGE) architecture having a metal resistor Grant 10,892,261 - Hafez , et al. January 12, 2	2021-01-12
Self-aligned Gate Endcap (sage) Architecture Having Vertical Transistor With Sage Gate Structure App 20200411665 - HAFEZ; Walid M. ; et al.	2020-12-31
Variable Pitch And Stack Height For High Performance Interconnects App 20200411435 - LIU; En-Shao ; et al.	2020-12-31
Co-integration Of Extended-drain And Self-aligned Iii-n Transistors On A Single Die App 20200395358 - Radosavljevic; Marko ; et al.	2020-12-17
FINFET based junctionless wrap around structure Grant 10,854,757 - Ramaswamy , et al. December 1, 2	2020-12-01
Isolation well doping with solid-state diffusion sources for finFET architectures Grant 10,854,607 - Jan , et al. December 1, 2	2020-12-01
Gate Isolation In Non-planar Transistors App 20200373299 - Guler; Leonard P. ; et al.	2020-11-26
Enhancement-depletion Cascode Arrangements For Enhancement Mode Iii-n Transistors App 20200373297 - Nidhi; Nidhi ; et al.	2020-11-26
Iii-n Transistor Arrangements For Reducing Nonlinearity Of Off-state Capacitance App 20200373421 - Nidhi; Nidhi ; et al.	2020-11-26
Antifuse element using spacer breakdown Grant 10,847,456 - Chang , et al. November 24, 2	2020-11-24
High voltage three-dimensional devices having dielectric liners Grant 10,847,544 - Hafez , et al. November 24, 2	2020-11-24
Semiconductor devices, radio frequency devices and methods for forming semiconductor devices Grant 10,840,341 - Radosavljevic , et al. November 17, 2	2020-11-17
Dielectric And Isolation Lower Fin Material For Fin-based Electronics App 20200335582 - HAFEZ; Walid M. ; et al.	2020-10-22
Charge-induced Threshold Voltage Tuning In Iii-n Transistors App 20200335590 - Nidhi; Nidhi ; et al.	2020-10-22
Integration of Si-based transistors with non-Si technologies by semiconductor regrowth over an insulator material App 20200335526 - Nidhi; Nidhi ; et al.	2020-10-22
Schemes For Reducing Off-state Capacitance In Iii-n Transistor Arrangements App 20200335592 - Ramaswamy; Rahul ; et al.	2020-10-22
Gate isolation in non-planar transistors Grant 10,797,047 - Guler , et al. October 6, 2	2020-10-06
Iii-n Transistors Integrated With Thin-film Transistors Having Graded Dopant Concentrations And/or Composite Gate Dielectrics App 20200312961 - Then; Han Wui ; et al.	2020-10-01
Integration Of Passive Components In Iii-n Devices App 20200303371 - Nidhi; Nidhi ; et al.	2020-09-24
Ultra-scaled fin pitch having dual gate dielectrics Grant 10,784,378 - Hafez , et al. Sept	2020-09-22
Transmission line structures for III-N devices App 20200294932 - Then; Han Wui ; et al.	2020-09-17
III-N transistors with local stressors for threshold voltage control App 20200295172 - Dasgupta; Sansaptak ; et al.	2020-09-17
High-voltage Transistor With Self-aligned Isolation App 20200295190 - HAFEZ; Walid M. ; et al.	2020-09-17
Self-aligned Gate Endcap (sage) Architecture Having Gate Or Contact Plugs App 20200287015 - SUBRAMANIAN; Sairam ; et al.	2020-09-10
Self-aligned Gate Endcap (sage) Architecture Having Gate Contacts App 20200286890 - SUBRAMANIAN; Sairam ; et al.	2020-09-10
Self-aligned Gate Endcap (sage) Architecture Having Local Interconnects App 20200286891 - SUBRAMANIAN; Sairam ; et al.	2020-09-10
Planar Transistors With Wrap-around Gates And Wrap-around Source And Drain Contacts App 20200279932 - Nidhi; Nidhi ; et al.	2020-09-03
Non-planar I/o And Logic Semiconductor Devices Having Different Workfunction On Common Substrate App 20200273752 - OLAC-VAW; Roman W. ; et al.	2020-08-27
Integration Of Iii-n Transistors And Non-iii-n Transistors By Semiconductor Regrowth App 20200273860 - Dasgupta; Sansaptak ; et al.	2020-08-27
High Voltage Three-dimensional Devices Having Dielectric Liners App 20200273887 - HAFEZ; Walid M. ; et al.	2020-08-27
Depletion mode gate in ultrathin FINFET based architecture Grant 10,756,210 - Jan , et al. A	2020-08-25
Logic Circuit With Indium Nitride Quantum Well App 20200266190 - Radosavljevic; Marko ; et al.	2020-08-20
Gate Structures Resistant To Voltage Breakdown App 20200266278 - RADOSAVLJEVIC; Marko ; et al.	2020-08-20
Transistors With Backside Field Plate Structures App 20200266291 - Rode; Johann Christian ; et al.	2020-08-20
Metal Fuse And Self-aligned Gate Edge (sage) Architecture Having A Metal Fuse App 20200266194 - BAMBERY; Rohan K. ; et al.	2020-08-20
Dielectric and isolation lower Fin material for Fin-based electronics Grant 10,741,640 - Hafez , et al. A	2020-08-11
Methods Of Integrating Multiple Gate Dielectric Transistors On A Tri-gate (finfet) Process App 20200251470 - Kind Code	2020-08-06
Isolation Well Doping With Solid-state Diffusion Sources For Finfet Architectures App 20200251471 - Kind Code	2020-08-06
Integration Of Iii-n Transistors And Polysilicon Resistors App 20200227407 - Radosavljevic; Marko ; et al.	2020-07-16
Maskless Process For Fabricating Gate Structures And Schottky Diodes App 20200219772 - RAMASWAMY; RAHUL ; et al.	2020-07-09
Side-by-side Integration Of Iii-n Transistors And Thin-film Transistors App 20200219878 - Then; Han Wui ; et al.	2020-07-09
Transistors With Ion- Or Fixed Charge-based Field Plate Structures App 20200219986 - Then; Han Wui ; et al.	2020-07-09
STACKED INTEGRATION OF lll-N TRANSISTORS AND THIN-FILM TRANSISTORS App 20200219877 - Then; Han Wui ; et al.	2020-07-09
High-voltage transistor with self-aligned isolation Grant 10,707,346 - Hafez , et al.	2020-07-07
Superlattice Finfet With Tunable Drive Current Capability App 20200203484 - NIDHI; Nidhi ; et al.	2020-06-25
Non-planar I/O and logic semiconductor devices having different workfunction on common substrate Grant 10,692,771 - Olac-Vaw , et al.	2020-06-23
High voltage three-dimensional devices having dielectric liners Grant 10,692,888 - Hafez , et al.	2020-06-23
Antenna Gate Field Plate On 2deg Planar Fet App 20200194578 - RAMASWAMY; Rahul ; et al.	2020-06-18
E-d Mode 2deg Fet With Gate Spacer To Locally Tune Vt And Improve Breakdown App 20200194575 - RAMASWAMY; Rahul ; et al.	2020-06-18
Methods of integrating multiple gate dielectric transistors on a tri-gate (FINFET) process Grant 10,658,361 - Tsai , et al.	2020-05-19
Doping with solid-state diffusion sources for finFET architectures Grant 10,643,999 - Jan , et al.	2020-05-05
Semiconductor devices, radio frequency devices and methods for forming semiconductor devices App 20200135865 - Radosavljevic; Marko ; et al.	2020-04-30
Iii-n Tunnel Device Architectures & High Frequency Mixers Employing A Iii-n Tunnel Device App 20200105881 - Ramaswamy; Rahul ; et al.	2020-04-02
Depletion Mode Gate In Ultrathin Finfet Based Architecture App 20200066907 - JAN; Chia-Hong ; et al.	2020-02-27
Ultra-scaled Fin Pitch Processes Having Dual Gate Dielectrics And The Resulting Structures App 20200066897 - HAFEZ; Walid M. ; et al.	2020-02-27
Metal Resistor And Self-aligned Gate Edge (sage) Architecture Having A Metal Resistor App 20200066712 - HAFEZ; Walid M. ; et al.	2020-02-27
Transistor with thermal performance boost Grant 10,559,688 - Lee , et al. Feb	2020-02-11
Resistor Between Gates In Self-aligned Gate Edge Architecture App 20200043914 - OLAC-VAW; ROMAN W. ; et al.	2020-02-06
Vertical transistor using a through silicon via gate Grant 10,505,034 - Yang , et al. Dec	2019-12-10
Work Function Material Recess For Threshold Voltage Tuning In Finfets App 20190348516 - Ramaswamy; Rahul ; et al.	2019-11-14
Multi Voltage Threshold Transistors Through Process And Design-induced Multiple Work Functions App 20190304840 - LEE; Chen-Guan ; et al.	2019-10-03
Device Terminal Interconnect Structures App 20190304902 - Subramanian; Sairam ; et al.	2019-10-03
Metal Interconnect Fuse Memory Arrays App 20190304893 - DORGAN; Vincent ; et al.	2019-10-03
Self-aligned Gate Endcap (sage) Architecture Having Endcap Plugs App 20190305111 - SUBRAMANIAN; Sairam ; et al.	2019-10-03
Dual Self-aligned Gate Endcap (sage) Architectures App 20190305112 - SUBRAMANIAN; Sairam ; et al.	2019-10-03
Unidirectional Self-aligned Gate Endcap (sage) Architectures With Gate-orthogonal Walls App 20190304971 - HAFEZ; Walid M. ; et al.	2019-10-03
Dielectric And Isolation Lower Fin Material For Fin-based Electronics App 20190296105 - HAFEZ; Walid M. ; et al.	2019-09-26
Non-planar Semiconductor Device Having Omega-fin With Doped Sub-fin Region And Method To Fabricate Same App 20190296114 - BHIMARASETTI; Gopinath ; et al.	2019-09-26
Doping With Solid-state Diffusion Sources For Finfet Architectures App 20190287973 - Jan; Chia-Hong ; et al.	2019-09-19
Dual Fin Endcap For Self-aligned Gate Edge (sage) Architectures App 20190287972 - HAFEZ; Walid M. ; et al.	2019-09-19
Finfet Based Junctionless Wrap Around Structure App 20190245098 - RAMASWAMY; Rahul ; et al.	2019-08-08
Hybrid Finfet Structure With Bulk Source/drain Regions App 20190237564 - JAN; Chia-Hong ; et al.	2019-08-01
Dielectric and isolation lower Fin material for Fin-based electronics Grant 10,355,081 - Hafez , et al. July 16, 2	2019-07-16
Non-planar semiconductor device having omega-fin with doped sub-fin region and method to fabricate same Grant 10,355,093 - Bhimarasetti , et al. July 16, 2	2019-07-16
Fin-based Thin Film Resistor App 20190206980 - JAN; Chia-Hong ; et al.	2019-07-04
Doping with solid-state diffusion sources for finFET architectures Grant 10,340,273 - Jan , et al.	2019-07-02
Compound lateral resistor structures for integrated circuitry Grant 10,340,220 - Lee , et al.	2019-07-02
Non-planar I/o And Logic Semiconductor Devices Having Different Workfunction On Common Substrate App 20190157153 - OLAC-VAW; Roman W. ; et al.	2019-05-23
Asymmetric Spacer For Low Capacitance Applications App 20190123170 - Lin; Jui-Yen ; et al.	2019-04-25
Transistor With Airgap Spacer App 20190123164 - Lee; Chen-Guan ; et al.	2019-04-25
Vertical non-planar semiconductor device for system-on-chip (SoC) applications Grant 10,263,112 - Jan , et al.	2019-04-16
Non-linear Fin-based Devices App 20190097057 - Dias; Neville L. ; et al.	2019-03-28
Non-planar I/O and logic semiconductor devices having different workfunction on common substrate Grant 10,229,853 - Olac-Vaw , et al.	2019-03-12
On-chip through-body-via capacitors and techniques for forming same Grant 10,229,866 - Chen , et al.	2019-03-12
Transistor with airgap spacer Grant 10,204,999 - Lee , et al. Feb	2019-02-12
Transistor With Thermal Performance Boost App 20190027604 - LEE; CHEN-GUAN ; et al.	2019-01-24
Compound Lateral Resistor Structures For Integrated Circuitry App 20190006279 - Lee; Chen-Guan ; et al.	2019-01-03
Non-linear fin-based devices Grant 10,164,115 - Dias , et al. Dec	2018-12-25
Through silicon via based photovoltaic cell Grant 10,158,034 - Phoa , et al. Dec	2018-12-18
Gate Isolation In Non-planar Transistors App 20180331098 - Guler; Leonard P. ; et al.	2018-11-15
Dual Threshold Voltage (vt) Channel Devices And Their Methods Of Fabrication App 20180323260 - CHANG; Hsu-Yu ; et al.	2018-11-08
Planar device on fin-based transistor architecture Grant 10,115,721 - Hafez , et al. October 30, 2	2018-10-30
Extended drain non-planar MOSFETs for electrostatic discharge (ESD) protection Grant 10,103,542 - Ahsan , et al. October 16, 2	2018-10-16
Methods of integrating multiple gate dielectric transistors on a tri-gate (finFET) process Grant 10,096,599 - Tsai , et al. October 9, 2	2018-10-09
Isolation well doping with solid-state diffusion sources for FinFET architectures Grant 10,090,304 - Jan , et al. October 2, 2	2018-10-02
High-voltage Transistor With Self-aligned Isolation App 20180248039 - HAFEZ; WALID M. ; et al.	2018-08-30
High Voltage Three-dimensional Devices Having Dielectric Liners App 20180226432 - HAFEZ; Walid M. ; et al.	2018-08-09
Antifuse Element Using Spacer Breakdown App 20180218977 - CHANG; TING ; et al.	2018-08-02
Transistor With Airgap Spacer App 20180197966 - Lee; Chen-Guan ; et al.	2018-07-12
Antifuse with backfilled terminals Grant 10,020,313 - Lee , et al. July 10, 2	2018-07-10
Embedded fuse with conductor backfill Grant 10,008,445 - Lee , et al. June 26, 2	2018-06-26
Fin-based semiconductor devices and methods Grant 10,002,954 - Hafez , et al. June 19, 2	2018-06-19
Dielectric And Isolation Lower Fin Material For Fin-based Electronics App 20180158906 - HAFEZ; Walid M. ; et al.	2018-06-07
On-chip Through-body-via Capacitors And Techniques For Forming Same App 20180151474 - CHEN; YI WEI ; et al.	2018-05-31
Controlled Modification Of Antifuse Programming Voltage App 20180145083 - TONG; Xiaoghong ; et al.	2018-05-24
High voltage three-dimensional devices having dielectric liners Grant 9,972,642 - Hafez , et al. May 15, 2	2018-05-15
Vertical Transistor Using A Through Silicon Via Gate App 20180130902 - YANG; Xiaodong ; et al.	2018-05-10
Multi-gate transistor with variably sized fin Grant 9,947,585 - Nidhi , et al. April 17, 2	2018-04-17
Antifuse element using spacer breakdown Grant 9,929,090 - Chang , et al. March 27, 2	2018-03-27
Extended-drain structures for high voltage field effect transistors Grant 9,911,815 - Nidhi , et al. March 6, 2	2018-03-06
Dielectric and isolation lower fin material for fin-based electronics Grant 9,899,472 - Hafez , et al. February 20, 2	2018-02-20
High Voltage Three-dimensional Devices Having Dielectric Liners App 20180040637 - HAFEZ; Walid M. ; et al.	2018-02-08
CMOS-compatible polycide fuse structure and method of fabricating same Grant 9,881,927 - Yeh , et al. January 30, 2	2018-01-30
High-voltage transistor architectures, processes of forming same, and systems containing same Grant 9,865,695 - Hafez , et al. January 9, 2	2018-01-09
Solid-source diffused junction for fin-based electronics Grant 9,842,944 - Hafez , et al. December 12, 2	2017-12-12
High voltage three-dimensional devices having dielectric liners Grant 9,806,095 - Hafez , et al. October 31, 2	2017-10-31
Memory cell having isolated charge sites and method of fabricating same Grant 9,799,668 - Chang , et al. October 24, 2	2017-10-24
Transistor architecture having extended recessed spacer and source/drain regions and method of making same Grant 9,786,783 - Hafez , et al. October 10, 2	2017-10-10
Non-planar semiconductor device having self-aligned fin with top blocking layer Grant 9,780,217 - Yeh , et al. October 3, 2	2017-10-03
Antifuse element utilizing non-planar topology Grant 9,748,252 - Hafez , et al. August 29, 2	2017-08-29
Low leakage non-planar access transistor for embedded dynamic random access memory (eDRAM) Grant 9,741,721 - Park , et al. August 22, 2	2017-08-22
Through Silicon Via Based Photovoltaic Cell App 20170155004 - PHOA; KINYIP ; et al.	2017-06-01
Dielectric And Isolation Lower Fin Material For Fin-based Electronics App 20170133461 - HAFEZ; Walid M. ; et al.	2017-05-11
Doping With Solid-state Diffusion Sources For Finfet Architectures App 20170125419 - Jan; Chia-Hong ; et al.	2017-05-04
Multi-gate Transistor With Variably Sized Fin App 20170103923 - NIDHI; NIDHI ; et al.	2017-04-13
Non-linear Fin-based Devices App 20170098709 - DIAS; NEVILLE L. ; et al.	2017-04-06
Extended-drain Structures For High Voltage Field Effect Transistors App 20170092726 - Nidhi; Nidhi ; et al.	2017-03-30
Non-planar Semiconductor Device Having Omega-fin With Doped Sub-fin Region And Method To Fabricate Same App 20170069725 - BHIMARASETTI; GOPINATH ; et al.	2017-03-09
Vertical Non-planar Semiconductor Device For System-on-chip (soc) Applications App 20170069758 - Jan; Chia-Hong ; et al.	2017-03-09
High voltage three-dimensional devices having dielectric liners Grant 9,570,467 - Hafez , et al. February 14, 2	2017-02-14
Extended Drain Non-planar Mosfets For Electrostatic Discharge (esd) Protection App 20170040793 - AHSAN; AKM ; et al.	2017-02-09
Solid-source Diffused Junction For Fin-based Electronics App 20170018658 - HAFEZ; Walid M. ; et al.	2017-01-19
Fin-based Semiconductor Devices And Methods App 20170005187 - Hafez; Walid M. ; et al.	2017-01-05
Vertical non-planar semiconductor device for system-on-chip (SoC) applications Grant 9,520,494 - Jan , et al. December 13, 2	2016-12-13
Antifuse Element Using Spacer Breakdown App 20160351498 - CHANG; TING ; et al.	2016-12-01
Extended drain non-planar MOSFETs for electrostatic discharge (ESD) protection Grant 9,502,883 - Ahsan , et al. November 22, 2	2016-11-22
Antifuse With Backfilled Terminals App 20160336332 - LEE; Chen Guan ; et al.	2016-11-17
Embedded Fuse With Conductor Backfill App 20160329282 - Lee; Chen-Guan ; et al.	2016-11-10
Planar Device On Fin-based Transistor Architecture App 20160276346 - HAFEZ; WALID M. ; et al.	2016-09-22
Non-Planar I/O and Logic Semiconductor Devices having Different Workfunction on Common Substrate App 20160225671 - OLAC-VAW; ROMAN W. ; et al.	2016-08-04
Isolation Well Doping With Solid-state Diffusion Sources For Finfet Architectures App 20160211262 - JAN; CHIA-HONG ; et al.	2016-07-21
Vertical Non-Planar Semiconductor Device for System-on-Chip (SoC) Applications App 20160211369 - JAN; CHIA-HONG ; et al.	2016-07-21
Low Leakage Non-Planar Access Transistor for Embedded Dynamic Random Access Memory (eDRAM) App 20160197082 - PARK; JOODONG ; et al.	2016-07-07
Planar device on fin-based transistor architecture Grant 9,356,023 - Hafez , et al. May 31, 2	2016-05-31
Metal fuse by topology Grant 9,324,665 - Lee , et al. April 26, 2	2016-04-26
Methods Of Integrating Multiple Gate Dielectric Transistors On A Tri-gate (finfet) Process App 20160111426 - TSAI; Curtis ; et al.	2016-04-21
High Voltage Three-dimensional Devices Having Dielectric Liners App 20160111449 - Hafez; Walid M. ; et al.	2016-04-21
Cmos-compatible Polycide Fuse Structure And Method Of Fabricating Same App 20160056162 - YEH; JENG-YA D. ; et al.	2016-02-25
Non-planar Semiconductor Device Having Self-aligned Fin With Top Blocking Layer App 20160056293 - YEH; JENG-YA D. ; et al.	2016-02-25
Memory Cell Having Isolated Charge Sites And Method Of Fabricating Same App 20160049418 - CHANG; TING ; et al.	2016-02-18
Antifuse Element Utilizing Non-planar Topology App 20160035735 - HAFEZ; WALID M. ; et al.	2016-02-04
Extended Drain Non-planar Mosfets For Electrostatic Discharge (esd) Protection App 20150326007 - AHSAN; AKM ; et al.	2015-11-12
Antifuse element utilizing non-planar topology Grant 9,159,734 - Hafez , et al. October 13, 2	2015-10-13
Methods of forming secured metal gate antifuse structures Grant 9,123,724 - Tong , et al. September 1, 2	2015-09-01
High-Voltage Transistor Architectures, Processes of Forming Same, and Systems Containing Same App 20150206948 - Hafez; Walid M. ; et al.	2015-07-23
Extended drain non-planar MOSFETs for electrostatic discharge (ESD) protection Grant 9,087,719 - Ahsan , et al. July 21, 2	2015-07-21
Metal Fuse By Topology App 20150187709 - Lee; Chen-Guan ; et al.	2015-07-02
High Voltage Three-dimensional Devices Having Dielectric Liners App 20150179525 - Hafez; Walid M. ; et al.	2015-06-25
High-voltage transistor architectures, processes of forming same, and systems containing same Grant 8,993,401 - Hafez , et al. March 31, 2	2015-03-31
High voltage three-dimensional devices having dielectric liners Grant 8,981,481 - Hafez , et al. March 17, 2	2015-03-17
Precision resistor for non-planar semiconductor device architecture Grant 8,889,508 - Yeh , et al. November 18, 2	2014-11-18
Methods Of Integrating Multiple Gate Dielectric Transistors On A Tri-gate (finfet) Process App 20140319623 - Tsai; Curtis ; et al.	2014-10-30
Precision Resistor For Non-planar Semiconductor Device Architecture App 20140308785 - Yeh; Jeng-Ya D. ; et al.	2014-10-16
Planar Device On Fin-based Transistor Architecture App 20140291766 - Hafez; Walid M. ; et al.	2014-10-02
Transistor Architecture Having Extended Recessed Spacer And Source/drain Regions And Method Of Making Same App 20140291737 - Hafez; Walid M. ; et al.	2014-10-02
Non-volatile storage element having dual work-function electrodes Grant 8,829,592 - Hafez , et al. September 9, 2	2014-09-09
Precision resistor for non-planar semiconductor device architecture Grant 8,796,772 - Yeh , et al. August 5, 2	2014-08-05
Converting A High Dielectric Spacer To A Low Dielectric Spacer App 20140175566 - Bhimarasetti; Gopinath ; et al.	2014-06-26
Penetrating implant for forming a semiconductor device Grant 8,741,720 - Curello , et al. June 3, 2	2014-06-03
Methods Of Forming Secured Metal Gate Antifuse Structures App 20140103448 - Tong; Xianghong ; et al.	2014-04-17
Extended Drain Non-planar MOSFETs for Electrostatic Discharge (ESD) Protection App 20140092506 - AHSAN; AKM ; et al.	2014-04-03
Precision Resistor For Non-planar Semiconductor Device Architecture App 20140084381 - Yeh; Jeng-Ya D. ; et al.	2014-03-27
Programmable/re-programmable device in high-k metal gate MOS Grant 8,681,573 - Hafez , et al. March 25, 2	2014-03-25
Multi-gate transistors Grant 8,669,617 - Jan , et al. March 11, 2	2014-03-11
High Voltage Three-dimensional Devices Having Dielectric Liners App 20140001569 - Hafez; Walid M. ; et al.	2014-01-02
Methods of forming secured metal gate antifuse structures Grant 08618613 -	2013-12-31
Methods of forming secured metal gate antifuse structures Grant 8,618,613 - Tong , et al. December 31, 2	2013-12-31
High-Voltage Transistor Architectures, Processes Of Forming Same, And Systems Containing Same App 20130288444 - Hafez; Walid M. ; et al.	2013-10-31
Antifuse Element Utilizing Non-planar Topology App 20130270559 - Hafez; Walid M. ; et al.	2013-10-17
Programmable/re-programmable Device In High-k Metal Gate Mos App 20130229882 - Hafez; Walid M. ; et al.	2013-09-05
Penetrating Implant For Forming A Semiconductor Device App 20130224926 - Curello; Giuseppe ; et al.	2013-08-29
High-voltage transistor architectures, processes of forming same, and systems containing same Grant 8,487,376 - Hafez , et al. July 16, 2	2013-07-16
Memory cell using BTI effects in high-k metal gate MOS Grant 8,432,751 - Hafez , et al. April 30, 2	2013-04-30
Penetrating implant for forming a semiconductor device Grant 8,426,927 - Curello , et al. April 23, 2	2013-04-23
Methods Of Forming Secured Metal Gate Antifuse Structures App 20120248546 - Tong; Xianghong ; et al.	2012-10-04
Multi-gate Transistors App 20120161237 - Jan; Chia-Hong ; et al.	2012-06-28
Memory Cell Using Bti Effects In High-k Metal Gate Mos App 20120163103 - Hafez; Walid M. ; et al.	2012-06-28
Non-volatile Storage Element Having Dual Work-function Electrodes App 20120146124 - Hafez; Walid M. ; et al.	2012-06-14
High-voltage Transistor Architectures, Processes Of Forming Same, And Systems Containing Same App 20120043609 - Hafez; Walid M. ; et al.	2012-02-23
Method of forming programmable anti-fuse element Grant 8,101,471 - Hafez , et al. January 24, 2	2012-01-24
Penetrating Implant For Forming A Semiconductor Device App 20110215422 - Curello; Giuseppe ; et al.	2011-09-08
Dual Work Function Gate Structures App 20110147837 - Hafez; Walid M. ; et al.	2011-06-23
Penetrating implant for forming a semiconductor device Grant 7,943,468 - Curello , et al. May 17, 2	2011-05-17
Flash Cell with Integrated High-K Dielectric and Metal-Based Control Gate App 20100163952 - Jan; Chia-Hong ; et al.	2010-07-01
Programmable fuse and anti-fuse elements and methods of changing conduction states of same App 20100164603 - Hafez; Walid M. ; et al.	2010-07-01
Penetrating Implant For Forming A Semiconductor Device App 20090242998 - Curello; Giuseppe ; et al.	2009-10-01