loadpatents
Patent applications and USPTO patent grants for Guo; Ta-Pen.The latest application filed is for "integrated circuit device".
Patent | Date |
---|---|
Flip flop standard cell Grant 11,437,982 - Samra , et al. September 6, 2 | 2022-09-06 |
Integrated Circuit Device App 20220271025 - CHEN; Chien-Ying ;   et al. | 2022-08-25 |
Integrated circuit layout method, device, and system Grant 11,355,488 - Chen , et al. June 7, 2 | 2022-06-07 |
Method Of Forming Semiconductor Device Including Deep Vias App 20210384121 - GUO; Ta-Pen ;   et al. | 2021-12-09 |
Method of manufacturing a semiconductor device and a semiconductor device Grant 11,195,763 - Chiang , et al. December 7, 2 | 2021-12-07 |
Method of manufacturing a semiconductor device and a semiconductor device Grant 11,177,179 - Chiang , et al. November 16, 2 | 2021-11-16 |
Vertical nanowire transistor for input/output structure Grant 11,127,734 - Colinge , et al. September 21, 2 | 2021-09-21 |
Semiconductor device including deep vias, and method of generating layout diagram for same Grant 11,127,673 - Guo , et al. September 21, 2 | 2021-09-21 |
Semiconductor arrangement with one or more semiconductor columns Grant 11,104,573 - Colinge , et al. August 31, 2 | 2021-08-31 |
Semiconductor Device Including Standard Cells App 20210257388 - GUO; Ta-Pen ;   et al. | 2021-08-19 |
Semiconductor Device Including Standard Cells With Combined Active Region App 20210224458 - GUO; TA-PEN ;   et al. | 2021-07-22 |
Semiconductor Device Including Standard Cell Having Split Portions App 20210224457 - GUO; TA-PEN ;   et al. | 2021-07-22 |
Flip Flop Standard Cell App 20210203314 - Samra; Nick ;   et al. | 2021-07-01 |
Semiconductor arrangement with one or more semiconductor columns Grant 11,038,052 - Colinge , et al. June 15, 2 | 2021-06-15 |
Semiconductor device including standard cells Grant 11,011,545 - Guo , et al. May 18, 2 | 2021-05-18 |
Semiconductor device including standard cells having different cell height Grant 10,998,340 - Guo , et al. May 4, 2 | 2021-05-04 |
Method for manufacturing monolithic three-dimensional (3D) integrated circuits Grant 10,985,159 - Colinge , et al. April 20, 2 | 2021-04-20 |
Method for manufacturing monolithic three-dimensional (3D) integrated circuits Grant 10,964,691 - Colinge , et al. March 30, 2 | 2021-03-30 |
Enhancing integrated circuit density with active atomic reservoir Grant 10,950,540 - Guo , et al. March 16, 2 | 2021-03-16 |
Flip flop standard cell Grant 10,951,201 - Samra , et al. March 16, 2 | 2021-03-16 |
Monolithic 3D Integration Inter-Tier Vias Insertion Scheme and Associated Layout Structure App 20200402899 - Guo; Ta-Pen ;   et al. | 2020-12-24 |
Semiconductor device with silicide Grant 10,854,721 - Colinge , et al. December 1, 2 | 2020-12-01 |
Integrated Circuit Layout Method, Device, And System App 20200350307 - CHEN; Chien-Ying ;   et al. | 2020-11-05 |
Method Of Manufacturing A Semiconductor Device And A Semiconductor Device App 20200335400 - CHIANG; Hung-Li ;   et al. | 2020-10-22 |
3d Cross-bar Nonvolatile Memory App 20200333987 - COLINGE; Jean-Pierre ;   et al. | 2020-10-22 |
Cell Of Transmission Gate Free Circuit And Integrated Circuit Layout Including The Same App 20200313659 - GUO; Ta-Pen ;   et al. | 2020-10-01 |
Monolithic 3D integration inter-tier vias insertion scheme and associated layout structure Grant 10,763,198 - Guo , et al. Sep | 2020-09-01 |
Integrated circuit layout method and device Grant 10,741,540 - Chen , et al. A | 2020-08-11 |
3D cross-bar nonvolatile memory Grant 10,705,766 - Colinge , et al. | 2020-07-07 |
Method of manufacturing a semiconductor device and a semiconductor device Grant 10,699,956 - Chiang , et al. | 2020-06-30 |
Cell of transmission gate free circuit and integrated circuit layout including the same Grant 10,686,428 - Guo , et al. | 2020-06-16 |
2-D material transistor with vertical structure Grant 10,644,168 - Colinge , et al. | 2020-05-05 |
Integrated Circuits And Manufacturing Methods Thereof App 20200126986 - KESHAVARZI; Ali ;   et al. | 2020-04-23 |
Semiconductor Device Including Standard Cells App 20200119048 - GUO; Ta-Pen ;   et al. | 2020-04-16 |
Method For Manufacturing Monolithic Three-dimensional (3d) Integrated Circuits App 20200098749 - Colinge; Jean-Pierre ;   et al. | 2020-03-26 |
Vertical Nanowire Transistor for Input/Output Structure App 20200075579 - Colinge; Jean-Pierre ;   et al. | 2020-03-05 |
Flip Flop Standard Cell App 20200059223 - Samra; Nick ;   et al. | 2020-02-20 |
Method for manufacturing monolithic three-dimensional (3D) integrated circuits Grant 10,559,563 - Colinge , et al. Feb | 2020-02-11 |
Integrated circuits and manufacturing methods thereof Grant 10,535,655 - Keshavarzi , et al. Ja | 2020-01-14 |
Integrated Circuit Layout Method, Device, And System App 20200006316 - CHEN; Chien-Ying ;   et al. | 2020-01-02 |
Method Of Manufacturing A Semiconductor Device And A Semiconductor Device App 20190393102 - CHIANG; Hung-Li ;   et al. | 2019-12-26 |
Method For Manufacturing Monolithic Three-dimensional (3d) Integrated Circuits App 20190393215 - Colinge; Jean-Pierre ;   et al. | 2019-12-26 |
Vertical nanowire transistor for input/output structure Grant 10,510,744 - Colinge , et al. Dec | 2019-12-17 |
Semiconductor Arrangement With One Or More Semiconductor Columns App 20190337800 - COLINGE; Jean-Pierre ;   et al. | 2019-11-07 |
SRAM with stacked bit cells Grant 10,453,522 - Diaz , et al. Oc | 2019-10-22 |
Semiconductor Device With Silicide App 20190305097 - COLINGE; Jean-Pierre ;   et al. | 2019-10-03 |
Enhancing Integrated Circuit Density with Active Atomic Reservoir App 20190287897 - Guo; Ta-Pen ;   et al. | 2019-09-19 |
Method of manufacturing a semiconductor device and a semiconductor device Grant 10,403,550 - Chiang , et al. Sep | 2019-09-03 |
Semiconductor Arrangement With One Or More Semiconductor Columns App 20190267488 - Colinge; Jean-Pierre ;   et al. | 2019-08-29 |
Semiconductor device with silicide Grant 10,325,989 - Colinge , et al. | 2019-06-18 |
Cell Of Transmission Gate Free Circuit And Integrated Circuit Layout Including The Same App 20190173456 - GUO; Ta-Pen ;   et al. | 2019-06-06 |
Enhancing integrated circuit density with active atomic reservoir Grant 10,312,189 - Guo , et al. | 2019-06-04 |
Semiconductor arrangement with one or more semiconductor columns Grant 10,294,101 - Colinge , et al. | 2019-05-21 |
Semiconductor Device Including Standard Cells App 20190148407 - GUO; Ta-Pen ;   et al. | 2019-05-16 |
Semiconductor arrangement with one or more semiconductor columns Grant 10,290,737 - Colinge , et al. | 2019-05-14 |
Monolithic 3D Integration Inter-Tier Vias Insertion Scheme and Associated Layout Structure App 20190131230 - Guo; Ta-Pen ;   et al. | 2019-05-02 |
3d Cross-bar Nonvolatile Memory App 20190121582 - Colinge; Jean-Pierre ;   et al. | 2019-04-25 |
Cell of transmission gate free circuit and integrated circuit and integrated circuit layout including the same Grant 10,270,430 - Guo , et al. | 2019-04-23 |
2-D Material Transistor with Vertical Structure App 20190103496 - COLINGE; Jean-Pierre ;   et al. | 2019-04-04 |
Method Of Manufacturing A Semiconductor Device And A Semiconductor Device App 20190067113 - CHIANG; Hung-Li ;   et al. | 2019-02-28 |
Method Of Manufacturing A Semiconductor Device And A Semiconductor Device App 20190067125 - CHIANG; Hung-Li ;   et al. | 2019-02-28 |
3D cross-bar nonvolatile memory Grant 10,191,694 - Colinge , et al. Ja | 2019-01-29 |
Monolithic 3D integration inter-tier vias insertion scheme and associated layout structure Grant 10,170,404 - Guo , et al. J | 2019-01-01 |
Method For Manufacturing Monolithic Three-dimensional (3d) Integrated Circuits App 20180374845 - Colinge; Jean-Pierre ;   et al. | 2018-12-27 |
Gate structure and method for fabricating the same Grant 10,164,040 - Colinge , et al. Dec | 2018-12-25 |
Semiconductor devices and methods of manufacture thereof Grant 10,157,928 - Colinge , et al. Dec | 2018-12-18 |
Memory device and method for fabricating the same Grant 10,134,918 - Colinge , et al. November 20, 2 | 2018-11-20 |
2-D material transistor with vertical structure Grant 10,134,915 - Colinge , et al. November 20, 2 | 2018-11-20 |
Stacked device and associated layout structure Grant 10,083,869 - Guo , et al. September 25, 2 | 2018-09-25 |
Semiconductor Arrangement With One Or More Semiconductor Columns App 20180269321 - COLINGE; Jean-Pierre ;   et al. | 2018-09-20 |
Enhancing Integrated Circuit Density with Active Atomic Reservoir App 20180218976 - Guo; Ta-Pen ;   et al. | 2018-08-02 |
Cell Of Transmission Gate Free Circuit And Integrated Circuit Layout Including The Same App 20180183414 - GUO; Ta-Pen ;   et al. | 2018-06-28 |
Semiconductor device with reduced electrical resistance and capacitance Grant 10,008,566 - Colinge , et al. June 26, 2 | 2018-06-26 |
2-d Material Transistor With Vertical Structure App 20180175213 - COLINGE; Jean-Pierre ;   et al. | 2018-06-21 |
Semiconductor arrangement with one or more semiconductor columns Grant 9,978,863 - Colinge , et al. May 22, 2 | 2018-05-22 |
Enhancing integrated circuit density with active atomic reservoir Grant 9,929,087 - Guo , et al. March 27, 2 | 2018-03-27 |
Semiconductor Devices and Methods of Manufacture Thereof App 20180069011 - Colinge; Jean-Pierre ;   et al. | 2018-03-08 |
3d Cross-bar Nonvolatile Memory App 20180059992 - COLINGE; Jean-Pierre ;   et al. | 2018-03-01 |
Method of forming masks Grant 9,892,224 - Lin , et al. February 13, 2 | 2018-02-13 |
FinFET with an asymmetric source/drain structure and method of making same Grant 9,882,002 - Tseng , et al. January 30, 2 | 2018-01-30 |
Semiconductor Arrangement With One Or More Semiconductor Cloumns App 20180002172 - COLINGE; Jean-Pierre ;   et al. | 2018-01-04 |
Vertical Nanowire Transistor for Input/Output Structure App 20170365597 - Colinge; Jean-Pierre ;   et al. | 2017-12-21 |
Method for cell placement in semiconductor layout and system thereof Grant 9,846,755 - Kuo , et al. December 19, 2 | 2017-12-19 |
Semiconductor devices and methods of manufacture thereof Grant 9,825,043 - Colinge , et al. November 21, 2 | 2017-11-21 |
Monolithic 3d Integration Inter-tier Vias Insertion Scheme And Associated Layout Structure App 20170287826 - Guo; Ta-Pen ;   et al. | 2017-10-05 |
Semiconductor arrangement with one or more semiconductor columns Grant 9,764,950 - Colinge , et al. September 19, 2 | 2017-09-19 |
Memory Device and Method for Fabricating the Same App 20170250288 - Colinge; Jean-Pierre ;   et al. | 2017-08-31 |
Stacked Device and Associated Layout Structure App 20170250115 - Guo; Ta-Pen ;   et al. | 2017-08-31 |
Semiconductor Device With Silicide App 20170236911 - Colinge; Jean-Pierre ;   et al. | 2017-08-17 |
Vertical nanowire transistor for input/output structure Grant 9,735,146 - Colinge , et al. August 15, 2 | 2017-08-15 |
Sram With Stacked Bit Cells App 20170221555 - DIAZ; Carlos H. ;   et al. | 2017-08-03 |
Gate Structure and Method for Fabricating the Same App 20170194447 - Colinge; Jean-Pierre ;   et al. | 2017-07-06 |
Monolithic 3D integration inter-tier vias insertion scheme and associated layout structure Grant 9,691,695 - Guo , et al. June 27, 2 | 2017-06-27 |
Memory device and method for fabricating the same Grant 9,673,209 - Colinge , et al. June 6, 2 | 2017-06-06 |
SRAM with stacked bit cells Grant 9,659,632 - Guo , et al. May 23, 2 | 2017-05-23 |
Enhancing Integrated Circuit Density with Active Atomic Reservoir App 20170141029 - Guo; Ta-Pen ;   et al. | 2017-05-18 |
Stacked device and associated layout structure Grant 9,653,457 - Guo , et al. May 16, 2 | 2017-05-16 |
Semiconductor device with silicide Grant 9,640,645 - Colinge , et al. May 2, 2 | 2017-05-02 |
Sram With Stacked Bit Cells App 20170110180 - GUO; Ta-Pen ;   et al. | 2017-04-20 |
Semiconductor arrangement Grant 9,620,422 - Colinge , et al. April 11, 2 | 2017-04-11 |
Gate structure and method for fabricating the same Grant 9,614,091 - Colinge , et al. April 4, 2 | 2017-04-04 |
Monolithic 3d Integration Inter-tier Vias Insertion Scheme And Associated Layout Structure App 20170062319 - Guo; Ta-Pen ;   et al. | 2017-03-02 |
Integrated Circuits And Manufacturing Methods Thereof App 20160372469 - Keshavarzi; Ali ;   et al. | 2016-12-22 |
Semiconductor Devices and Methods of Manufacture Thereof App 20160336329 - Colinge; Jean-Pierre ;   et al. | 2016-11-17 |
Contact Structure Of Semiconductor Device App 20160329405 - Tseng; Hsiang-Jen ;   et al. | 2016-11-10 |
Self-aligned wrapped-around structure Grant 9,478,624 - Colinge , et al. October 25, 2 | 2016-10-25 |
Method For Cell Placement In Semiconductor Layout And System Thereof App 20160306911 - KUO; MING-ZHANG ;   et al. | 2016-10-20 |
Method Of Forming Masks App 20160283631 - LIN; Yi-Hsiung ;   et al. | 2016-09-29 |
Semiconductor Arrangement App 20160268168 - Colinge; Jean-Pierre ;   et al. | 2016-09-15 |
Semiconductor devices and methods of manufacture thereof Grant 9,419,003 - Colinge , et al. August 16, 2 | 2016-08-16 |
Stacked Device and Associated Layout Structure App 20160211259 - Guo; Ta-Pen ;   et al. | 2016-07-21 |
Contact structure of non-planar semiconductor device Grant 9,397,217 - Tseng , et al. July 19, 2 | 2016-07-19 |
Integrated circuits and manufacturing methods thereof Grant 9,385,213 - Wu , et al. July 5, 2 | 2016-07-05 |
Semiconductor arrangement Grant 9,356,020 - Colinge , et al. May 31, 2 | 2016-05-31 |
FinFET with an Asymmetric Source/Drain Structure and Method of Making Same App 20160118462 - Tseng; Hsiang-Jen ;   et al. | 2016-04-28 |
Integrated circuits and manufacturing methods thereof Grant 9,312,260 - Keshavarzi , et al. April 12, 2 | 2016-04-12 |
Self-Aligned Wrapped-Around Structure App 20160087054 - Colinge; Jean-Pierre ;   et al. | 2016-03-24 |
Semiconductor device with seal ring with embedded decoupling capacitor Grant 9,293,606 - Chen , et al. March 22, 2 | 2016-03-22 |
Vertical Nanowire Transistor For Input/output Structure App 20160049391 - COLINGE; JEAN-PIERRE ;   et al. | 2016-02-18 |
FinFET with an asymmetric source/drain structure and method of making same Grant 9,231,106 - Tseng , et al. January 5, 2 | 2016-01-05 |
Gate Structure and Method for Fabricating the Same App 20150372149 - Colinge; Jean-Pierre ;   et al. | 2015-12-24 |
Self-aligned wrapped-around structure Grant 9,209,247 - Colinge , et al. December 8, 2 | 2015-12-08 |
Memory Device and Method for Fabricating the Same App 20150333078 - Colinge; Jean-Pierre ;   et al. | 2015-11-19 |
Vertical nanowire transistor for input/output structure Grant 9,177,924 - Colinge , et al. November 3, 2 | 2015-11-03 |
Semiconductor integrated circuit having a resistor and method of forming the same Grant 9,117,677 - Ma , et al. August 25, 2 | 2015-08-25 |
Vertical Nanowire Transistor For Input/output Structure App 20150171032 - Colinge; Jean-Pierre ;   et al. | 2015-06-18 |
Semiconductor device with reduced gate length Grant 8,999,805 - Colinge , et al. April 7, 2 | 2015-04-07 |
Semiconductor Arrangement App 20150069501 - Colinge; Jean-Pierre ;   et al. | 2015-03-12 |
Semiconductor Device With Reduced Electrical Resistance And Capacitance App 20150069475 - Colinge; Jean-Pierre ;   et al. | 2015-03-12 |
Semiconductor Device With Silicide App 20150060996 - Colinge; Jean-Pierre ;   et al. | 2015-03-05 |
Semiconductor Arrangement With One Or More Semiconductor Columns App 20150048441 - Colinge; Jean-Pierre ;   et al. | 2015-02-19 |
Semiconductor Arrangement With One Or More Semiconductor Columns App 20150048442 - Colinge; Jean-Pierre ;   et al. | 2015-02-19 |
Self-Aligned Wrapped-Around Structure App 20140332859 - Colinge; Jean-Pierre ;   et al. | 2014-11-13 |
FinFET with an Asymmetric Source/Drain Structure and Method of Making Same App 20140252477 - Tseng; Hsiang-Jen ;   et al. | 2014-09-11 |
Contact Structure Of Semiconductor Device App 20140183632 - Tseng; Hsiang-Jen ;   et al. | 2014-07-03 |
Integrated circuit design using DFM-enhanced architecture Grant 8,631,366 - Hou , et al. January 14, 2 | 2014-01-14 |
Pulse generator Grant 8,552,785 - Kuo , et al. October 8, 2 | 2013-10-08 |
Systems and methods of designing integrated circuits Grant 8,473,888 - Guo , et al. June 25, 2 | 2013-06-25 |
Integrated Circuits And Manufacturing Methods Thereof App 20130130456 - WU; Chung-Cheng ;   et al. | 2013-05-23 |
Semiconductor Device With Seal Ring With Embedded Decoupling Capacitor App 20130119449 - CHEN; Kuo-Ji ;   et al. | 2013-05-16 |
Planar compatible FDSOI design architecture Grant 8,443,306 - Dhong , et al. May 14, 2 | 2013-05-14 |
Pulse Generator App 20130113537 - KUO; Ming-Zhang ;   et al. | 2013-05-09 |
Semiconductor Integrated Circuit Having A Resistor And Method Of Forming The Same App 20130093052 - MA; Wei Yu ;   et al. | 2013-04-18 |
Integrated circuits and manufacturing methods thereof Grant 8,362,573 - Wu , et al. January 29, 2 | 2013-01-29 |
Systems And Methods Of Designing Integrated Circuits App 20120240088 - GUO; Ta-Pen ;   et al. | 2012-09-20 |
Integrated Circuits And Manufacturing Methods Thereof App 20110291197 - WU; Chung-Cheng ;   et al. | 2011-12-01 |
Integrated Circuits And Manufacturing Methods Thereof App 20110291200 - KESHAVARZI; Ali ;   et al. | 2011-12-01 |
Voltage level shifter Grant 7,940,108 - Wang , et al. May 10, 2 | 2011-05-10 |
Structure and system of mixing poly pitch cell design under default poly pitch design rules Grant 7,932,566 - Hou , et al. April 26, 2 | 2011-04-26 |
Integrated Circuit Design using DFM-Enhanced Architecture App 20100281446 - Hou; Yung-Chin ;   et al. | 2010-11-04 |
Layout architecture for improving circuit performance Grant 7,821,039 - Tien , et al. October 26, 2 | 2010-10-26 |
Standard cell without OD space effect in Y-direction Grant 7,808,051 - Hou , et al. October 5, 2 | 2010-10-05 |
Structure and System of Mixing Poly Pitch Cell Design under Default Poly Pitch Design Rules App 20100164614 - Hou; Yung-Chin ;   et al. | 2010-07-01 |
Novel Layout Architecture For Performance Enhancement App 20100127333 - Hou; Yung-Chin ;   et al. | 2010-05-27 |
Standard Cell without OD Space Effect in Y-Direction App 20100078725 - Hou; Yung-Chin ;   et al. | 2010-04-01 |
Layout Architecture for Improving Circuit Performance App 20090315079 - Tien; Li-Chun ;   et al. | 2009-12-24 |
Hidden precharge pseudo cache DRAM Grant 6,061,759 - Guo May 9, 2 | 2000-05-09 |
Programmable interconnect architecture using fewer storage cells than switches Grant 5,406,138 - Srinivasan , et al. * April 11, 1 | 1995-04-11 |
Structures for electrostatic discharge protection of electrical and other components Grant 5,341,267 - Whitten , et al. August 23, 1 | 1994-08-23 |
Reprogrammable interconnect architecture using fewer storage cells than switches Grant 5,319,261 - Srinivasan , et al. June 7, 1 | 1994-06-07 |
Static random access memory cell with single logic-high voltage level bit-line and address-line drivers Grant 5,301,147 - Guo , et al. April 5, 1 | 1994-04-05 |
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