Grinman; Andrey
Patent Applications and Registrations
Patent applications and USPTO patent grants for Grinman; Andrey.The latest application filed is for "methods for routing electrical interconnections and resultant structures".
- Grinman; Andrey - Charlotte NC
- Grinman; Andrey - Jerusalem IL
| Patent | Date |
|---|---|
| Methods for routing electrical interconnections and resultant structures Grant 11,063,159 - Gershtenman-Avsian , et al. July 13, 2 | 2021-07-13 |
| Methods for singulation and packaging Grant 10,818,550 - Ovrutsky , et al. October 27, 2 | 2020-10-27 |
| Methods For Routing Electrical Interconnections And Resultant Structures App 20190221679 - Gershtenman-Avsian; Hagit ; et al. | 2019-07-18 |
| Methods For Singulation And Packaging App 20190148232 - OVRUTSKY; David ; et al. | 2019-05-16 |
| Packaged semiconductor chips with array Grant 9,548,254 - Grinman , et al. January 17, 2 | 2017-01-17 |
| Packaged Semiconductor Chips With Array App 20150380336 - Grinman; Andrey ; et al. | 2015-12-31 |
| Packaged semiconductor chips with array Grant 9,070,678 - Grinman , et al. June 30, 2 | 2015-06-30 |
| Packaged Semiconductor Chips With Array App 20140151881 - Grinman; Andrey ; et al. | 2014-06-05 |
| Packaged semiconductor chips Grant 8,704,347 - Grinman , et al. April 22, 2 | 2014-04-22 |
| Packaged semiconductor chips with array Grant 8,653,644 - Grinman , et al. February 18, 2 | 2014-02-18 |
| Stack Packages Using Reconstituted Wafers App 20140027931 - Avsian; Osher ; et al. | 2014-01-30 |
| Packaged semiconductor chips with array Grant 8,569,876 - Grinman , et al. October 29, 2 | 2013-10-29 |
| Stack packages using reconstituted wafers Grant 8,551,815 - Avsian , et al. October 8, 2 | 2013-10-08 |
| Packaged Semiconductor Chips With Array App 20120153443 - Grinman; Andrey ; et al. | 2012-06-21 |
| Stack Packages Using Reconstituted Wafers App 20110248410 - Avsian; Osher ; et al. | 2011-10-13 |
| Wafer level chip packaging Grant 7,936,062 - Humpston , et al. May 3, 2 | 2011-05-03 |
| Packaged Semiconductor Chips App 20110012259 - Grinman; Andrey ; et al. | 2011-01-20 |
| Wafer-level fabrication of lidded chips with electrodeposited dielectric coating Grant 7,807,508 - Oganesian , et al. October 5, 2 | 2010-10-05 |
| Packaged semiconductor chips Grant 7,791,199 - Grinman , et al. September 7, 2 | 2010-09-07 |
| Packaged semiconductor chips with array App 20080116544 - Grinman; Andrey ; et al. | 2008-05-22 |
| Packaged semiconductor chips App 20080116545 - Grinman; Andrey ; et al. | 2008-05-22 |
| Wafer-level fabrication of lidded chips with electrodeposited dielectric coating App 20080099907 - Oganesian; Vage ; et al. | 2008-05-01 |
| Wafer level chip packaging App 20070190691 - Humpston; Giles ; et al. | 2007-08-16 |
| Wafer level packaging to lidded chips App 20070190747 - Humpston; Giles ; et al. | 2007-08-16 |
uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.
While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.
All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.
| 