loadpatents
name:-0.00040197372436523
name:-0.010684967041016
name:-0.00044989585876465
Gates, Jr.; Louis E. Patent Filings

Gates, Jr.; Louis E.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Gates, Jr.; Louis E..The latest application filed is for "method of constructing a sealed chip-on-board electronic module".

Company Profile
0.9.0
  • Gates, Jr.; Louis E. - Westlake Village CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Method of constructing a sealed chip-on-board electronic module
Grant 5,685,071 - Gates, Jr. , et al. November 11, 1
1997-11-11
Multi-layer film adhesive for electrically isolating and grounding an integrated circuit chip to a printed circuit substrate
Grant 5,600,183 - Gates, Jr. February 4, 1
1997-02-04
Orthogonal grid circuit interconnect method
Grant 5,568,682 - Gates, Jr. , et al. October 29, 1
1996-10-29
Stacked chip assembly and manufacturing method therefor
Grant 5,311,401 - Gates, Jr. , et al. May 10, 1
1994-05-10
Diaphragm test probe
Grant 4,972,143 - Kamensky , et al. November 20, 1
1990-11-20
Stacked wafer electronic package
Grant 4,956,746 - Gates, Jr. , et al. September 11, 1
1990-09-11
Microelectronic package
Grant 4,705,917 - Gates, Jr. , et al. November 10, 1
1987-11-10
Method for fabricating a shaped dielectric antenna lens
Grant 3,917,773 - Gates, Jr. , et al. November 4, 1
1975-11-04
Shaped ceramic dielectric antenna lens
Grant 3,866,234 - Gates, Jr. , et al. February 11, 1
1975-02-11

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