| Patent | Date |
|---|
Mram Access Coordination Systems And Methods
App 20220276807 - LOUIE; Benjamin ; et al. | 2022-09-01 |
Circuit engine for managing memory meta-stability
Grant 11,386,010 - Berger , et al. July 12, 2 | 2022-07-12 |
MRAM access coordination systems and methods with a plurality of pipelines
Grant 11,334,288 - Louie , et al. May 17, 2 | 2022-05-17 |
Error cache segmentation for power reduction
Grant 11,151,042 - Louie , et al. October 19, 2 | 2021-10-19 |
MRAM noise mitigation for write operations with simultaneous background operations
Grant 11,010,294 - Louie , et al. May 18, 2 | 2021-05-18 |
MRAM noise mitigation for background operations by delaying verify timing
Grant 10,990,465 - Louie , et al. April 27, 2 | 2021-04-27 |
Circuit Engine For Managing Memory Meta-stability
App 20210089455 - Berger; Neal ; et al. | 2021-03-25 |
Memory array with horizontal source line and a virtual source line
Grant 10,891,997 - Berger , et al. January 12, 2 | 2021-01-12 |
Over-voltage write operation of tunnel magnet-resistance ("TMR") memory device and correcting failure bits therefrom by using on-the-fly bit failure detection and bit redundancy remapping techniques
Grant 10,656,994 - Berger , et al. | 2020-05-19 |
Memory device with a plurality of memory banks where each memory bank is associated with a corresponding memory instruction pipeline and a dynamic redundancy register
Grant 10,628,316 - Berger , et al. | 2020-04-21 |
Mram Noise Mitigation For Background Operations By Delaying Verify Timing
App 20200057687 - LOUIE; Benjamin ; et al. | 2020-02-20 |
Mram Noise Mitigation For Write Operations With Simultaneous Background Operations
App 20200050545 - LOUIE; Benjamin ; et al. | 2020-02-13 |
Error Cache Segmentation For Power Reduction
App 20200042450 - LOUIE; Benjamin ; et al. | 2020-02-06 |
Multi-port random access memory
Grant 10,546,624 - El-Baraji , et al. Ja | 2020-01-28 |
On-the-fly bit failure detection and bit redundancy remapping techniques to correct for fixed bit defects
Grant 10,529,439 - Berger , et al. J | 2020-01-07 |
Forcing stuck bits, waterfall bits, shunt bits and low TMR bits to short during testing and using on-the-fly bit failure detection and bit redundancy remapping techniques to correct them
Grant 10,489,245 - Berger , et al. Nov | 2019-11-26 |
Forcing bits as bad to widen the window between the distributions of acceptable high and low resistive bits thereby lowering the margin and increasing the speed of the sense amplifiers
Grant 10,481,976 - Berger , et al. Nov | 2019-11-19 |
Memory device with a dual Y-multiplexer structure for performing two simultaneous operations on the same row of a memory bank
Grant 10,460,781 - Berger , et al. Oc | 2019-10-29 |
Memory instruction pipeline with a pre-read stage for a write operation for reducing power consumption in a memory device that uses dynamic redundancy registers
Grant 10,446,210 - Berger , et al. Oc | 2019-10-15 |
Method of processing incomplete memory operations in a memory device during a power up sequence and a power down sequence using a dynamic redundancy register
Grant 10,437,491 - Berger , et al. O | 2019-10-08 |
Method of flushing the contents of a dynamic redundancy register to a secure storage area during a power down in a memory device
Grant 10,437,723 - Berger , et al. O | 2019-10-08 |
Mram Access Coordination Systems And Methods
App 20190303044 - LOUIE; Benjamin ; et al. | 2019-10-03 |
Memory array with horizontal source line and sacrificial bitline per virtual source
Grant 10,395,712 - Berger , et al. A | 2019-08-27 |
Perpendicular source and bit lines for an MRAM array
Grant 10,395,711 - Berger , et al. A | 2019-08-27 |
Method of writing contents in memory during a power up sequence using a dynamic redundancy register in a memory device
Grant 10,360,964 - Berger , et al. | 2019-07-23 |
Memory Array With Horizontal Source Line And Sacrificial Bitline Per Virtual Source
App 20190206473 - BERGER; Neal ; et al. | 2019-07-04 |
Memory Array With Horizontal Source Line And A Virtual Source Line
App 20190206471 - BERGER; Neal ; et al. | 2019-07-04 |
Perpendicular Source And Bit Lines For An Mram Array
App 20190206470 - BERGER; Neal ; et al. | 2019-07-04 |
Multi-port Random Access Memory
App 20190206468 - EL-BARAJI; Mourad ; et al. | 2019-07-04 |
Forcing Bits As Bad To Widen The Window Between The Distributions Of Acceptable High And Low Resistive Bits Thereby Lowering The Margin And Increasing The Speed Of The Sense Amplifiers
App 20190121692 - BERGER; Neal ; et al. | 2019-04-25 |
Over-voltage Write Operation Of Tunnel Magnet-resistance ("tmr") Memory Device And Correcting Failure Bits Therefrom By Using On-the-fly Bit Failure Detection And Bit Redundancy Remapping Techniques
App 20190121694 - BERGER; Neal ; et al. | 2019-04-25 |
Forcing Stuck Bits, Waterfall Bits, Shunt Bits And Low Tmr Bits To Short During Testing And Using On-the-fly Bit Failure Detection And Bit Redundancy Remapping Techniques To Correct Them
App 20190121693 - BERGER; Neal ; et al. | 2019-04-25 |
On-the-fly Bit Failure Detection And Bit Redundancy Remapping Techniques To Correct For Fixed Bit Defects
App 20190122746 - BERGER; Neal ; et al. | 2019-04-25 |
Memory instruction pipeline with an additional write stage in a memory device that uses dynamic redundancy registers
Grant 10,192,601 - Berger , et al. Ja | 2019-01-29 |
Smart cache design to prevent overflow for a memory device with a dynamic redundancy register
Grant 10,192,602 - Berger , et al. Ja | 2019-01-29 |
Method Of Processing Incompleted Memory Operations In A Memory Device During A Power Up Sequence And A Power Down Sequence Using A Dynamic Redundancy Register
App 20180121117 - BERGER; Neal ; et al. | 2018-05-03 |
Memory Device With A Plurality Of Memory Banks Where Each Memory Bank Is Associated With A Corresponding Memory Instruction Pipeline And A Dynamic Redundancy Register
App 20180121361 - BERGER; Neal ; et al. | 2018-05-03 |
Method Of Flushing The Contents Of A Dynamic Redundancy Register To A Secure Storage Area During A Power Down In A Memory Device
App 20180121355 - BERGER; Neal ; et al. | 2018-05-03 |
Memory Device With A Dual Y-multiplexer Structure For Performing Two Simultaneous Operations On The Same Row Of A Memory Bank
App 20180122446 - BERGER; Neal ; et al. | 2018-05-03 |
Smart Cache Design To Prevent Overflow For A Memory Device With A Dynamic Redundancy Register
App 20180122450 - BERGER; Neal ; et al. | 2018-05-03 |
Memory Instruction Pipeline With A Pre-read Stage For A Write Operation For Reducing Power Consumption In A Memory Device That Uses Dynamic Redundancy Registers
App 20180122448 - BERGER; Neal ; et al. | 2018-05-03 |
Method Of Writing Contents In Memory During A Power Up Sequence Using A Dynamic Redundancy Register In A Memory Device
App 20180122447 - BERGER; Neal ; et al. | 2018-05-03 |
Memory Instruction Pipeline With An Additional Write Stage In A Memory Device That Uses Dynamic Redundancy Registers
App 20180122449 - BERGER; Neal ; et al. | 2018-05-03 |
| 