Costrini; Gregory

Patent Applications and Registrations

Patent applications and USPTO patent grants for Costrini; Gregory.The latest application filed is for "multi-level isolation structure".

Company Profile

3.29.26

Costrini; Gregory - Flanders NJ
Costrini; Gregory - Hopewell Junction NY
Costrini, Gregory - US

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Multi-level isolation structure Grant 11,158,633 - Wang , et al. October 26, 2	2021-10-26
Multi-level Isolation Structure App 20210313321 - Wang; Haiting ; et al.	2021-10-07
System and method employing three-dimensional (3D) emulation of in-kerf optical macros Grant 10,733,354 - Kim , et al.	2020-08-04
Design System And Method Employing Three-dimensional (3d) Emulation Of In-kerf Optical Macros App 20200201955 - Kim; Hojin ; et al.	2020-06-25
Structure and method to prevent EPI short between trenches in FinFET eDRAM Grant 10,177,154 - Aquilino , et al. J	2019-01-08
Structure And Method To Prevent Epi Short Between Trenches In Finfet Edram App 20170365606 - Aquilino; Michael V. ; et al.	2017-12-21
Structure and method to prevent EPI short between trenches in FINFET eDRAM Grant 9,818,741 - Aquilino , et al. November 14, 2	2017-11-14
Protection of semiconductor-oxide-containing gate dielectric during replacement gate formation Grant 9,577,068 - Costrini , et al. February 21, 2	2017-02-21
Structure And Method To Prevent Epi Short Between Trenches In Finfet Edram App 20170005098 - Aquilino; Michael V. ; et al.	2017-01-05
Protection Of Semiconductor-oxide-containing Gate Dielectric During Replacement Gate Formation App 20160351687 - Costrini; Gregory ; et al.	2016-12-01
Protection of semiconductor-oxide-containing gate dielectric during replacement gate formation Grant 9,431,395 - Costrini , et al. August 30, 2	2016-08-30
Protection Of Semiconductor-oxide-containing Gate Dielectric During Replacement Gate Formation App 20160005735 - Costrini; Gregory ; et al.	2016-01-07
Electrically conductive path forming below barrier oxide layer and integrated circuit Grant 8,563,398 - Costrini , et al. October 22, 2	2013-10-22
Conductive spacers for semiconductor devices and methods of forming Grant 8,039,888 - Bronner , et al. October 18, 2	2011-10-18
Methods for fabricating contacts to pillar structures in integrated circuits Grant 8,008,095 - Assefa , et al. August 30, 2	2011-08-30
Electrically Conductive Path Forming Below Barrier Oxide Layer And Integrated Circuit App 20110092056 - Costrini; Gregory ; et al.	2011-04-21
Electrically conductive path forming below barrier oxide layer and integrated circuit Grant 7,923,840 - Costrini , et al. April 12, 2	2011-04-12
Method and structure for self-aligned device contacts Grant 7,884,396 - Costrini , et al. February 8, 2	2011-02-08
Method and structure for self-aligned device contacts Grant 7,875,550 - Costrini , et al. January 25, 2	2011-01-25
Method for non-selective shallow trench isolation reactive ion etch for patterning hybrid-oriented devices compatible with high-performance highly-integrated logic devices Grant 7,871,893 - Costrini , et al. January 18, 2	2011-01-18
Highly manufacturable SRAM cells in substrates with hybrid crystal orientation Grant 7,605,447 - Doris , et al. October 20, 2	2009-10-20
Method For Non-selective Shallow Trench Isolation Reactive Ion Etch For Patterning Hybrid-oriented Devices Compatible With High-performance Highly-integrated Logic Devices App 20090189242 - Costrini; Gregory ; et al.	2009-07-30
Methods for Fabricating Contacts to Pillar Structures in Integrated Circuits App 20090091037 - Assefa; Solomon ; et al.	2009-04-09
Dual Stress Liner Structure Having Substantially Planar Interface Between Liners And Related Method App 20090090974 - Costrini; Gregory ; et al.	2009-04-09
Semiconductor structure with self-aligned device contacts Grant 7,470,615 - Costrini , et al. December 30, 2	2008-12-30
Method And Sturcture For Self-aligned Device Contacts App 20080308936 - Costrini; Gregory ; et al.	2008-12-18
Conductive Spacers For Semiconductor Devices And Methods Of Forming App 20080272398 - Bronner; Gary Bela ; et al.	2008-11-06
Method and Structure for Self-Aligned Device Contacts App 20080233743 - Costrini; Gregory ; et al.	2008-09-25
Electrically Conductive Path Forming Below Barrier Oxide Layer And Integrated Circuit App 20080166857 - Costrini; Gregory ; et al.	2008-07-10
Methods of patterning a magnetic stack of a magnetic memory cell and structures thereof Grant 7,374,952 - Kasko , et al. May 20, 2	2008-05-20
Method And Structure For Self-aligned Device Contacts App 20080026513 - Costrini; Gregory ; et al.	2008-01-31
Conductive Spacers For Semiconductor Devices And Methods Of Forming App 20070249133 - Bronner; Gary Bela ; et al.	2007-10-25
Highly Manufacturable Sram Cells In Substrates With Hybrid Crystal Orientation App 20070063278 - Doris; Bruce B. ; et al.	2007-03-22
Magnetic switching device Grant 7,097,777 - Costrini , et al. August 29, 2	2006-08-29
Mask schemes for patterning magnetic tunnel junctions Grant 7,001,783 - Costrini , et al. February 21, 2	2006-02-21
Spacer integration scheme in MRAM technology Grant 6,985,384 - Costrini , et al. January 10, 2	2006-01-10
Methods of patterning a magnetic stack of a magnetic memory cell and structures thereof App 20050280040 - Kasko, Ihar ; et al.	2005-12-22
Mask Schemes For Patterning Magnetic Tunnel Junctions App 20050277207 - Costrini, Gregory ; et al.	2005-12-15
Self-aligned mask to reduce cell layout area Grant 6,974,770 - Costrini , et al. December 13, 2	2005-12-13
Magnetic switching device App 20050207064 - Costrini, Gregory ; et al.	2005-09-22
Spacer integration scheme in MRAM technology App 20050146927 - Costrini, Gregory	2005-07-07
Self-aligned mask to reduce cell layout area App 20040259358 - Costrini, Gregory ; et al.	2004-12-23
Recessed metal lines for protective enclosure in integrated circuits Grant 6,812,141 - Gaidis , et al. November 2, 2	2004-11-02
Bilayer CMP process to improve surface roughness of magnetic stack in MRAM technology Grant 6,743,642 - Costrini , et al. June 1, 2	2004-06-01
Bilayer Cmp Process To Improve Surface Roughness Of Magnetic Stack In Mram Technology App 20040087038 - Costrini, Gregory ; et al.	2004-05-06
Patterning metal stack layers of magnetic switching device, utilizing a bilayer metal hardmask App 20040084400 - Costrini, Gregory ; et al.	2004-05-06
Spacer integration scheme in MRAM technology App 20040063223 - Costrini, Gregory ; et al.	2004-04-01
Insulating Cap Layer And Conductive Cap Layer For Semiconductor Devices With Magnetic Material Layers App 20040021188 - Low, Kia-Seng ; et al.	2004-02-05
Nitrogen-based highly polymerizing plasma process for etching of organic materials in semiconductor manufacturing Grant 6,686,296 - Costrini , et al. February 3, 2	2004-02-03
Insulating cap layer and conductive cap layer for semiconductor devices with magnetic material layers Grant 6,680,500 - Low , et al. January 20, 2	2004-01-20
Method/structure for creating aluminum wirebound pad on copper BEOL Grant 6,333,559 - Costrini , et al. December 25, 2	2001-12-25
Capacitor formed with Pt electrodes having a 3D cup-like shape with roughened inner and outer surfaces Grant 6,323,127 - Andricacos , et al. November 27, 2	2001-11-27
Method/structure for creating aluminum wirebound pad on copper BEOL Grant 6,187,680 - Costrini , et al. February 13, 2	2001-02-13
Gettering of particles from an electro-negative plasma with insulating chuck Grant 5,587,045 - Keller , et al. December 24, 1	1996-12-24

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.