Chirca; Kai

Patent Applications and Registrations

Patent applications and USPTO patent grants for Chirca; Kai.The latest application filed is for "distributed error detection and correction with hamming code handoff".

Company Profile

45.86.100

Chirca; Kai - Dallas TX
CHIRCA; Kai - Richardson TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Nested loop control Grant 11,442,709 - Chirca , et al. September 13, 2	2022-09-13
Distributed Error Detection And Correction With Hamming Code Handoff App 20220283942 - CHIRCA; Kai ; et al.	2022-09-08
Credit aware central arbitration for multi-endpoint, multi-core system Grant 11,429,526 - Pierson , et al. August 30, 2	2022-08-30
Multi-processor, Multi-domain, Multi-protocol, Cache Coherent, Speculation Aware Shared Memory And Interconnect App 20220269607 - CHIRCA; Kai ; et al.	2022-08-25
Multicore, multibank, fully concurrent coherence controller Grant 11,422,938 - Pierson , et al. August 23, 2	2022-08-23
Multicore Bus Architecture With Wire Reduction And Physical Congestion Minimization Via Shared Transaction Channels App 20220261373 - Thompson; David M. ; et al.	2022-08-18
Cache Preload Operations Using Streaming Engine App 20220244957 - Zbiciak; Joseph Raymond Michael ; et al.	2022-08-04
Storing a result of a first instruction of an execute packet in a holding register prior to completion of a second instruction of the execute packet Grant 11,403,110 - Chirca , et al. August 2, 2	2022-08-02
Configurable Cache For Multi-endpoint Heterogeneous Coherent System App 20220229779 - CHIRCA; Kai ; et al.	2022-07-21
Exit history based branch prediction Grant 11,372,646 - Chirca , et al. June 28, 2	2022-06-28
Distributed error detection and correction with hamming code handoff Grant 11,347,644 - Chirca , et al. May 31, 2	2022-05-31
Cache Coherence Shared State Suppression App 20220164287 - CHACHAD; Abhijeet Ashok ; et al.	2022-05-26
Multi-processor, multi-domain, multi-protocol, cache coherent, speculation aware shared memory and interconnect Grant 11,341,052 - Chirca , et al. May 24, 2	2022-05-24
Multicore Shared Cache Operation Engine App 20220156192 - Chirca; Kai ; et al.	2022-05-19
Delayed Snoop For Improved Multi-process False Sharing Parallel Thread Performance App 20220156193 - CHIRCA; Kai ; et al.	2022-05-19
Processing Device With A Microbranch Target Buffer For Branch Prediction Using Loop Iteration Count App 20220137972 - Chirca; Kai ; et al.	2022-05-05
Multicore bus architecture with wire reduction and physical congestion minimization via shared transaction channels Grant 11,321,268 - Thompson , et al. May 3, 2	2022-05-03
Configurable cache for multi-endpoint heterogeneous coherent system Grant 11,307,988 - Chirca , et al. April 19, 2	2022-04-19
Cache preload operations using streaming engine Grant 11,307,858 - Zbiciak , et al. April 19, 2	2022-04-19
Processing device with a microbranch target buffer for branch prediction using loop iteration count Grant 11,294,681 - Chirca , et al. April 5, 2	2022-04-05
Delayed snoop for improved multi-process false sharing parallel thread performance Grant 11,269,774 - Chirca , et al. March 8, 2	2022-03-08
Cache coherence shared state suppression Grant 11,243,883 - Chachad , et al. February 8, 2	2022-02-08
Multicore shared cache operation engine Grant 11,237,968 - Chirca , et al. February 1, 2	2022-02-01
Memory Pipeline Control In A Hierarchical Memory System App 20220027275 - Chachad; Abhijeet Ashok ; et al.	2022-01-27
Cache Management Operations Using Streaming Engine App 20210406014 - Zbiciak; Joseph Raymond Michael ; et al.	2021-12-30
Flexible hybrid firewall architecture Grant 11,212,256 - Mundra , et al. December 28, 2	2021-12-28
Virtual Network Pre-arbitration For Deadlock Avoidance And Enhanced Performance App 20210382822 - PIERSON; Matthew David ; et al.	2021-12-09
System And Method For Addressing Data In Memory App 20210357226 - ANDERSON; Timothy David ; et al.	2021-11-18
Multi-processor Bridge With Cache Allocate Awareness App 20210349821 - CHIRCA; Kai ; et al.	2021-11-11
Slot/sub-slot Prefetch Architecture For Multiple Memory Requestors App 20210349827 - CHIRCA; Kai ; et al.	2021-11-11
Implementing Fundamental Computational Primitives Using A Matrix Multiplication Accelerator (MMA) App 20210334337 - Redfern; Arthur John ; et al.	2021-10-28
Nested Loop Control App 20210334103 - Chirca; Kai ; et al.	2021-10-28
Multicore Shared Cache Operation Engine App 20210326260 - CHIRCA; Kai ; et al.	2021-10-21
Memory pipeline control in a hierarchical memory system Grant 11,138,117 - Chachad , et al. October 5, 2	2021-10-05
Cache management operations using streaming engine Grant 11,119,776 - Zbiciak , et al. September 14, 2	2021-09-14
System and method for addressing data in memory Grant 11,106,463 - Anderson , et al. August 31, 2	2021-08-31
Virtual network pre-arbitration for deadlock avoidance and enhanced performance Grant 11,099,994 - Pierson , et al. August 24, 2	2021-08-24
Multi-processor bridge with cache allocate awareness Grant 11,099,993 - Chirca , et al. August 24, 2	2021-08-24
Mechanism For Interrupting And Resuming Execution On An Unprotected Pipeline Processor App 20210247980 - ANDERSON; Timothy D. ; et al.	2021-08-12
Implementing fundamental computational primitives using a matrix multiplication accelerator (MMA) Grant 11,086,967 - Redfern , et al. August 10, 2	2021-08-10
Multicore shared cache operation engine Grant 11,086,778 - Chirca , et al. August 10, 2	2021-08-10
Highly Integrated Scalable, Flexible Dsp Megamodule Architecture App 20210240634 - Anderson; Timothy D. ; et al.	2021-08-05
Slot/sub-slot prefetch architecture for multiple memory requestors Grant 11,074,190 - Chirca , et al. July 27, 2	2021-07-27
Implied Fence On Stream Open App 20210216316 - BHORIA; Naveen ; et al.	2021-07-15
Nested loop control Grant 11,055,095 - Chirca , et al. July 6, 2	2021-07-06
Highly integrated scalable, flexible DSP megamodule architecture Grant 11,036,648 - Anderson , et al. June 15, 2	2021-06-15
Programmable Event Testing App 20210124673 - CHIRCA; Kai ; et al.	2021-04-29
Event Handling In Pipeline Execute Stages App 20210124589 - CHIRCA; Kai ; et al.	2021-04-29
User Mode Event Handling App 20210124607 - CHIRCA; Kai	2021-04-29
Mechanism for interrupting and resuming execution on an unprotected pipeline processor Grant 10,990,398 - Anderson , et al. April 27, 2	2021-04-27
Multi-power-domain bridge with prefetch and write merging Grant 10,990,529 - Wu , et al. April 27, 2	2021-04-27
Software-hardware Memory Management Modes App 20210109868 - ANDERSON; Timothy D. ; et al.	2021-04-15
Implied fence on stream open Grant 10,963,255 - Bhoria , et al. March 30, 2	2021-03-30
Virtual Network Pre-arbitration For Deadlock Avoidance And Enhanced Performance App 20210026768 - PIERSON; Matthew David ; et al.	2021-01-28
Multicore Bus Architecture With Non-blocking High Performance Transaction Credit System App 20210011872 - Thompson; David M. ; et al.	2021-01-14
Processing Device With A Micro-branch Target Buffer For Branch Prediction App 20200379764 - Chirca; Kai ; et al.	2020-12-03
System And Method For Addressing Data In Memory App 20200371803 - ANDERSON; Timothy David ; et al.	2020-11-26
Nested Loop Control App 20200371800 - CHIRCA; Kai ; et al.	2020-11-26
Streaming Engine With Deferred Exception Reporting App 20200371888 - Zbiciak; Joseph ; et al.	2020-11-26
Memory Pipeline Control In A Hierarchical Memory System App 20200371937 - Chachad; Abhijeet Ashok ; et al.	2020-11-26
Cache Coherence Shared State Suppression App 20200371931 - CHACHAD; Abhijeet Ashok ; et al.	2020-11-26
Nested Loop Control App 20200371762 - CHIRCA; Kai ; et al.	2020-11-26
Reconfigurable matrix multiplier system and method Grant 10,817,587 - Redfern , et al. October 27, 2	2020-10-27
Virtual network pre-arbitration for deadlock avoidance and enhanced performance Grant 10,802,974 - Pierson , et al. October 13, 2	2020-10-13
Multicore bus architecture with non-blocking high performance transaction credit system Grant 10,795,844 - Thompson , et al. October 6, 2	2020-10-06
Flexible Hybrid Firewall Architecture App 20200304464 - Mundra; Amritpal Singh ; et al.	2020-09-24
Cache Preload Operations Using Streaming Engine App 20200285470 - Zbiciak; Joseph Raymond Michael ; et al.	2020-09-10
Cache Management Operations Using Streaming Engine App 20200285469 - Zbiciak; Joseph Raymond Michael ; et al.	2020-09-10
Streaming engine with deferred exception reporting Grant 10,747,636 - Zbiciak , et al. A	2020-08-18
Nested loop control Grant 10,732,945 - Chirca , et al.	2020-08-04
Exit History Based Branch Prediction App 20200210191 - Chirca; Kai ; et al.	2020-07-02
Multicore Shared Cache Operation Engine App 20200117600 - CHIRCA; Kai ; et al.	2020-04-16
Multi-processor Bridge With Cache Allocate Awareness App 20200117395 - CHIRCA; Kai ; et al.	2020-04-16
Distributed Error Detection And Correction With Hamming Code Handoff App 20200119753 - CHIRCA; Kai ; et al.	2020-04-16
Multicore Shared Cache Operation Engine App 20200117394 - CHIRCA; Kai ; et al.	2020-04-16
Delayed Snoop For Improved Multi-process False Sharing Parallel Thread Performance App 20200117602 - CHIRCA; Kai ; et al.	2020-04-16
Configurable Cache For Multi-endpoint Heterogeneous Coherent System App 20200117467 - CHIRCA; Kai ; et al.	2020-04-16
Credit Aware Central Arbitration For Multi-endpoint, Multi-core System App 20200117619 - PIERSON; Matthew David ; et al.	2020-04-16
Multi-processor, Multi-domain, Multi-protocol, Cache Coherent, Speculation Aware Shared Memory And Interconnect App 20200117621 - CHIRCA; Kai ; et al.	2020-04-16
Multi-power-domain Bridge With Prefetch And Write Merging App 20200117606 - WU; Daniel ; et al.	2020-04-16
Virtual Network Pre-arbitration For Deadlock Avoidance And Enhanced Performance App 20200117618 - PIERSON; Matthew David ; et al.	2020-04-16
Multicore, Multibank, Fully Concurrent Coherence Controller App 20200117603 - PIERSON; Matthew David ; et al.	2020-04-16
Cache preload operations using streaming engine Grant 10,606,596 - Zbiciak , et al.	2020-03-31
Cache management operations using streaming engine Grant 10,599,433 - Zbiciak , et al.	2020-03-24
Slot/sub-slot Prefetch Architecture For Multiple Memory Requestors App 20200057723 - CHIRCA; Kai ; et al.	2020-02-20
Flexible hybrid firewall architecture Grant 10,560,428 - Mundra , et al. Feb	2020-02-11
Multicore Bus Architecture With Non-blocking High Performance Transaction Credit System App 20190354500 - Thompson; David M. ; et al.	2019-11-21
Slot/sub-slot prefetch architecture for multiple memory requestors Grant 10,394,718 - Chirca , et al. A	2019-08-27
Mechanism For Interrupting And Resuming Execution On An Unprotected Pipeline Processor App 20190243647 - ANDERSON; Timothy D. ; et al.	2019-08-08
Implied Fence On Stream Open App 20190220276 - BHORIA; Naveen ; et al.	2019-07-18
Multicore bus architecture with non-blocking high performance transaction credit system Grant 10,311,007 - Thompson , et al.	2019-06-04
Highly Integrated Scalable, Flexible Dsp Megamodule Architecture App 20190146790 - Anderson; Timothy D. ; et al.	2019-05-16
Cache Management Operations Using Streaming Engine App 20190095204 - Zbiciak; Joseph Raymond Michael ; et al.	2019-03-28
Cache Preload Operations Using Streaming Engine App 20190095205 - Zbiciak; Joseph Raymond Michael ; et al.	2019-03-28
Flexible Hybrid Firewall Architecture App 20190058691 - Mundra; Amritpal Singh ; et al.	2019-02-21
Highly integrated scalable, flexible DSP megamodule architecture Grant 10,162,641 - Anderson , et al. Dec	2018-12-25
Streaming Engine With Deferred Exception Reporting App 20180365122 - Zbiciak; Joseph ; et al.	2018-12-20
Secure Master And Secure Guest Endpoint Security Firewall App 20180357448 - Anderson; Timothy D. ; et al.	2018-12-13
Multicore Bus Architecture With Non-blocking High Performance Transaction Credit System App 20180293199 - THOMPSON; David M. ; et al.	2018-10-11
Implementing Fundamental Computational Primitives Using A Matrix Multiplication Accelerator (MMA) App 20180253402 - Redfern; Arthur John ; et al.	2018-09-06
Reconfigurable Matrix Multiplier System And Method App 20180246855 - Redfern; Arthur John ; et al.	2018-08-30
Streaming engine with deferred exception reporting Grant 10,061,675 - Zbiciak , et al. August 28, 2	2018-08-28
Slot/sub-slot Prefetch Architecture For Multiple Memory Requestors App 20180239710 - CHIRCA; Kai ; et al.	2018-08-23
Secure master and secure guest endpoint security firewall Grant 10,037,439 - Anderson , et al. July 31, 2	2018-07-31
Multicore bus architecture with non-blocking high performance transaction credit system Grant 9,904,645 - Thompson , et al. February 27, 2	2018-02-27
Slot/sub-slot prefetch architecture for multiple memory requestors Grant 9,898,415 - Chirca , et al. February 20, 2	2018-02-20
Highly Integrated Scalable, Flexible Dsp Megamodule Architecture App 20170153890 - Anderson; Timothy D. ; et al.	2017-06-01
Multicore, multibank, fully concurrent coherence controller Grant 9,652,404 - Pierson , et al. May 16, 2	2017-05-16
Highly integrated scalable, flexible DSP megamodule architecture Grant 9,606,803 - Anderson , et al. March 28, 2	2017-03-28
Protection of memories, datapath and pipeline registers, and other storage elements by distributed delayed detection and correction of soft errors Grant 9,557,936 - Anderson , et al. January 31, 2	2017-01-31
Multi-master cache coherent speculation aware memory controller with advanced arbitration, virtualization and EDC Grant 9,489,314 - Chirca , et al. November 8, 2	2016-11-08
Multi processor multi domain conversion bridge with out of order return buffering Grant 9,465,741 - Chirca , et al. October 11, 2	2016-10-11
Multi-processor, multi-domain, multi-protocol cache coherent speculation aware shared memory controller and interconnect Grant 9,465,767 - Chirca , et al. October 11, 2	2016-10-11
Synchronizing barrier support with zero performance impact Grant 9,465,742 - Wu , et al. October 11, 2	2016-10-11
Three-term predictive adder and/or subtracter Grant 9,448,767 - Anderson , et al. September 20, 2	2016-09-20
Flexible arbitration scheme for multi endpoint atomic accesses in multicore systems Grant 9,424,193 - Chirca , et al. August 23, 2	2016-08-23
Protection Of Memories, Datapath And Pipeline Registers, And Other Storage Elements By Distributed Delayed Detection And Correction Of Soft Errors App 20160188408 - Anderson; Timothy ; et al.	2016-06-30
Optimum cache access scheme for multi endpoint atomic access in a multicore system Grant 9,372,796 - Chirca , et al. June 21, 2	2016-06-21
Deadlock-avoiding coherent system on chip interconnect Grant 9,372,808 - Pierson , et al. June 21, 2	2016-06-21
Coherent cache system with optional acknowledgement for out-of-order coherence transaction completion Grant 9,372,799 - Wu , et al. June 21, 2	2016-06-21
Multicore, Multibank, Fully Concurrent Coherence Controller App 20160162407 - Pierson; Matthew D. ; et al.	2016-06-09
Multicore Bus Architecture With Wire Reduction and Physical Congestion Minimization Via Shared Transaction Channels App 20160124890 - Thompson; David M. ; et al.	2016-05-05
Multicore Bus Architecture With Non-Blocking High Performance Transaction Credit System App 20160124883 - Thompson; David M. ; et al.	2016-05-05
Distributed data return buffer for coherence system with speculative address support Grant 9,304,925 - Chirca , et al. April 5, 2	2016-04-05
Multi processor bridge with mixed Endian mode support Grant 9,304,954 - Wu , et al. April 5, 2	2016-04-05
Multicore, multibank, fully concurrent coherence controller Grant 9,298,665 - Pierson , et al. March 29, 2	2016-03-29
Flexible Arbitration Scheme For Multi Endpoint Atomic Accesses In Multicore Systems App 20160062887 - Chirca; Kai ; et al.	2016-03-03
Multi-Processor, Multi-Domain, Multi-Protocol Cache Coherent Speculation Aware Shared Memory Controller and Interconnect App 20160055096 - Chirca; Kai ; et al.	2016-02-25
Prefetcher with arbitrary downstream prefetch cancelation Grant 9,239,798 - Pierson , et al. January 19, 2	2016-01-19
Optional Acknowledgement For Out-of-order Coherence Transaction Completion App 20150370710 - Wu; Daniel B. ; et al.	2015-12-24
Flexible arbitration scheme for multi endpoint atomic accesses in multicore systems Grant 9,213,656 - Chirca , et al. December 15, 2	2015-12-15
Multi-processor, multi-domain, multi-protocol cache coherent speculation aware shared memory controller and interconnect Grant 9,208,120 - Chirca , et al. December 8, 2	2015-12-08
Coherent cache system with optional acknowledgement for out-of-order coherence transaction completion Grant 9,152,586 - Wu , et al. October 6, 2	2015-10-06
Coherence controller slot architecture allowing zero latency write commit Grant 9,129,071 - Pierson , et al. September 8, 2	2015-09-08
Hazard detection and elimination for coherent endpoint allowing out-of-order execution Grant 9,075,928 - Pierson , et al. July 7, 2	2015-07-07
Prefetch stream filter with FIFO allocation and stream direction prediction Grant 8,977,819 - Chirca , et al. March 10, 2	2015-03-10
Highly Integrated Scalable, Flexible DSP Megamodule Architecture App 20150019840 - Anderson; Timothy D. ; et al.	2015-01-15
Multistream prefetch buffer Grant 8,880,847 - Chirca November 4, 2	2014-11-04
Three-Term Predictive Adder and/or Subtracter App 20140181165 - Anderson; Timothy D. ; et al.	2014-06-26
Multicore, Multibank, Fully Concurrent Coherence Controller App 20140156951 - Pierson; Matthew D. ; et al.	2014-06-05
Multi-Processor, Multi-Domain, Multi-Protocol Cache Coherent Speculation Aware Shared Memory Controller and Interconnect App 20140149690 - Chirca; Kai ; et al.	2014-05-29
Flexible Arbitration Scheme For Multi Endpoint Atomic Accesses In Multicore Systems App 20140143486 - Chirca; Kai ; et al.	2014-05-22
Secure Master and Secure Guest Endpoint Security Firewall App 20140143849 - Anderson; Timothy D. ; et al.	2014-05-22
Multilayer arbitration for access to multiple destinations Grant 8,732,370 - Chirca , et al. May 20, 2	2014-05-20
Memory controller with automatic error detection and correction Grant 8,732,551 - Chirca , et al. May 20, 2	2014-05-20
Three-term predictive adder and/or subtracter Grant 8,713,086 - Anderson , et al. April 29, 2	2014-04-29
Coherence Controller Slot Architecture Allowing Zero Latency Write Commit App 20140115271 - Pierson; Matthew D. ; et al.	2014-04-24
Distributed Data Return Buffer For Coherence System With Speculative Address Support App 20140115273 - Chirca; Kai ; et al.	2014-04-24
Optional Acknowledgement For Out-of-order Coherence Transaction Completion App 20140115266 - Wu; Daniel B ; et al.	2014-04-24
Synchronizing Barrier Support With Zero Performance Impact App 20140115220 - Wu; Daniel B. ; et al.	2014-04-24
Deadlock-Avoiding Coherent System On Chip Interconnect App 20140115272 - Pierson; Matthew D. ; et al.	2014-04-24
Hazard Detection and Elimination for Coherent Endpoint Allowing Out-of-Order Execution App 20140115267 - Pierson; Matthew D ; et al.	2014-04-24
Multi-Master Cache Coherent Speculation Aware Memory Controller with Advanced Arbitration, Virtualization and EDC App 20140115279 - Chirca; Kai ; et al.	2014-04-24
Optimum Cache Access Scheme For Multi Endpoint Atomic Access In A Multicore System App 20140115265 - Chirca; Kai ; et al.	2014-04-24
Multi Processor Bridge With Mixed Endian Mode Support App 20140115270 - Wu; Daniel B. ; et al.	2014-04-24
Multi Processor Multi Domain Conversion Bridge with Out of Order Return Buffering App 20140115210 - Chirca; Kai ; et al.	2014-04-24
High fairness variable priority arbitration method Grant 8,706,940 - Chirca , et al. April 22, 2	2014-04-22
Variable line size prefetcher for multiple memory requestors Grant 8,706,969 - Anderson , et al. April 22, 2	2014-04-22
Speculation-aware memory controller arbiter Grant 8,601,221 - Chirca , et al. December 3, 2	2013-12-03
Predictive sequential prefetching for data caching Grant 8,473,689 - Anderson , et al. June 25, 2	2013-06-25
Three-term Predictive Adder And/or Subtracter App 20130013656 - Anderson; Timothy D. ; et al.	2013-01-10
High Fairness Variable Priority Arbitration Method App 20120317322 - Chirca; Kai ; et al.	2012-12-13
Multistream Prefetch Buffer App 20120079202 - Chirca; Kai	2012-03-29
Memory Controller With Automatic Error Detection And Correction App 20120072796 - Chirca; Kai ; et al.	2012-03-22
Variable Line Size Prefetcher For Multiple Memory Requestors App 20120072667 - Anderson; Timothy D. ; et al.	2012-03-22
Prefetch Stream Filter With Fifo Allocation And Stream Direction Prediction App 20120072671 - Chirca; Kai ; et al.	2012-03-22
Slot/sub-slot Prefetch Architecture For Multiple Memory Requestors App 20120072668 - Chirca; Kai ; et al.	2012-03-22
Speculation-aware Memory Controller Arbiter App 20120072673 - Chirca; Kai ; et al.	2012-03-22
Multilayer Arbitration for Access to Multiple Destinations App 20120072631 - Chirca; Kai ; et al.	2012-03-22
Prefetcher With Arbitrary Downstream Prefetch Cancelation App 20120072702 - Pierson; Matthew D. ; et al.	2012-03-22
Fast address translation for linear and circular modes Grant 8,117,422 - Anderson , et al. February 14, 2	2012-02-14
Predictive Sequential Prefetching For Data Caching App 20120030431 - ANDERSON; Timothy D. ; et al.	2012-02-02
Fast Address Translation for Linear and Circular Modes App 20100199064 - Anderson; Timothy D. ; et al.	2010-08-05
Arithmetic circuit with balanced logic levels for low-power operation Grant 7,349,938 - Chirca , et al. March 25, 2	2008-03-25
Arithmetic circuit with balanced logic levels for low-power operation App 20050203983 - Chirca, Kai ; et al.	2005-09-15

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