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Standard-cell layout structure with horn power and smart metal cut
Grant 11,437,321 - Fan , et al. September 6, 2 | 2022-09-06 |
Integrated circuit and method of manufacturing same
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Methods Of Resistance And Capacitance Reduction To Circuit Output Nodes
App 20220238515 - LAI; Po-Chia ; et al. | 2022-07-28 |
Transmission Gate Manufacturing Method
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Methods of resistance and capacitance reduction to circuit output nodes
Grant 11,309,311 - Lai , et al. April 19, 2 | 2022-04-19 |
Transmission gate structure and method
Grant 11,295,055 - Chien , et al. April 5, 2 | 2022-04-05 |
Semiconductor Device
App 20220102363 - XIAO; You-Cheng ; et al. | 2022-03-31 |
Method For Generating A Layout Diagram Of A Semiconductor Device Including Power-grid-adapted Route-spacing
App 20220075923 - TIEN; Li-Chun ; et al. | 2022-03-10 |
Integrated circuit layout and method of configuring the same
Grant 11,239,228 - Lin , et al. February 1, 2 | 2022-02-01 |
Multi-bit standard cell
Grant 11,227,084 - Kao , et al. January 18, 2 | 2022-01-18 |
Connection structure for stacked substrates
Grant 11,217,553 - Tseng , et al. January 4, 2 | 2022-01-04 |
Integrated Circuit Structure
App 20210374323 - ZHUANG; Hui-Zhong ; et al. | 2021-12-02 |
Semiconductor device including power-grid-adapted route-spacing and method for generating layout diagram of same
Grant 11,182,529 - Tien , et al. November 23, 2 | 2021-11-23 |
Odd-fin height cell regions, semiconductor device having the same, and method of generating a layout diagram corresponding to the same
Grant 11,177,256 - Zhuang , et al. November 16, 2 | 2021-11-16 |
Power Rail With Non-linear Edge
App 20210350062 - YANG; Jung-Chan ; et al. | 2021-11-11 |
Semiconductor Device And Layout Design Thereof
App 20210343636 - Lin; Chung-Te ; et al. | 2021-11-04 |
Method Of Designing An Integrated Circuit And Integrated Circuit
App 20210326511 - LI; Jian-Sing ; et al. | 2021-10-21 |
Integrated Circuit Having Fins Crossing Cell Boundary
App 20210313319 - SUE; Pin-Dai ; et al. | 2021-10-07 |
Method of modifying cell, system for modifying cell and global connection routing method
Grant 11,132,488 - Chen , et al. September 28, 2 | 2021-09-28 |
Flip-flop With Delineated Layout For Reduced Footprint
App 20210297068 - Liu; Chi-Lin ; et al. | 2021-09-23 |
Method For Manufacturing Standard Cell Regions And Engineering Change Order (eco) Cell Regions
App 20210286928 - TIEN; Li-Chun ; et al. | 2021-09-16 |
Double Height Cell Regions, Semiconductor Device Having The Same, And Method Of Generating A Layout Diagram Corresponding To The Same
App 20210288144 - YANG; Jung-Chan ; et al. | 2021-09-16 |
Inverted Integrated Circuit And Method Of Forming The Same
App 20210279397 - WANG; Pochun ; et al. | 2021-09-09 |
Integrated Circuit Having Angled Conductive Feature
App 20210280572 - HSIEH; Tung-Heng ; et al. | 2021-09-09 |
Semiconductor Structure
App 20210280608 - CHOU; HSUEH-CHIH ; et al. | 2021-09-09 |
Semiconductor Device
App 20210273093 - Lu; Ze-Sian ; et al. | 2021-09-02 |
Pin Modification For Standard Cells
App 20210265336 - CHANG; Fong-yuan ; et al. | 2021-08-26 |
Power rail with non-linear edge
Grant 11,093,684 - Yang , et al. August 17, 2 | 2021-08-17 |
Methods Of Resistance And Capacitance Reduction To Circuit Output Nodes
App 20210249407 - LAI; Po-Chia ; et al. | 2021-08-12 |
Semiconductor device and layout design thereof
Grant 11,088,067 - Lin , et al. August 10, 2 | 2021-08-10 |
Buried Metal Track and Methods Forming Same
App 20210242212 - Wang; Pochun ; et al. | 2021-08-05 |
Method for improved cut metal patterning
Grant 11,080,461 - Chang , et al. August 3, 2 | 2021-08-03 |
Method of designing an integrated circuit and integrated circuit
Grant 11,074,390 - Li , et al. July 27, 2 | 2021-07-27 |
Semiconductor device including a conductive feature over an active region
Grant 11,075,164 - Hsieh , et al. July 27, 2 | 2021-07-27 |
Method And System For Generating Layout Diagram For Semiconductor Device Having Engineering Change Order (eco) Cells
App 20210224444 - CHIU; Mao-Wei ; et al. | 2021-07-22 |
Power Switch Circuit, Ic Structure Of Power Switch Circuit, And Method Of Forming Ic Structure
App 20210218398 - HUNG; TZUNG-YO ; et al. | 2021-07-15 |
Integrated Circuit Layout Method And System
App 20210209284 - LI; Jian-Sing ; et al. | 2021-07-08 |
Integrated circuit and method of manufacturing the same
Grant 11,048,849 - Wang , et al. June 29, 2 | 2021-06-29 |
Flip-flop with delineated layout for reduced footprint
Grant 11,050,415 - Liu , et al. June 29, 2 | 2021-06-29 |
Semiconductor structure
Grant 11,037,957 - Chou , et al. June 15, 2 | 2021-06-15 |
Pin modification for standard cells
Grant 11,037,920 - Chang , et al. June 15, 2 | 2021-06-15 |
System for generating standard cell layout having engineering change order (ECO) cells
Grant 11,030,373 - Tien , et al. June 8, 2 | 2021-06-08 |
Semiconductor device including a conductive feature over an active region
Grant 11,031,334 - Hsieh , et al. June 8, 2 | 2021-06-08 |
Integrated circuit having angled conductive feature
Grant 11,024,622 - Hsieh , et al. June 1, 2 | 2021-06-01 |
Buried metal track and methods forming same
Grant 11,004,855 - Wang , et al. May 11, 2 | 2021-05-11 |
Semiconductor Device
App 20210134947 - YANG; JUNG-CHAN ; et al. | 2021-05-06 |
Integrated Circuit And Method Of Manufacturing Same
App 20210124866 - CHIANG; Ting-Wei ; et al. | 2021-04-29 |
Double height cell regions, semiconductor device having the same, and method of generating a layout diagram corresponding to the same
Grant 10,971,586 - Yang , et al. April 6, 2 | 2021-04-06 |
Integrated circuit layout method, device, and system
Grant 10,970,451 - Li , et al. April 6, 2 | 2021-04-06 |
Method and system for generating layout diagram for semiconductor device having engineering change order (ECO) cells
Grant 10,970,440 - Chiu , et al. April 6, 2 | 2021-04-06 |
Transmission Gate Structure And Method
App 20210089702 - CHIEN; Shao-Lun ; et al. | 2021-03-25 |
System For Designing Integrated Circuit Layout And Method Of Making The Integrated Circuit Layout
App 20210089698 - HSIEH; Shang-Chih ; et al. | 2021-03-25 |
Isolation Circuit Between Power Domains
App 20210089700 - LU; Chi-Yu ; et al. | 2021-03-25 |
Semiconductor Device And Layout Thereof
App 20210082904 - HUANG; Cheng-I ; et al. | 2021-03-18 |
Integrated Circuit, System For And Method Of Forming An Integrated Circuit
App 20210082739 - YANG; Jung-Chan ; et al. | 2021-03-18 |
Integrated circuit and method of fabricating the same
Grant 10,950,594 - Lin , et al. March 16, 2 | 2021-03-16 |
Standard-cell layout structure with horn power and smart metal cut
Grant 10,923,426 - Fan , et al. February 16, 2 | 2021-02-16 |
Method Of Designing A Device
App 20210034807 - CHEN; Sheng-Hsiung ; et al. | 2021-02-04 |
Method For Improved Cut Metal Patterning
App 20210004518 - CHANG; Kuang-Ching ; et al. | 2021-01-07 |
Integrated circuit and method of manufacturing same
Grant 10,885,254 - Chiang , et al. January 5, 2 | 2021-01-05 |
Semiconductor Device
App 20200411516 - SUE; Pin-Dai ; et al. | 2020-12-31 |
Tie Off Device
App 20200402979 - Chien; Shao-Lun ; et al. | 2020-12-24 |
Transmission gate structure, layout, methods, and system
Grant 10,867,113 - Chien , et al. December 15, 2 | 2020-12-15 |
Integrated circuit and method of forming an integrated circuit
Grant 10,867,114 - Zhuang , et al. December 15, 2 | 2020-12-15 |
Isolation circuit between power domains
Grant 10,867,104 - Lu , et al. December 15, 2 | 2020-12-15 |
Integrated circuit designing system
Grant 10,867,100 - Hsieh , et al. December 15, 2 | 2020-12-15 |
System for designing integrated circuit layout and method of making the integrated circuit layout
Grant 10,867,099 - Hsieh , et al. December 15, 2 | 2020-12-15 |
Integrated circuit, system for and method of forming an integrated circuit
Grant 10,854,499 - Yang , et al. December 1, 2 | 2020-12-01 |
Semiconductor device and layout thereof
Grant 10,854,593 - Huang , et al. December 1, 2 | 2020-12-01 |
Integrated Circuit And Method Of Manufacturing Same
App 20200350250 - WANG; Pochun ; et al. | 2020-11-05 |
Integrated Circuit Layout and Method of Configuring the Same
App 20200335489 - Lin; Chung-Te ; et al. | 2020-10-22 |
Semiconductor Device and Layout Design Thereof
App 20200328148 - Lin; Chung-Te ; et al. | 2020-10-15 |
Integrated Circuit, System For And Method Of Forming An Integrated Circuit
App 20200320244 - YANG; Jung-Chan ; et al. | 2020-10-08 |
Method and system for pin layout
Grant 10,796,060 - Chang , et al. October 6, 2 | 2020-10-06 |
Method And System For Generating Layout Diagram For Semiconductor Device Having Engineering Change Order (eco) Cells
App 20200302101 - CHIU; Mao-Wei ; et al. | 2020-09-24 |
Method for improved cut metal patterning
Grant 10,783,313 - Chang , et al. Sept | 2020-09-22 |
Semiconductor Structure
App 20200286919 - CHOU; HSUEH-CHIH ; et al. | 2020-09-10 |
Integrated circuit, system for and method of forming an integrated circuit
Grant 10,740,531 - Yang , et al. A | 2020-08-11 |
Integrated circuit and method of manufacturing same
Grant 10,734,321 - Wang , et al. | 2020-08-04 |
Standard-cell Layout Structure With Horn Power And Smart Metal Cut
App 20200243446 - Fan; Ni-Wan ; et al. | 2020-07-30 |
Semiconductor device and layout design thereof
Grant 10,727,177 - Lin , et al. | 2020-07-28 |
Integrated circuit layout and method of configuring the same
Grant 10,707,199 - Lin , et al. | 2020-07-07 |
Semiconductor structure
Grant 10,685,982 - Chou , et al. | 2020-06-16 |
System For Generating Standard Cell Layout Having Engineering Change Order (eco) Cells
App 20200184138 - TIEN; Li-Chun ; et al. | 2020-06-11 |
Semiconductor device having engineering change order (ECO) cells
Grant 10,678,977 - Chiu , et al. | 2020-06-09 |
Standard-cell layout structure with horn power and smart metal cut
Grant 10,672,708 - Fan , et al. | 2020-06-02 |
Method Of Modifying Cell, System For Modifying Cell And Global Connection Routing Method
App 20200167518 - CHEN; Sheng-Hsiung ; et al. | 2020-05-28 |
Multi-bit Standard Cell
App 20200151297 - KAO; JERRY CHANG JUI ; et al. | 2020-05-14 |
Pin Modification For Standard Cells
App 20200152617 - CHANG; Fong-Yuan ; et al. | 2020-05-14 |
Integrated Circuit And Method Of Manufacturing The Same
App 20200134123 - WANG; Pochun ; et al. | 2020-04-30 |
Power Rail With Non-linear Edge
App 20200134133 - YANG; Jung-Chan ; et al. | 2020-04-30 |
Integrated Circuit Having Angled Conductive Feature
App 20200126966 - HSIEH; Tung-Heng ; et al. | 2020-04-23 |
Method Of Designing An Integrated Circuit And Integrated Circuit
App 20200104450 - LI; Chien-Hsing ; et al. | 2020-04-02 |
Integrated Circuit Layout Method, Device, And System
App 20200104446 - LI; Jian-Sing ; et al. | 2020-04-02 |
Flip-flop With Delineated Layout For Reduced Footprint
App 20200099369 - Liu; Chi-Lin ; et al. | 2020-03-26 |
Transmission Gate Structure, Layout, Methods, And System
App 20200082052 - CHIEN; Shao-Lun ; et al. | 2020-03-12 |
Semiconductor Device including a Conductive Feature Over an Active Region
App 20200075476 - Hsieh; Tung-Heng ; et al. | 2020-03-05 |
Method For Improved Cut Metal Patterning
App 20200074043 - CHANG; Kuang-Ching ; et al. | 2020-03-05 |
Isolation Circuit Between Power Domains
App 20200074039 - LU; Chi-Yu ; et al. | 2020-03-05 |
Semiconductor device having engineering change order (ECO) cells
Grant 10,565,345 - Tien , et al. Feb | 2020-02-18 |
Pin modification for standard cells
Grant 10,559,558 - Chang , et al. Feb | 2020-02-11 |
Semiconductor device having engineering change order (ECO) cells and method of using
Grant 10,553,575 - Tien , et al. Fe | 2020-02-04 |
Method of modifying cell and global connection routing method
Grant 10,552,568 - Chen , et al. Fe | 2020-02-04 |
Integrated Circuit And Method Of Forming An Integrated Circuit
App 20200034512 - ZHUANG; Hui-Zhong ; et al. | 2020-01-30 |
Connection Structure For Stacked Substrates
App 20200027853 - Tseng; Hsiang-Jen ; et al. | 2020-01-23 |
Connecting Techniques For Stacked Substrates
App 20200027854 - Tseng; Hsiang-Jen ; et al. | 2020-01-23 |
Flip-flop with delineated layout for reduced footprint
Grant 10,530,345 - Liu , et al. J | 2020-01-07 |
Double Height Cell Regions, Semiconductor Device Having The Same, And Method Of Generating A Layout Diagram Corresponding To The
App 20200006481 - YANG; Jung-Chan ; et al. | 2020-01-02 |
Odd-fin Height Cell Regions, Semiconductor Device Having The Same, And Method Of Generating A Layout Diagram Corresponding To Th
App 20200006335 - ZHUANG; Hui-Zhong ; et al. | 2020-01-02 |
Semiconductor Device Including a Conductive Feature Over an Active Region
App 20200006217 - Hsieh; Tung-Heng ; et al. | 2020-01-02 |
System and method of processing cutting layout and example switching circuit
Grant 10,522,527 - Hsieh , et al. Dec | 2019-12-31 |
Semiconductor device including a conductive feature over an active region
Grant 10,504,837 - Hsieh , et al. Dec | 2019-12-10 |
Connecting techniques for stacked CMOS devices
Grant 10,497,661 - Tseng , et al. De | 2019-12-03 |
Buried Metal Track and Methods Forming Same
App 20190341387 - Wang; Pochun ; et al. | 2019-11-07 |
Integrated Circuit Designing System
App 20190332736 - HSIEH; Shang-Chih ; et al. | 2019-10-31 |
Buried metal track and methods forming same
Grant 10,446,555 - Wang , et al. Oc | 2019-10-15 |
Semiconductor Device Including Power-grid-adapted Route-spacing And Method For Generating Layout Diagram Of Same
App 20190303527 - TIEN; Li-Chun ; et al. | 2019-10-03 |
Integrated Circuit and Method of Fabricating the Same
App 20190279975 - Lin; Chung-Te ; et al. | 2019-09-12 |
System For Designing Integrated Circuit Layout And Method Of Making The Integrated Circuit Layout
App 20190258768 - HSIEH; Shang-Chih ; et al. | 2019-08-22 |
Integrated Circuit And Method Of Manufacturing Same
App 20190251225 - CHIANG; Ting-Wei ; et al. | 2019-08-15 |
Integrated Circuit Layout and Method of Configuring the Same
App 20190252367 - Lin; Chung-Te ; et al. | 2019-08-15 |
Integrated circuit and method of forming an integrated circuit
Grant 10,380,315 - Zhuang , et al. A | 2019-08-13 |
Layout of standard cells for predetermined function in integrated circuits
Grant 10,380,306 - Hsieh , et al. A | 2019-08-13 |
Method And System For Pin Layout
App 20190243940 - CHANG; FONG-YUAN ; et al. | 2019-08-08 |
Flip-flop With Delineated Layout For Reduced Footprint
App 20190229715 - Liu; Chi-Lin ; et al. | 2019-07-25 |
Method of generating engineering change order (ECO) layout of base cell and computer-readable medium comprising executable instructions for carrying out said method
Grant 10,339,250 - Tien , et al. | 2019-07-02 |
Semiconductor device with fill cells
Grant 10,331,838 - Yang , et al. | 2019-06-25 |
Integrated circuit and method of fabricating the same
Grant 10,325,900 - Lin , et al. | 2019-06-18 |
Semiconductor Structure
App 20190164992 - CHOU; HSUEH-CHIH ; et al. | 2019-05-30 |
Integrated circuit and method of manufacturing same
Grant 10,296,694 - Chiang , et al. | 2019-05-21 |
Semiconductor Device Having Engineering Change Order (eco) Cells
App 20190147132 - CHIU; Mao-Wei ; et al. | 2019-05-16 |
System for designing integrated circuit layout and method of making the integrated circuit layout
Grant 10,289,789 - Hsieh , et al. | 2019-05-14 |
Semiconductor device layout
Grant 10,277,227 - Sue , et al. | 2019-04-30 |
Method and system for pin layout
Grant 10,268,796 - Chang , et al. | 2019-04-23 |
Integrated circuit layout and method of configuring the same
Grant 10,269,784 - Lin , et al. | 2019-04-23 |
Flip-flop with delineated layout for reduced footprint
Grant 10,270,432 - Liu , et al. | 2019-04-23 |
Standard Cell Layout, Semiconductor Device Having Engineering Change Order (eco) Cells And Method
App 20190114382 - TIEN; Li-Chun ; et al. | 2019-04-18 |
Integrated Circuit, System For And Method Of Forming An Integrated Circuit
App 20190102503 - YANG; Jung-Chan ; et al. | 2019-04-04 |
Pin Modification For Standard Cells
App 20190103392 - CHANG; Fong-yuan ; et al. | 2019-04-04 |
Semiconductor Device And Layout Thereof
App 20190103393 - HUANG; Cheng-I ; et al. | 2019-04-04 |
Integrated Circuit And Method Of Manufacturing Same
App 20190096811 - WANG; Pochun ; et al. | 2019-03-28 |
Semiconductor Device and Layout Design Thereof
App 20190067185 - Lin; Chung-Te ; et al. | 2019-02-28 |
Buried Metal Track and Methods Forming Same
App 20190067290 - Wang; Pochun ; et al. | 2019-02-28 |
Semiconductor device and layout thereof
Grant 10,163,882 - Huang , et al. Dec | 2018-12-25 |
Integrated circuit and method of fabricating the same
Grant 10,163,880 - Lin , et al. Dec | 2018-12-25 |
Circuits and structures including tap cells and fabrication methods thereof
Grant 10,157,910 - Xu , et al. Dec | 2018-12-18 |
Semiconductor devices with cells comprising routing resources
Grant 10,157,902 - Chiu , et al. Dec | 2018-12-18 |
Standard-cell Layout Structure With Horn Power And Smart Metal Cut
App 20180350743 - Fan; Ni-Wan ; et al. | 2018-12-06 |
Semiconductor device and layout design thereof
Grant 10,141,256 - Lin , et al. Nov | 2018-11-27 |
Integrated Circuit and Method of Fabricating the Same
App 20180337167 - Lin; Chung-Te ; et al. | 2018-11-22 |
Standard cell layout, semiconductor device having engineering change order (ECO) cells and method
Grant 10,127,340 - Chiu , et al. November 13, 2 | 2018-11-13 |
Gate pad layout patterns for masks and structures
Grant 10,007,750 - Chiang , et al. June 26, 2 | 2018-06-26 |
Semiconductor Device With Fill Cells
App 20180165399 - YANG; Jung-Chan ; et al. | 2018-06-14 |
Semiconductor device, layout of semiconductor device, and method of manufacturing semiconductor device
Grant 9,991,158 - Hsieh , et al. June 5, 2 | 2018-06-05 |
Standard Cell Layout, Semiconductor Device Having Engineering Change Order (eco) Cells And Method
App 20180150586 - TIEN; Li-Chun ; et al. | 2018-05-31 |
Integrated Circuit, System For And Method Of Forming An Integrated Circuit
App 20180150589 - YANG; Jung-Chan ; et al. | 2018-05-31 |
Integrated Circuit, System For And Method Of Forming An Integrated Circuit
App 20180151411 - YANG; Jung-Chan ; et al. | 2018-05-31 |
Method Of Modifying Cell And Global Connection Routing Method
App 20180107780 - CHEN; Sheng-Hsiung ; et al. | 2018-04-19 |
Connecting Techniques For Stacked Cmos Devices
App 20180108635 - Tseng; Hsiang-Jen ; et al. | 2018-04-19 |
Standard Cell Layout, Semiconductor Device Having Engineering Change Order (eco) Cells And Method
App 20180096981 - CHIU; Mao-Wei ; et al. | 2018-04-05 |
Integrated Circuit And Method Of Forming An Integrated Circuit
App 20180075182 - ZHUANG; Hui-Zhong ; et al. | 2018-03-15 |
Semiconductor Device Having Engineering Change Order (eco) Cells And Method Of Using
App 20180076190 - TIEN; Li-Chun ; et al. | 2018-03-15 |
Method And System For Pin Layout
App 20180075181 - CHANG; FONG-YUAN ; et al. | 2018-03-15 |
Method of forming layout design
Grant 9,899,263 - Hsieh , et al. February 20, 2 | 2018-02-20 |
FinFET with an asymmetric source/drain structure and method of making same
Grant 9,882,002 - Tseng , et al. January 30, 2 | 2018-01-30 |
Integrated Circuit Layout And Method Of Configuring The Same
App 20180006009 - LIN; Chung-Te ; et al. | 2018-01-04 |
Integrated Circuit And Method Of Manufacturing Same
App 20180004884 - CHIANG; Ting-Wei ; et al. | 2018-01-04 |
Connecting techniques for stacked CMOS devices
Grant 9,853,008 - Tseng , et al. December 26, 2 | 2017-12-26 |
Global connection routing method and system for performing the same
Grant 9,846,759 - Chen , et al. December 19, 2 | 2017-12-19 |
Cell grid architecture for FinFET technology
Grant 9,846,757 - Zhuang , et al. December 19, 2 | 2017-12-19 |
Semiconductor Devices With Cells Comprising Routing Resources
App 20170345810 - CHIU; MAO-WEI ; et al. | 2017-11-30 |
Semiconductor Device Layout
App 20170346490 - Sue; Pin-Dai ; et al. | 2017-11-30 |
Standard cell layout, semiconductor device having engineering change order (ECO) cells and method
Grant 9,831,230 - Tien , et al. November 28, 2 | 2017-11-28 |
Integrated Circuit And Method Of Fabricating The Same
App 20170323877 - LIN; Chung-Te ; et al. | 2017-11-09 |
Flip-flop With Delineated Layout For Reduced Footprint
App 20170317666 - Liu; Chi-Lin ; et al. | 2017-11-02 |
Integrated circuit with elongated coupling
Grant 9,806,071 - Hsieh , et al. October 31, 2 | 2017-10-31 |
Semiconductor Device And Layout Design Thereof
App 20170309562 - LIN; Chung-Te ; et al. | 2017-10-26 |
System and method of layout design for integrated circuits
Grant 9,767,243 - Chiang , et al. September 19, 2 | 2017-09-19 |
Gate Pad Layout Patterns For Masks And Structures
App 20170262566 - CHIANG; Ting-Wei ; et al. | 2017-09-14 |
System For Designing Integrated Circuit Layout And Method Of Making The Integrated Circuit Layout
App 20170255739 - HSIEH; Shang-Chih ; et al. | 2017-09-07 |
Circuits and Structures Including Tap Cells and Fabrication Methods Thereof
App 20170194319 - XU; JIN-WEI ; et al. | 2017-07-06 |
Masks based on gate pad layout patterns of standard cell having different gate pad pitches
Grant 9,690,892 - Chiang , et al. June 27, 2 | 2017-06-27 |
Semiconductor device and layout method thereof
Grant 9,691,750 - Chou , et al. June 27, 2 | 2017-06-27 |
Semiconductor Device And Layout Thereof
App 20170179105 - HUANG; Cheng-I ; et al. | 2017-06-22 |
Standard-cell Layout Structure With Horn Power And Smart Metal Cut
App 20170154848 - Fan; Ni-Wan ; et al. | 2017-06-01 |
Standard cell having cell height being non-integral multiple of nominal minimum pitch
Grant 9,659,129 - Hsieh , et al. May 23, 2 | 2017-05-23 |
Method and layout of an integrated circuit
Grant 9,653,393 - Chen , et al. May 16, 2 | 2017-05-16 |
Flip-flop with delineated layout for reduced footprint
Grant 9,641,161 - Liu , et al. May 2, 2 | 2017-05-02 |
Method and system of forming layout design
Grant 9,626,472 - Chiang , et al. April 18, 2 | 2017-04-18 |
Layout Of Standard Cells For Predetermined Function In Integrated Circuits
App 20170068767 - HSIEH; Shang-Chih ; et al. | 2017-03-09 |
Cell Grid Architecture For Finfet Technology
App 20170061056 - ZHUANG; Hui-Zhong ; et al. | 2017-03-02 |
Global Connection Routing Method And System For Performing The Same
App 20170032073 - CHEN; Sheng-Hsiung ; et al. | 2017-02-02 |
Method and system of layout placement based on multilayer gridlines
Grant 9,536,032 - Chiang , et al. January 3, 2 | 2017-01-03 |
Integrated Circuit with Elongated Coupling
App 20160358902 - Hsieh; Tung-Heng ; et al. | 2016-12-08 |
System And Method Of Processing Cutting Layout And Example Switching Circuit
App 20160351555 - HSIEH; Tung-Heng ; et al. | 2016-12-01 |
Semiconductor Device and Method of Manufacturing Semiconductor Device
App 20160343656 - Hsieh; Tung-Heng ; et al. | 2016-11-24 |
Standard cells for predetermined function having different types of layout
Grant 9,501,600 - Hsieh , et al. November 22, 2 | 2016-11-22 |
Connecting Techniques For Stacked Cmos Devices
App 20160336289 - Tseng; Hsiang-Jen ; et al. | 2016-11-17 |
Contact Structure Of Semiconductor Device
App 20160329405 - Tseng; Hsiang-Jen ; et al. | 2016-11-10 |
Integrated circuit with multiple cells having different heights
Grant 9,478,609 - Chiang , et al. October 25, 2 | 2016-10-25 |
Connecting techniques for stacked CMOS devices
Grant 9,443,758 - Tseng , et al. September 13, 2 | 2016-09-13 |
Method of Forming Layout Design
App 20160254190 - Hsieh; Tung-Heng ; et al. | 2016-09-01 |
System and method of processing cutting layout and example switching circuit
Grant 9,431,381 - Hsieh , et al. August 30, 2 | 2016-08-30 |
Integrated circuit with elongated coupling
Grant 9,425,141 - Hsieh , et al. August 23, 2 | 2016-08-23 |
Semiconductor device and method of manufacturing semiconductor device
Grant 9,412,700 - Hsieh , et al. August 9, 2 | 2016-08-09 |
Semiconductor Device And Layout Method Thereof
App 20160225752 - CHOU; TING-WEI ; et al. | 2016-08-04 |
Method And System Of Forming Layout Design
App 20160147927 - CHIANG; Ting-Wei ; et al. | 2016-05-26 |
Method And System Of Forming Layout Design
App 20160147926 - CHIANG; Ting-Wei ; et al. | 2016-05-26 |
Method of forming layout design
Grant 9,336,348 - Hsieh , et al. May 10, 2 | 2016-05-10 |
FinFET with an Asymmetric Source/Drain Structure and Method of Making Same
App 20160118462 - Tseng; Hsiang-Jen ; et al. | 2016-04-28 |
Method and layout of an integrated circuit
Grant 9,323,881 - Tseng , et al. April 26, 2 | 2016-04-26 |
Semiconductor Device And Method Of Manufacturing Semiconductor Device
App 20160111370 - HSIEH; Tung-Heng ; et al. | 2016-04-21 |
Integrated Circuit With Elongated Coupling
App 20160104674 - HSIEH; Tung-Heng ; et al. | 2016-04-14 |
System And Method Of Processing Cutting Layout And Example Switching Circuit
App 20160093603 - HSIEH; Tung-Heng ; et al. | 2016-03-31 |
Semiconductor Device, Layout Of Semiconductor Device, And Method Of Manufacturing Semiconductor Device
App 20160079162 - HSIEH; Tung-Heng ; et al. | 2016-03-17 |
Method Of Forming Layout Design
App 20160078164 - HSIEH; Tung-Heng ; et al. | 2016-03-17 |
Method and layout of an integrated circuit
Grant 9,245,887 - Chiang , et al. January 26, 2 | 2016-01-26 |
Integrated Circuit With Multiple Cells Having Different Heights
App 20160013271 - CHIANG; Ting-Wei ; et al. | 2016-01-14 |
Gate Pad Layout Patterns Of Standard Cell Having Different Gate Pad Pitches
App 20160012169 - CHIANG; Ting-Wei ; et al. | 2016-01-14 |
FinFET with an asymmetric source/drain structure and method of making same
Grant 9,231,106 - Tseng , et al. January 5, 2 | 2016-01-05 |
System And Method Of Layout Design For Integrated Circuits
App 20150347659 - CHIANG; Ting-Wei ; et al. | 2015-12-03 |
Standard cell metal structure directly over polysilicon structure
Grant 9,158,877 - Hsieh , et al. October 13, 2 | 2015-10-13 |
Layout of an integrated circuit
Grant 9,098,668 - Tien , et al. August 4, 2 | 2015-08-04 |
Method and Layout of an Integrated Circuit
App 20150171005 - Chen; Wei-Yu ; et al. | 2015-06-18 |
Connecting Techniques For Stacked Cmos Devices
App 20150162295 - Tseng; Hsiang-Jen ; et al. | 2015-06-11 |
Layout Of An Integrated Circuit
App 20150149976 - Tien; Li-Chun ; et al. | 2015-05-28 |
Standard Cell Layout, Semiconductor Device Having Engineering Change Order (eco) Cells And Method
App 20150048424 - TIEN; Li-Chun ; et al. | 2015-02-19 |
Method And Layout Of An Integrated Circuit
App 20150035070 - Chiang; Ting-Wei ; et al. | 2015-02-05 |
Method And Layout Of An Integrated Circuit
App 20140332971 - TSENG; Hsiang-Jen ; et al. | 2014-11-13 |
Standard Cell Metal Structure Directly Over Polysilicon Structure
App 20140327081 - HSIEH; Shang-Chih ; et al. | 2014-11-06 |
Standard Cell Having Cell Height Being Non-integral Multiple Of Nominal Minimum Pitch
App 20140327050 - HSIEH; Shang-Chih ; et al. | 2014-11-06 |
Standard Cells For Predetermined Function Having Different Types Of Layout
App 20140327471 - HSIEH; Shang-Chih ; et al. | 2014-11-06 |
FinFET with an Asymmetric Source/Drain Structure and Method of Making Same
App 20140252477 - Tseng; Hsiang-Jen ; et al. | 2014-09-11 |
Method and layout of an integrated circuit
Grant 8,819,610 - Tseng , et al. August 26, 2 | 2014-08-26 |
Method And Layout Of An Integrated Circuit
App 20140195997 - TSENG; Hsiang-Jen ; et al. | 2014-07-10 |
Actuating apparatus, actuating system and method for actuating a working stage to move relative to a platform with high-precision positioning capability
Grant 8,605,294 - Hwang , et al. December 10, 2 | 2013-12-10 |
Actuating Apparatus, Actuating System And Method For Actuating A Working Stage To Move Relative To A Platform With High-Precision Positioning Capability
App 20130235389 - Hwang; Yi-Yuh ; et al. | 2013-09-12 |
Method and system for positioning by using optical speckle
Grant 8,144,339 - Hwang , et al. March 27, 2 | 2012-03-27 |
Movable touchpad with high sensitivity
Grant 8,125,449 - Liao , et al. February 28, 2 | 2012-02-28 |
Method And System For Determining Whether A To-be-identified Individual Is A Registered Individual
App 20110262012 - Liao; Chih-Ming ; et al. | 2011-10-27 |
Movable Touchpad With High Sensitivity
App 20110141014 - LIAO; Chih-Ming ; et al. | 2011-06-16 |
Method And System For Positioning By Using Optical Speckle
App 20110134434 - HWANG; Yi-Yuh ; et al. | 2011-06-09 |
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