| Patent | Date |
|---|
Reversible Resistive Memory Logic Gate Device
App 20220310908 - Chen; Hsueh-Chung ; et al. | 2022-09-29 |
Multiple patterning with mandrel cuts defined by block masks
Grant 11,417,525 - O'Toole , et al. August 16, 2 | 2022-08-16 |
Metal on metal multiple patterning
Grant 11,398,378 - Chen , et al. July 26, 2 | 2022-07-26 |
Method of forming a BEOL interconnect structure using a subtractive metal via first process
Grant 11,398,409 - Mignot , et al. July 26, 2 | 2022-07-26 |
Non Volatile Resistive Memory Logic Device
App 20220172776 - Chen; Hsueh-Chung ; et al. | 2022-06-02 |
Bi metal subtractive etch for trench and via formation
Grant 11,328,954 - Mignot , et al. May 10, 2 | 2022-05-10 |
Cut integration for subtractive first metal line with bottom up second metal line
Grant 11,302,571 - Ghosh , et al. April 12, 2 | 2022-04-12 |
Method Of Forming A Beol Interconnect Structure Using A Subtractive Metal Via First Process
App 20220093459 - Mignot; Yann ; et al. | 2022-03-24 |
Metal Via Structure
App 20220005762 - Mignot; Yann ; et al. | 2022-01-06 |
Multiple patterning scheme integration with planarized cut patterning
Grant 11,171,001 - Chen , et al. November 9, 2 | 2021-11-09 |
Barrier-free vertical interconnect structure
Grant 11,164,778 - Wang , et al. November 2, 2 | 2021-11-02 |
Metal via structure
Grant 11,152,298 - Mignot , et al. October 19, 2 | 2021-10-19 |
Wafer Backside Engineering For Wafer Stress Control
App 20210320036 - JAIN; Nikhil ; et al. | 2021-10-14 |
Multi-metal Interconnects For Semiconductor Device Structures
App 20210305160 - CHEN; Hsueh-Chung ; et al. | 2021-09-30 |
Interconnect structure
Grant 11,133,216 - Chen , et al. September 28, 2 | 2021-09-28 |
Interconnection Fabric For Buried Power Distribution
App 20210296234 - Dechene; Daniel James ; et al. | 2021-09-23 |
Bi Metal Subtractive Etch For Trench And Via Formation
App 20210287940 - Mignot; Yann ; et al. | 2021-09-16 |
Double metal double patterning with vias extending into dielectric
Grant 11,107,727 - Mignot , et al. August 31, 2 | 2021-08-31 |
Via-via Spacing Reduction Without Additional Cut Mask
App 20210265166 - Dechene; Daniel James ; et al. | 2021-08-26 |
Wet clean solutions to prevent pattern collapse
Grant 11,094,527 - Peethala , et al. August 17, 2 | 2021-08-17 |
Double replacement metal line patterning
Grant 11,087,993 - Xie , et al. August 10, 2 | 2021-08-10 |
Large via buffer
Grant 11,075,161 - Mignot , et al. July 27, 2 | 2021-07-27 |
Double metal patterning
Grant 11,069,564 - Chen , et al. July 20, 2 | 2021-07-20 |
Metal contact isolation for semiconductor structures
Grant 11,063,126 - Fan , et al. July 13, 2 | 2021-07-13 |
Metallization interconnect structure formation
Grant 11,056,426 - Mignot , et al. July 6, 2 | 2021-07-06 |
Metal replacement vertical interconnections for buried capacitance
Grant 11,024,551 - Chen , et al. June 1, 2 | 2021-06-01 |
Barrier-free Vertical Interconnect Structure
App 20210159117 - Wang; Junli ; et al. | 2021-05-27 |
Integrated circuit having a single damascene wiring network
Grant 11,004,736 - Chen , et al. May 11, 2 | 2021-05-11 |
Cut Integration For Subtractive First Metal Line With Bottom Up Second Metal Line
App 20210111066 - Ghosh; Somnath ; et al. | 2021-04-15 |
Stack viabar structures
Grant 10,971,356 - Fan , et al. April 6, 2 | 2021-04-06 |
Skip-via Proximity Interconnect
App 20210082747 - Mignot; Yann ; et al. | 2021-03-18 |
Multiple patterning scheme integration with planarized cut patterning
Grant 10,937,653 - Chen , et al. March 2, 2 | 2021-03-02 |
Double Replacement Metal Line Patterning
App 20210043462 - Xie; Ruilong ; et al. | 2021-02-11 |
Integrated Circuit Having A Single Damascene Wiring Network
App 20210020507 - Chen; Hsueh-Chung ; et al. | 2021-01-21 |
Metal On Metal Multiple Patterning
App 20210005454 - CHEN; Hsueh-Chung ; et al. | 2021-01-07 |
Large Via Buffer
App 20200395293 - MIGNOT; YANN ; et al. | 2020-12-17 |
Metal Via Structure
App 20200388567 - Mignot; Yann ; et al. | 2020-12-10 |
Metallization Interconnect Structure Formation
App 20200381354 - Mignot; Yann ; et al. | 2020-12-03 |
Double Metal Double Patterning With Vias Extending Into Dielectric
App 20200357686 - Mignot; Yann ; et al. | 2020-11-12 |
Integration of artificial intelligence devices
Grant 10,833,010 - Chen , et al. November 10, 2 | 2020-11-10 |
Metal spacer self aligned multi-patterning integration
Grant 10,825,726 - Chen , et al. November 3, 2 | 2020-11-03 |
Metal on metal multiple patterning
Grant 10,818,494 - Chen , et al. October 27, 2 | 2020-10-27 |
Metal spacer self aligned double patterning with airgap integration
Grant 10,811,310 - Chen , et al. October 20, 2 | 2020-10-20 |
Double Metal Patterning
App 20200328111 - CHEN; HSUEH-CHUNG ; et al. | 2020-10-15 |
Multiple patterning with lithographically-defined cuts
Grant 10,784,119 - Srivastava , et al. Sept | 2020-09-22 |
Metal Contact Isolation For Semiconductor Structures
App 20200279925 - Fan; Su Chen ; et al. | 2020-09-03 |
Merge mandrel features
Grant 10,741,439 - Chen , et al. A | 2020-08-11 |
Fully aligned semiconductor device with a skip-level via
Grant 10,741,751 - Lanzillo , et al. A | 2020-08-11 |
Structure and method using metal spacer for insertion of variable wide line implantation in SADP/SAQP integration
Grant 10,714,389 - Chen , et al. | 2020-07-14 |
Stack Viabar Structures
App 20200203156 - FAN; Su Chen ; et al. | 2020-06-25 |
Self-aligned Litho-etch Double Patterning
App 20200185269 - Chen; Hsueh-Chung ; et al. | 2020-06-11 |
Physical Vapor Deposition With A Dual-shutter
App 20200176235 - Chen; Hsueh-Chung ; et al. | 2020-06-04 |
Multiple patterning with late lithographically-defined mandrel cuts
Grant 10,651,046 - Chen , et al. | 2020-05-12 |
Metal Spacer Self Aligned Double Patterning With Airgap Integration
App 20200135537 - Chen; Hsueh-Chung ; et al. | 2020-04-30 |
Integration Of Artificial Intelligence Devices
App 20200135635 - Chen; Hsueh-Chung ; et al. | 2020-04-30 |
Fully Aligned Semiconductor Device With A Skip-level Via
App 20200136028 - Lanzillo; Nicholas A. ; et al. | 2020-04-30 |
Stack Viabar Structures
App 20200135457 - FAN; Su Chen ; et al. | 2020-04-30 |
Wet Clean Solutions To Prevent Pattern Collapse
App 20200118808 - Peethala; Cornelius B. ; et al. | 2020-04-16 |
Metal Spacer Self Aligned Multi-patterning Integration
App 20200118872 - CHEN; HSUEH-CHUNG ; et al. | 2020-04-16 |
Multiple Patterning With Mandrel Cuts Defined By Block Masks
App 20200111668 - O'Toole; Martin ; et al. | 2020-04-09 |
Multiple Patterning With Lithographically-defined Cuts
App 20200111677 - Srivastava; Ravi Prakash ; et al. | 2020-04-09 |
Multiple Patterning With Late Lithographically-defined Mandrel Cuts
App 20200111676 - Chen; Hsueh-Chung ; et al. | 2020-04-09 |
Stack viabar structures
Grant 10,615,027 - Fan , et al. | 2020-04-07 |
Metal On Metal Multiple Patterning
App 20200083043 - CHEN; Hsueh-Chung ; et al. | 2020-03-12 |
Multiple Patterning Scheme Integration With Planarized Cut Patterning
App 20200066526 - Chen; Hsueh-Chung ; et al. | 2020-02-27 |
Multiple Patterning Scheme Integration With Planarized Cut Patterning
App 20200066525 - Chen; Hsueh-Chung ; et al. | 2020-02-27 |
Multiple patterning scheme integration with planarized cut patterning
Grant 10,573,520 - Chen , et al. Feb | 2020-02-25 |
Interconnect formation with chamferless via, and related interconnect
Grant 10,566,231 - O'Toole , et al. Feb | 2020-02-18 |
Fully aligned semiconductor device with a skip-level via
Grant 10,553,789 - Lanzillo , et al. Fe | 2020-02-04 |
Advanced interconnect with air gap
Grant 10,546,743 - Zhang , et al. Ja | 2020-01-28 |
Multiple Patterning Scheme Integration With Planarized Cut Patterning
App 20190378718 - Chen; Hsueh-Chung ; et al. | 2019-12-12 |
Interconnect Structure
App 20190371656 - Chen; Hsueh-Chung ; et al. | 2019-12-05 |
Interconnect Formation With Chamferless Via, And Related Interconnect
App 20190333805 - O'Toole; Martin J. ; et al. | 2019-10-31 |
Merge Mandrel Features
App 20190267281 - CHEN; Hsueh-Chung ; et al. | 2019-08-29 |
SADP method with mandrel undercut spacer portion for mandrel space dimension control
Grant 10,395,941 - Srivastava , et al. A | 2019-08-27 |
Design-aware pattern density control in directed self-assembly graphoepitaxy process
Grant 10,361,116 - Chen , et al. | 2019-07-23 |
Merge Mandrel Features
App 20190221474 - CHEN; Hsueh-Chung ; et al. | 2019-07-18 |
Structure And Method Using Metal Spacer For Insertion Of Variable Wide Line Implantation In Sadp/saqp Integration
App 20190206719 - Chen; Hsueh-Chung ; et al. | 2019-07-04 |
Merge mandrel features
Grant 10,340,180 - Chen , et al. | 2019-07-02 |
Methods Of Forming Conductive Lines And Vias And The Resulting Structures
App 20190139823 - Chen; Hsueh-Chung ; et al. | 2019-05-09 |
Structure and method using metal spacer for insertion of variable wide line implantation in SADP/SAQP integration
Grant 10,276,434 - Chen , et al. | 2019-04-30 |
Design-aware Pattern Density Control In Directed Self-assembly Graphoepitaxy Process
App 20180211869 - Chen; Hsueh-Chung ; et al. | 2018-07-26 |
Image transfer using EUV lithographic structure and double patterning process
Grant 10,032,633 - Chen , et al. July 24, 2 | 2018-07-24 |
Image Transfer Using Euv Lithographic Structure And Double Patterning Process
App 20180204724 - CHEN; HSUEH-CHUNG ; et al. | 2018-07-19 |
Image Transfer Using Euv Lithographic Structure And Double Patterning Process
App 20180204723 - CHEN; HSUEH-CHUNG ; et al. | 2018-07-19 |
Design-aware pattern density control in directed self-assembly graphoepitaxy process
Grant 9,984,920 - Chen , et al. May 29, 2 | 2018-05-29 |
Advanced Interconnect With Air Gap
App 20180144926 - Zhang; John H. ; et al. | 2018-05-24 |
Electrically conductive interconnect including via having increased contact surface area
Grant 9,953,915 - Chen , et al. April 24, 2 | 2018-04-24 |
Design-aware Pattern Density Control In Directed Self-assembly Graphoepitaxy Process
App 20180012795 - Chen; Hsueh-Chung ; et al. | 2018-01-11 |
Drive-in Mn before copper plating
Grant 9,842,805 - Chen , et al. December 12, 2 | 2017-12-12 |
Freestanding spacer having sub-lithographic lateral dimension and method of forming same
Grant 9,653,571 - Chen , et al. May 16, 2 | 2017-05-16 |
Making an efuse
Grant 9,646,929 - Chen , et al. May 9, 2 | 2017-05-09 |
Drive-in Mn Before Copper Plating
App 20170092589 - Chen; Hsueh-Chung ; et al. | 2017-03-30 |
Electrically Conductive Interconnect Including Via Having Increased Contact Surface Area
App 20170084534 - Chen; Hsueh-Chung ; et al. | 2017-03-23 |
Contact area structure and method for manufacturing the same
Grant 9,576,901 - Chen , et al. February 21, 2 | 2017-02-21 |
Electrically conductive interconnect including via having increased contact surface area
Grant 9,553,044 - Chen , et al. January 24, 2 | 2017-01-24 |
Freestanding Spacer Having Sub-lithographic Lateral Dimension And Method Of Forming Same
App 20160365425 - Chen; Hsueh-Chung ; et al. | 2016-12-15 |
STI region for small fin pitch in FinFET devices
Grant 9,385,123 - Chen , et al. July 5, 2 | 2016-07-05 |
Electrically Conductive Interconnect Including Via Having Increased Contact Surface Area
App 20160126183 - Chen; Hsueh-Chung ; et al. | 2016-05-05 |
Double self aligned via patterning
Grant 9,330,965 - Chen , et al. May 3, 2 | 2016-05-03 |
Double self-aligned via patterning
Grant 9,257,334 - Chen , et al. February 9, 2 | 2016-02-09 |
Double Self Aligned Via Patterning
App 20150371896 - Chen; Hsueh-Chung ; et al. | 2015-12-24 |
Double self aligned via patterning
Grant 9,219,007 - Chen , et al. December 22, 2 | 2015-12-22 |
Double Self-aligned Via Patterning
App 20150364372 - Chen; Hsueh-Chung ; et al. | 2015-12-17 |
Trench interconnect having reduced fringe capacitance
Grant 9,214,429 - Zhang , et al. December 15, 2 | 2015-12-15 |
Sti Region For Small Fin Pitch In Finfet Devices
App 20150357328 - Chen; Hsueh-Chung ; et al. | 2015-12-10 |
Sti Region For Small Fin Pitch In Finfet Devices
App 20150340272 - Chen; Hsueh-Chung ; et al. | 2015-11-26 |
Advanced Interconnect With Air Gap
App 20150162277 - Zhang; John H. ; et al. | 2015-06-11 |
Trench Interconnect Having Reduced Fringe Capacitance
App 20150162278 - Zhang; John H. ; et al. | 2015-06-11 |
Making An Efuse
App 20150155238 - Chen; Hsueh-Chung ; et al. | 2015-06-04 |
Structure and metallization process for advanced technology nodes
Grant 8,957,519 - Yang , et al. February 17, 2 | 2015-02-17 |
Multipatterning Via Shrink Method Using Ald Spacer
App 20150001735 - Mignot; Yann ; et al. | 2015-01-01 |
Making An Efuse
App 20140367826 - Chen; Hsueh-Chung ; et al. | 2014-12-18 |
Double Self Aligned Via Patterning
App 20140363969 - Chen; Hsueh-Chung ; et al. | 2014-12-11 |
Multi-gate Field-effect Transistors With Variable Fin Heights
App 20130082333 - Chen; Hsueh-Chung ; et al. | 2013-04-04 |
Multi-gate Field-effect Transistors With Variable Fin Heights
App 20130082329 - Chen; Hsueh-Chung ; et al. | 2013-04-04 |
Three dimensional IC device and alignment methods of IC device substrates
Grant 8,232,659 - Chen , et al. July 31, 2 | 2012-07-31 |
Structure And Metallization Process For Advanced Technology Nodes
App 20120098133 - YANG; CHIH-CHAO ; et al. | 2012-04-26 |
Structure design for minimizing on-chip interconnect inductance
Grant 7,952,453 - Chen , et al. May 31, 2 | 2011-05-31 |
Semiconductor device
Grant 7,834,351 - Chen , et al. November 16, 2 | 2010-11-16 |
Method for fabricating air gap for semiconductor device
Grant 7,803,713 - Chen , et al. September 28, 2 | 2010-09-28 |
Interconnect structure and method of fabricating same
Grant 7,781,892 - Chen , et al. August 24, 2 | 2010-08-24 |
Structure Design For Minimizing On-chip Interconnect Inductance
App 20100194501 - Chen; Hsien-Wei ; et al. | 2010-08-05 |
Pad structure design with reduced density
Grant 7,714,443 - Chen , et al. May 11, 2 | 2010-05-11 |
Structure design for minimizing on-chip interconnect inductance
Grant 7,705,696 - Chen , et al. April 27, 2 | 2010-04-27 |
Metal electrical fuse structure
Grant 7,651,893 - Chen , et al. January 26, 2 | 2010-01-26 |
Design structure for coupling noise prevention
Grant 7,615,841 - Chen , et al. November 10, 2 | 2009-11-10 |
Semiconductor Device
App 20090200549 - Chen; Hsien-Wei ; et al. | 2009-08-13 |
Increasing dielectric constant in local regions for the formation of capacitors
Grant 7,553,736 - Chen , et al. June 30, 2 | 2009-06-30 |
Semiconductor device
Grant 7,538,346 - Chen , et al. May 26, 2 | 2009-05-26 |
Semiconductor device structure and methods of manufacturing the same
Grant 7,512,924 - Chen , et al. March 31, 2 | 2009-03-31 |
Semiconductor Device
App 20080296570 - Chen; Hsien-Wei ; et al. | 2008-12-04 |
Structure Design For Minimizing On-chip Interconnect Inductance
App 20080231393 - Chen; Hsien-Wei ; et al. | 2008-09-25 |
Three Dimensional Ic Device And Alignment Methods Of Ic Device Substrates
App 20080157407 - CHEN; Hsueh-Chung ; et al. | 2008-07-03 |
Three dimensional IC device and alignment methods of IC device substrates
Grant 7,371,663 - Chen , et al. May 13, 2 | 2008-05-13 |
Method For Fabricating Air Gap For Semiconductor Device
App 20080076258 - Chen; Hsien-Wei ; et al. | 2008-03-27 |
Interconnects with improved reliability
Grant 7,348,672 - Chen , et al. March 25, 2 | 2008-03-25 |
Pad Structure Design With Reduced Density
App 20080020559 - Chen; Hsien-Wei ; et al. | 2008-01-24 |
Increasing dielectric constant in local regions for the formation of capacitors
App 20080014706 - Chen; Hsien-Wei ; et al. | 2008-01-17 |
Direct printing lithography system and method
App 20070289467 - Chen; Hsueh-Chung ; et al. | 2007-12-20 |
Wiring structure to minimize stress induced void formation
Grant 7,301,239 - Wang , et al. November 27, 2 | 2007-11-27 |
Packaged Devices And Methods For Forming Packaged Devices
App 20070267737 - Chen; Hsien-Wei ; et al. | 2007-11-22 |
Bonding pad structure
App 20070176292 - Chen; Hsien-Wei ; et al. | 2007-08-02 |
Semiconductor device structure and methods of manufacturing the same
App 20070166887 - Chen; Hsien-Wei ; et al. | 2007-07-19 |
Method for designing interconnect for a new processing technology
App 20070158835 - Lin; Jian-Hong ; et al. | 2007-07-12 |
Interconnect structure and method of fabricating same
App 20070145596 - Chen; Hsueh-Chung ; et al. | 2007-06-28 |
Metal electrical fuse structure
App 20070145515 - Chen; Hsueh-Chung ; et al. | 2007-06-28 |
Method and apparatus for enhanced CMP planarization using surrounded dummy design
Grant 7,235,424 - Chen , et al. June 26, 2 | 2007-06-26 |
Ultra low-k dielectric in damascene structures
App 20070080461 - Lu; David Ding-Chung ; et al. | 2007-04-12 |
Three dimensional IC device and alignment methods of IC device substrates
App 20070020871 - Chen; Hsueh-Chung ; et al. | 2007-01-25 |
Method and apparatus for enhanced CMP planarization using surrounded dummy design
App 20070015365 - Chen; Hsien-Wei ; et al. | 2007-01-18 |
Interconnects with improved reliability
App 20070007653 - Chen; Hsien-Wei ; et al. | 2007-01-11 |
Design structure for coupling noise prevention
App 20060244133 - Chen; Hsien-Wei ; et al. | 2006-11-02 |
Electro-chemical Deposition Apparatus And Method Of Preventing Cavities In An Ecd Copper Film
App 20060199381 - Chen; Hsueh-Chung ; et al. | 2006-09-07 |
Copper interconnect structure with modulated topography and method for forming the same
App 20060099786 - Fan; Su-Chen ; et al. | 2006-05-11 |
Semiconductor device package with concavity-containing encapsulation body to prevent device delamination and increase thermal-transferring efficiency
App 20060076694 - Chen; Hsien-Wei ; et al. | 2006-04-13 |
Wiring structure to minimize stress induced void formation
App 20060019414 - Wang; Chien-Jung ; et al. | 2006-01-26 |
Dual damascene partial gap fill polymer fabrication process
Grant 6,930,038 - Lin , et al. August 16, 2 | 2005-08-16 |
Dual damascene partial gap fill polymer fabrication process
App 20050085069 - Lin, Chingfu ; et al. | 2005-04-21 |
Method for eliminating via resistance shift in organic ILD
Grant 6,806,182 - Restaino , et al. October 19, 2 | 2004-10-19 |
Wafer carrier assembly for a chemical mechanical polishing apparatus and a polishing method using the same
Grant 6,797,190 - Hsu , et al. September 28, 2 | 2004-09-28 |
Electro-chemical deposition apparatus and method of preventing cavities in an ECD copper film
App 20040178058 - Chen, Hsueh-Chung ; et al. | 2004-09-16 |
Process for forming fusible links
Grant 6,750,129 - Yang , et al. June 15, 2 | 2004-06-15 |
Process For Forming Fusible Links
App 20040092091 - Yang, Gwo-Shii ; et al. | 2004-05-13 |
Chemical mechanical polishing equipment
Grant 6,709,544 - Hu , et al. March 23, 2 | 2004-03-23 |
Chemical Mechanical Polishing Equipment
App 20040016507 - Hu, Shao-Chung ; et al. | 2004-01-29 |
Wafer Carrier Assembly For A Chemical Mechanical Polishing Apparatus And A Polishing Method Using The Same
App 20030234078 - Hsu, Chia-Lin ; et al. | 2003-12-25 |
Method for planarization of wafers with high selectivities
Grant 6,660,627 - Hu , et al. December 9, 2 | 2003-12-09 |
Method for eliminating VIA resistance shift in organic ILD
App 20030207559 - Restaino, Darryl ; et al. | 2003-11-06 |
Wafer carrier assembly for a chemical mechanical polishing apparatus and a polishing method using the same
Grant 6,638,391 - Hsu , et al. October 28, 2 | 2003-10-28 |
Method for forming an opening in polymer-based dielectric
App 20030199132 - Chen, Hsueh-Chung ; et al. | 2003-10-23 |
Method for planarization of wafers with high selectivities
App 20030181050 - Hu, Shao-Chung ; et al. | 2003-09-25 |
Method for monitoring a semiconductor wafer in a chemical mechanical polishing process
Grant 6,580,508 - Chen , et al. June 17, 2 | 2003-06-17 |
Polishing pad for a chemical mechanical polishing process
Grant 6,544,373 - Chen , et al. April 8, 2 | 2003-04-08 |
Method for forming dual-damascene interconnect structure
Grant 6,524,962 - Chen , et al. February 25, 2 | 2003-02-25 |
Polishing pad for a chemical mechanical polishing process
App 20030019570 - Chen, Hsueh-Chung ; et al. | 2003-01-30 |
Method For Forming Dual-damascene Interconnect Structure
App 20020182869 - Chen, Hsueh-Chung ; et al. | 2002-12-05 |
Damascene process in intergrated circuit fabrication
App 20020182857 - Liu, Chih-Chien ; et al. | 2002-12-05 |
Method for removing hard-mask layer after metal-CMP in dual-damascene interconnect structure
App 20020182853 - Chen, Hsueh-Chung ; et al. | 2002-12-05 |
Method for forming an opening in polymer-based dielectric
App 20020177300 - Chen, Hsueh-Chung ; et al. | 2002-11-28 |
Method of electroplating
App 20020176996 - Chen, Hsueh-Chung ; et al. | 2002-11-28 |
Method for surface treatment protecting metallic surface of semiconductor structure
App 20020177308 - Chen, Hsueh-Chung ; et al. | 2002-11-28 |
Method for forming interconnect structure with low dielectric constant
App 20020155263 - Wang, Sung-Hsiung ; et al. | 2002-10-24 |
Method for forming interconnect structure with low dielectric constant
App 20020155261 - Wang, Sung-Hsiung ; et al. | 2002-10-24 |
Method of fabricating a damascene structure
App 20020137319 - Hsu, Chia-Lin ; et al. | 2002-09-26 |
Method of fabricating a damascene structure
App 20020106877 - Hsu, Chia-Lin ; et al. | 2002-08-08 |
Method for improving non-uniformity of chemical mechanical polishing by over coating
Grant 6,344,408 - Chen , et al. February 5, 2 | 2002-02-05 |
Dual damascene CMP process with BPSG reflowed contact hole
Grant 6,239,017 - Lou , et al. May 29, 2 | 2001-05-29 |
Silicide glue layer for W-CVD plug application
App 20010000158 - Ku, Tzu-Kun ; et al. | 2001-04-05 |
Exhaust line of chemical-mechanical polisher
Grant 6,139,680 - Chen , et al. October 31, 2 | 2000-10-31 |
Dual damascene process using selective W CVD
Grant 6,110,826 - Lou , et al. August 29, 2 | 2000-08-29 |
Physical vapor deposition device for forming a uniform metal layer on a semiconductor wafer
Grant 6,099,705 - Chen , et al. August 8, 2 | 2000-08-08 |
Apparatus for controlling uniformity of polished material
Grant 6,093,089 - Chen , et al. July 25, 2 | 2000-07-25 |
Chemical-mechanical polishing station with end-point monitoring device
Grant 6,077,147 - Yang , et al. June 20, 2 | 2000-06-20 |
Method of determining real time removal rate for polishing
Grant 6,024,628 - Chen February 15, 2 | 2000-02-15 |
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