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Embedded NVM in a HKMG Process
App 20150194439 - Cheek; Jon D. ; et al. | 2015-07-09 |
Embedded NVM in a HKMG process
Grant 9,054,220 - Cheek , et al. June 9, 2 | 2015-06-09 |
Embedded NVM in a HKMG Process
App 20140225176 - Cheek; Jon D. ; et al. | 2014-08-14 |
Interlayer Dielectric Under Stress For An Integrated Circuit
App 20100190354 - Burnett; James D. ; et al. | 2010-07-29 |
Semiconductor device and method of making semiconductor device comprising multiple stacked hybrid orientation layers
Grant 7,422,956 - Waite , et al. September 9, 2 | 2008-09-09 |
Methodology to reduce SOI floating-body effect
Grant 7,410,876 - Min , et al. August 12, 2 | 2008-08-12 |
Interlayer Dielectric Under Stress For An Integrated Circuit
App 20070218618 - Burnett; James D. ; et al. | 2007-09-20 |
Interlayer dielectric under stress for an integrated circuit
Grant 7,238,990 - Burnett , et al. July 3, 2 | 2007-07-03 |
Method for offsetting a silicide process from a gate electrode of a semiconductor device
Grant 7,179,745 - Waite , et al. February 20, 2 | 2007-02-20 |
Interlayer dielectric under stress for an integrated circuit
App 20060226490 - Burnett; James D. ; et al. | 2006-10-12 |
Method of reducing STI divot formation during semiconductor device fabrication
Grant 7,091,106 - Bonser , et al. August 15, 2 | 2006-08-15 |
Semiconductor device and method of making semiconductor device comprising multiple stacked hybrid orientation layers
App 20060118918 - Waite; Andrew Michael ; et al. | 2006-06-08 |
Method of reducing STI divot formation during semiconductor device fabrication
App 20050196928 - Bonser, Douglas J. ; et al. | 2005-09-08 |
Method of forming resistive structures
App 20040235258 - Wu, David Donggang ; et al. | 2004-11-25 |
Method of forming silicide layers over a plurality of semiconductor devices
Grant 6,787,464 - Cheek , et al. September 7, 2 | 2004-09-07 |
Method of forming source/drain regions in a semiconductor device
Grant 6,720,227 - Kadosh , et al. April 13, 2 | 2004-04-13 |
Removable spacer technique
Grant 6,506,642 - Luning , et al. January 14, 2 | 2003-01-14 |
Method of forming silicide contacts and device incorporation same
App 20020137268 - Pellerin, John G. ; et al. | 2002-09-26 |
Angled halo implant tailoring using implant mask
Grant 6,372,587 - Cheek , et al. April 16, 2 | 2002-04-16 |
Ultra Short Channel Length Dictated By The Width Of A Sacrificial Sidewall Spacer
App 20020003272 - GARDNER, MARK I. ; et al. | 2002-01-10 |
Method for forming a retrograde impurity profile
Grant 6,245,649 - Buller , et al. June 12, 2 | 2001-06-12 |
Ultra short transistor channel length dictated by the width of a sidewall spacer
Grant 6,225,201 - Gardner , et al. May 1, 2 | 2001-05-01 |
Formation and control of a vertically oriented transistor channel length
Grant 6,191,446 - Gardner , et al. February 20, 2 | 2001-02-20 |
Gate conductor formed within a trench bounded by slanted sidewalls
Grant 6,130,454 - Gardner , et al. October 10, 2 | 2000-10-10 |
Transistor with integrated poly/metal gate electrode
Grant 6,118,163 - Gardner , et al. September 12, 2 | 2000-09-12 |
Method of making high performance MOSFET with integrated poly/metal gate electrode
Grant 5,994,193 - Gardner , et al. November 30, 1 | 1999-11-30 |
Test structure for determining how lithographic patterning of a gate conductor affects transistor properties
Grant 5,986,283 - Bush , et al. November 16, 1 | 1999-11-16 |
Stacked poly-oxide-poly gate for improved silicide formation
Grant 5,981,365 - Cheek , et al. November 9, 1 | 1999-11-09 |
Two level transistor formation for optimum silicon utilization
Grant 5,926,693 - Gardner , et al. July 20, 1 | 1999-07-20 |
Parallel and series-coupled transistors having gate conductors formed on sidewall surfaces of a sacrificial structure
Grant 5,866,934 - Kadosh , et al. February 2, 1 | 1999-02-02 |
Multi-level transistor fabrication method with a patterned upper transistor substrate and interconnection thereto
Grant 5,852,310 - Kadosh , et al. December 22, 1 | 1998-12-22 |
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