loadpatents
Patent applications and USPTO patent grants for Chang; Yi-Ching.The latest application filed is for "power ramping sequence control for a memory device".
Patent | Date |
---|---|
Power Ramping Sequence Control For A Memory Device App 20220254385 - Chang; Yi-Ching ;   et al. | 2022-08-11 |
Methods For Identification Of Genetic Modifiers And For Treating Nucleotide Repeat Disorder App 20220064644 - SOONG; Bing-Wen ;   et al. | 2022-03-03 |
Semiconductor device and method of forming the same Grant 11,244,948 - Chang , et al. February 8, 2 | 2022-02-08 |
Surge protector Grant D938,360 - Chang , et al. December 14, 2 | 2021-12-14 |
Surge protector adaptor Grant D938,361 - Chang , et al. December 14, 2 | 2021-12-14 |
Method Of Forming Semiconductor Device App 20210265462 - Chang; Feng-Yi ;   et al. | 2021-08-26 |
Semiconductor device having plug and metal line Grant 11,038,014 - Chang , et al. June 15, 2 | 2021-06-15 |
Method of self-aligned double patterning Grant 10,734,284 - Chang , et al. | 2020-08-04 |
Method For Forming Semiconductor Pattern App 20200212048 - Lin; Gang-Yi ;   et al. | 2020-07-02 |
Method for forming semiconductor pattern Grant 10,700,071 - Lin , et al. | 2020-06-30 |
Semiconductor Structure With Capacitor Landing Pad And Method Of Make The Same App 20200176453 - Chang; Feng-Yi ;   et al. | 2020-06-04 |
Semiconductor structure with capacitor landing pad and method of make the same Grant 10,593,677 - Chang , et al. | 2020-03-17 |
Semiconductor Device And Method Of Forming The Same App 20200083224 - Chang; Feng-Yi ;   et al. | 2020-03-12 |
Semiconductor Device And Method Of Forming The Same App 20200083325 - Chang; Feng-Yi ;   et al. | 2020-03-12 |
Method of forming semiconductor memory device Grant 10,490,555 - Chang , et al. Nov | 2019-11-26 |
Method for fabricating air gap adjacent to two sides of bit line Grant 10,418,367 - Chang , et al. Sept | 2019-09-17 |
Method of forming semiconductor device Grant 10,366,889 - Chang , et al. July 30, 2 | 2019-07-30 |
Method Of Self-aligned Double Patterning App 20190139824 - Chang; Feng-Yi ;   et al. | 2019-05-09 |
Semiconductor structure with a gap between conductor features and fabrication method thereof Grant 10,256,312 - Chang , et al. | 2019-04-09 |
Semiconductor Structure With Capacitor Landing Pad And Method Of Make The Same App 20190043865 - Chang; Feng-Yi ;   et al. | 2019-02-07 |
Method Of Forming Semiconductor Memory Device App 20190013321 - Chang; Yi-Ching ;   et al. | 2019-01-10 |
Method Of Forming Semiconductor Device App 20180374702 - Chang; Feng-Yi ;   et al. | 2018-12-27 |
Method For Fabricating Air Gap Adjacent To Two Sides Of Bit Line App 20180337186 - Chang; Yi-Ching ;   et al. | 2018-11-22 |
Semiconductor device and method for fabricating the same Grant 10,043,809 - Chang , et al. August 7, 2 | 2018-08-07 |
Integrated circuit having voltage mismatch reduction Grant 9,390,816 - Hsu , et al. July 12, 2 | 2016-07-12 |
Integrated Circuit Having Voltage Mismatch Reduction App 20160133342 - HSU; Yu-Hao ;   et al. | 2016-05-12 |
Heat Sink And Method Of Assemblying App 20160057891 - Chang; Yi-Ching ;   et al. | 2016-02-25 |
Integrated circuit having voltage mismatch reduction Grant 9,240,233 - Hsu , et al. January 19, 2 | 2016-01-19 |
Systems and methods of power device lighting Grant 8,686,593 - Chang , et al. April 1, 2 | 2014-04-01 |
Systems And Methods Of Power Device Lighting App 20120074840 - Chang; Yi-Ching ;   et al. | 2012-03-29 |
Edge-type Backlight Module With A Lock Mechanism For Combining A Light Guide Plate With A Backing Plate App 20070091645 - Chang; Yi-Ching ;   et al. | 2007-04-26 |
uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.
While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.
All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.