| Patent | Date |
|---|
Multiple-requestor Memory Access Pipeline And Arbiter
App 20220261360 - Chachad; Abhijeet Ashok ; et al. | 2022-08-18 |
Handling non-correctable errors
Grant 11,416,334 - Thompson , et al. August 16, 2 | 2022-08-16 |
Cache Size Change
App 20220253382 - CHACHAD; Abhijeet Ashok ; et al. | 2022-08-11 |
Prefetch Kill And Revival In An Instruction Cache
App 20220245069 - Heremagalur Ramaprasad; Bipin Prasad ; et al. | 2022-08-04 |
Cache Preload Operations Using Streaming Engine
App 20220244957 - Zbiciak; Joseph Raymond Michael ; et al. | 2022-08-04 |
Tag Update Bus For Updated Coherence State
App 20220237122 - CHACHAD; Abhijeet Ashok ; et al. | 2022-07-28 |
Global Coherence Operations
App 20220229690 - CHACHAD; Abhijeet Ashok ; et al. | 2022-07-21 |
Aliased mode for cache controller
Grant 11,392,498 - Chachad , et al. July 19, 2 | 2022-07-19 |
Error Correcting Codes For Multi-master Memory Controller
App 20220164252 - CHACHAD; Abhijeet Ashok ; et al. | 2022-05-26 |
Cache Coherence Shared State Suppression
App 20220164287 - CHACHAD; Abhijeet Ashok ; et al. | 2022-05-26 |
Merging Data For Write Allocate
App 20220164217 - CHACHAD; Abhijeet Ashok ; et al. | 2022-05-26 |
Pipelined Read-modify-write Operations In Cache Memory
App 20220156149 - Chachad; Abhijeet Ashok ; et al. | 2022-05-19 |
Multiple-requestor memory access pipeline and arbiter
Grant 11,321,248 - Chachad , et al. May 3, 2 | 2022-05-03 |
Prefetch kill and revival in an instruction cache
Grant 11,314,660 - Heremagalur Ramaprasad , et al. April 26, 2 | 2022-04-26 |
Cache size change
Grant 11,314,644 - Chachad , et al. April 26, 2 | 2022-04-26 |
Cache preload operations using streaming engine
Grant 11,307,858 - Zbiciak , et al. April 19, 2 | 2022-04-19 |
Tag update bus for updated coherence state
Grant 11,307,987 - Chachad , et al. April 19, 2 | 2022-04-19 |
Global coherence operations
Grant 11,294,707 - Chachad , et al. April 5, 2 | 2022-04-05 |
Hardware Coherence Signaling Protocol
App 20220066937 - CHACHAD; Abhijeet Ashok ; et al. | 2022-03-03 |
Prefetch Management In A Hierarchical Cache System
App 20220058127 - Heremagalur Ramaprasad; Bipin Prasad ; et al. | 2022-02-24 |
Error correcting codes for multi-master memory controller
Grant 11,249,842 - Chachad , et al. February 15, 2 | 2022-02-15 |
Cache coherence shared state suppression
Grant 11,243,883 - Chachad , et al. February 8, 2 | 2022-02-08 |
Pipelined read-modify-write operations in cache memory
Grant 11,237,905 - Chachad , et al. February 1, 2 | 2022-02-01 |
Memory Pipeline Control In A Hierarchical Memory System
App 20220027275 - Chachad; Abhijeet Ashok ; et al. | 2022-01-27 |
Cache Management Operations Using Streaming Engine
App 20210406014 - Zbiciak; Joseph Raymond Michael ; et al. | 2021-12-30 |
Shadow Caches For Level 2 Cache Controller
App 20210390050 - CHACHAD; Abhijeet Ashok ; et al. | 2021-12-16 |
Hardware Coherence For Memory Controller
App 20210390051 - CHACHAD; Abhijeet Ashok ; et al. | 2021-12-16 |
Merging data for write allocate
Grant 11,194,617 - Chachad , et al. December 7, 2 | 2021-12-07 |
Aliased Mode For Cache Controller
App 20210365374 - CHACHAD; Abhijeet Ashok ; et al. | 2021-11-25 |
Prefetch management in a hierarchical cache system
Grant 11,169,924 - Heremagalur Ramaprasad , et al. November 9, 2 | 2021-11-09 |
Hardware coherence signaling protocol
Grant 11,144,456 - Chachad , et al. October 12, 2 | 2021-10-12 |
Memory pipeline control in a hierarchical memory system
Grant 11,138,117 - Chachad , et al. October 5, 2 | 2021-10-05 |
Cache management operations using streaming engine
Grant 11,119,776 - Zbiciak , et al. September 14, 2 | 2021-09-14 |
Shadow caches for level 2 cache controller
Grant 11,106,583 - Chachad , et al. August 31, 2 | 2021-08-31 |
Hardware coherence for memory controller
Grant 11,106,584 - Chachad , et al. August 31, 2 | 2021-08-31 |
Lookahead Priority Collection To Support Priority Elevation
App 20200401532 - Chachad; Abhijeet Ashok ; et al. | 2020-12-24 |
Global Coherence Operations
App 20200371926 - CHACHAD; Abhijeet Ashok ; et al. | 2020-11-26 |
Multi-level Cache Security
App 20200371927 - Chachad; Abhijeet Ashok ; et al. | 2020-11-26 |
Merging Data For Write Allocate
App 20200371925 - CHACHAD; Abhijeet Ashok ; et al. | 2020-11-26 |
Controller With Caching And Non-caching Modes
App 20200371924 - CHACHAD; Abhijeet Ashok ; et al. | 2020-11-26 |
Memory Pipeline Control In A Hierarchical Memory System
App 20200371937 - Chachad; Abhijeet Ashok ; et al. | 2020-11-26 |
Multiple-requestor Memory Access Pipeline And Arbiter
App 20200371970 - Chachad; Abhijeet Ashok ; et al. | 2020-11-26 |
Hardware Coherence Signaling Protocol
App 20200371934 - CHACHAD; Abhijeet Ashok ; et al. | 2020-11-26 |
Parallelized Scrubbing Transactions
App 20200371862 - THOMPSON; David Matthew ; et al. | 2020-11-26 |
Pipeline Arbitration
App 20200371834 - CHACHAD; Abhijeet Ashok ; et al. | 2020-11-26 |
Error Correcting Codes For Multi-master Memory Controller
App 20200371874 - CHACHAD; Abhijeet Ashok ; et al. | 2020-11-26 |
Handling Non-correctable Errors
App 20200371875 - THOMPSON; David Matthew ; et al. | 2020-11-26 |
Pipelined Read-modify-write Operations In Cache Memory
App 20200371877 - Chachad; Abhijeet Ashok ; et al. | 2020-11-26 |
Tag Update Bus For Updated Coherence State
App 20200371923 - CHACHAD; Abhijeet Ashok ; et al. | 2020-11-26 |
Write Control For Read-modify-write Operations In Cache Memory
App 20200371918 - Chachad; Abhijeet Ashok ; et al. | 2020-11-26 |
Cache Coherence Shared State Suppression
App 20200371931 - CHACHAD; Abhijeet Ashok ; et al. | 2020-11-26 |
Write Streaming In A Processor
App 20200371917 - Chachad; Abhijeet Ashok ; et al. | 2020-11-26 |
Pseudo-random Way Selection
App 20200371935 - CHACHAD; Abhijeet Ashok ; et al. | 2020-11-26 |
Hardware Coherence For Memory Controller
App 20200371930 - CHACHAD; Abhijeet Ashok ; et al. | 2020-11-26 |
Shadow Caches For Level 2 Cache Controller
App 20200371920 - CHACHAD; Abhijeet Ashok ; et al. | 2020-11-26 |
Cache Size Change
App 20200371919 - CHACHAD; Abhijeet Ashok ; et al. | 2020-11-26 |
Prefetch Management In A Hierarchical Cache System
App 20200320006 - Heremagalur Ramaprasad; Bipin Prasad ; et al. | 2020-10-08 |
Cache Management Operations Using Streaming Engine
App 20200285469 - Zbiciak; Joseph Raymond Michael ; et al. | 2020-09-10 |
Cache Preload Operations Using Streaming Engine
App 20200285470 - Zbiciak; Joseph Raymond Michael ; et al. | 2020-09-10 |
Lookahead priority collection to support priority elevation
Grant 10,713,180 - Chachad , et al. | 2020-07-14 |
Prefetch management in a hierarchical cache system
Grant 10,642,742 - Heremagalur Ramaprasad , et al. | 2020-05-05 |
Cache preload operations using streaming engine
Grant 10,606,596 - Zbiciak , et al. | 2020-03-31 |
Cache management operations using streaming engine
Grant 10,599,433 - Zbiciak , et al. | 2020-03-24 |
Prefetch Kill And Revival In An Instruction Cache
App 20200089622 - Heremagalur Ramaprasad; Bipin Prasad ; et al. | 2020-03-19 |
Prefetch Management In A Hierarchical Cache System
App 20200057720 - Heremagalur Ramaprasad; Bipin Prasad ; et al. | 2020-02-20 |
Prefetch kill and revival in an instruction cache
Grant 10,489,305 - Heremagalur Ramaprasad , et al. Nov | 2019-11-26 |
Cache Preload Operations Using Streaming Engine
App 20190095205 - Zbiciak; Joseph Raymond Michael ; et al. | 2019-03-28 |
Cache Management Operations Using Streaming Engine
App 20190095204 - Zbiciak; Joseph Raymond Michael ; et al. | 2019-03-28 |
Lookahead Priority Collection to Support Priority Elevation
App 20190004967 - Chachad; Abhijeet Ashok ; et al. | 2019-01-03 |
Programmable address-based write-through cache control
Grant 9,575,901 - Damodaran , et al. February 21, 2 | 2017-02-21 |
Zero cycle clock invalidate operation
Grant 9,390,011 - Bhoria , et al. July 12, 2 | 2016-07-12 |
Performance and power improvement on DMA writes to level two combined cache/SRAM that is cached in level one data cache and line is valid and dirty
Grant 9,298,643 - Tran , et al. March 29, 2 | 2016-03-29 |
Level one data cache line lock and enhanced snoop protocol during cache victims and writebacks to maintain level one data cache and level two cache coherence
Grant 9,268,708 - Damodaran , et al. February 23, 2 | 2016-02-23 |
Programmable Address-Based Write-Through Cache Control
App 20160034396 - Damodaran; Raguram ; et al. | 2016-02-04 |
Zero Cycle Clock Invalidate Operation
App 20160026569 - Bhoria; Naveen ; et al. | 2016-01-28 |
Zero cycle clock invalidate operation
Grant 9,244,837 - Bhoria , et al. January 26, 2 | 2016-01-26 |
Programmable address-based write-through cache control
Grant 9,189,331 - Damodaran , et al. November 17, 2 | 2015-11-17 |
Performance And Power Improvement On Dma Writes To Level Two Combined Cache/sram That Is Cached In Level One Data Cache And Line Is Valid And Dirty
App 20150269090 - Tran; Jonathan (Son) Hung ; et al. | 2015-09-24 |
Performance and power improvement on DMA writes to level two combined cache/SRAM that is caused in level one data cache and line is valid and dirty
Grant 9,075,744 - Tran , et al. July 7, 2 | 2015-07-07 |
Managing bandwidth allocation in a processing node using distributed arbitration
Grant 9,075,743 - Damodaran , et al. July 7, 2 | 2015-07-07 |
Level One Data Cache Line Lock and Enhanced Snoop Protocol During Cache Victims and Writebacks to Maintain Level One Data Cache and Level Two Cache Coherence
App 20150178221 - Damodaran; Raguram ; et al. | 2015-06-25 |
Non-blocking, pipelined write allocates with allocate data merging in a multi-level cache system
Grant 9,009,408 - Chachad , et al. April 14, 2 | 2015-04-14 |
Level one data cache line lock and enhanced snoop protocol during cache victims and writebacks to maintain level one data cache and level two cache coherence
Grant 9,003,122 - Damodaran , et al. April 7, 2 | 2015-04-07 |
Asynchronous clock dividers to reduce on-chip variations of clock timing
Grant 8,970,267 - Damodaran , et al. March 3, 2 | 2015-03-03 |
Dynamic Management Of Write-miss Buffer To Reduce Write-miss Traffic
App 20150006820 - Bhoria; Naveen ; et al. | 2015-01-01 |
Cache with multiple access pipelines
Grant 8,904,115 - Chachad , et al. December 2, 2 | 2014-12-02 |
Robust hamming code implementation for soft error detection, correction, and reporting in a multi-level cache system using dual banking memory scheme
Grant 8,904,260 - Tran , et al. December 2, 2 | 2014-12-02 |
Hazard prevention for data conflicts between level one data cache line allocates and snoop writes
Grant 8,856,446 - Chachad , et al. October 7, 2 | 2014-10-07 |
Enhanced pipelining and multi-buffer architecture for level two cache controller to minimize hazard stalls and optimize performance
Grant 8,732,398 - Chachad , et al. May 20, 2 | 2014-05-20 |
Requester based transaction status reporting in a system with multi-level memory
Grant 8,732,416 - Damodaran , et al. May 20, 2 | 2014-05-20 |
Configurable source based/requestor based error detection and correction for soft errors in multi-level cache memory to minimize CPU interrupt service routines
Grant 8,707,127 - Tran , et al. April 22, 2 | 2014-04-22 |
Zero Cycle Clock Invalidate Operation
App 20140108737 - Bhoria; Naveen ; et al. | 2014-04-17 |
Clock control of pipelined memory for improved delay fault testing
Grant 8,694,843 - Venkatasubramanian , et al. April 8, 2 | 2014-04-08 |
Cache pre-allocation of ways for pipelined allocate requests
Grant 8,683,137 - Chachad , et al. March 25, 2 | 2014-03-25 |
Efficient level two memory banking to improve performance for multiple source traffic and enable deeper pipelining of accesses by reducing bank stalls
Grant 8,661,199 - Chachad , et al. February 25, 2 | 2014-02-25 |
Optimizing tag forwarding in a two level cache system from level one to lever two controllers for cache coherence protocol for direct memory access transfers
Grant 8,656,105 - Damodaran , et al. February 18, 2 | 2014-02-18 |
Efficient cache allocation by optimizing size and order of allocate commands based on bytes required by CPU
Grant 8,607,000 - Chachad , et al. December 10, 2 | 2013-12-10 |
System And Method Of Optimized User Coherence For A Cache Block With Sparse Dirty Lines
App 20130326155 - Chachad; Abhijeet Ashok | 2013-12-05 |
Priority based exception mechanism for multi-level cache controller
Grant 8,560,896 - Zbiciak , et al. October 15, 2 | 2013-10-15 |
Process variability tolerant programmable memory controller for a pipelined memory system
Grant 8,488,405 - Chachad , et al. July 16, 2 | 2013-07-16 |
Asynchronous Clock Dividers to Reduce On-Chip Variations of Clock Timing
App 20130176060 - Modaran; Raguram ; et al. | 2013-07-11 |
Clock Control of Pipelined Memory for Improved Delay Fault Testing
App 20130036337 - Venkatasubramanian; Ramakrishnan ; et al. | 2013-02-07 |
Process Variability Tolerant Programmable Memory Controller for a Pipelined Memory System
App 20130021858 - Chachad; Abhijeet Ashok ; et al. | 2013-01-24 |
Lookahead Priority Collection to Support Priority Elevation
App 20120290755 - Chachad; Abhijeet Ashok ; et al. | 2012-11-15 |
Managing Bandwidth Allocation in a Processing Node Using Distributed Arbitration
App 20120290756 - Damodaran; Raguram ; et al. | 2012-11-15 |
Enhanced Pipelining And Multi-buffer Architecture For Level Two Cache Controller To Minimize Hazard Stalls And Optimize Performance
App 20120260031 - Chachad; Abhijeet Ashok ; et al. | 2012-10-11 |
Priority Based Exception Mechanism for Multi-Level Cache Controller
App 20120198272 - Zbiciak; Joseph Raymond Michael ; et al. | 2012-08-02 |
Programmable Address-Based Write-Through Cache Control
App 20120198164 - Damodaran; Raguram ; et al. | 2012-08-02 |
Non-blocking, Pipelined Write Allocates With Allocate Data Merging In A Multi-level Cache System
App 20120198161 - Chachad; Abhijeet Ashok ; et al. | 2012-08-02 |
Level One Data Cache Line Lock and Enhanced Snoop Protocol During Cache Victims and Writebacks to Maintain Level One Data Cache and Level Two Cache Coherence
App 20120198163 - Damodaran; Raguram ; et al. | 2012-08-02 |
Configurable Source Based/requestor Based Error Detection And Correction For Soft Errors In Multi-level Cache Memory To Minimize Cpu Interrupt Service Routines
App 20120198310 - Tran; Jonathan (Son) Hung ; et al. | 2012-08-02 |
Hazard Prevention for Data Conflicts Between Level One Data Cache Line Allocates and Snoop Writes
App 20120198162 - Chachad; Abhijeet Ashok ; et al. | 2012-08-02 |
Cache Pre-Allocation of Ways for Pipelined Allocate Requests
App 20120198171 - Chachad; Abhijeet Ashok ; et al. | 2012-08-02 |
Efficient Cache Allocation by Optimizing Size and Order of Allocate Commands Based on Bytes Required by CPU
App 20120198160 - Chachad; Abhijeet Ashok ; et al. | 2012-08-02 |
Optimizing Tag Forwarding In A Two Level Cache System From Level One To Lever Two Controllers For Cache Coherence Protocol For Direct Memory Access Transfers
App 20120191916 - Chachad; Abhijeet Ashok ; et al. | 2012-07-26 |
Performance And Power Improvement On Dma Writes To Level Two Combined Cache/sram That Is Caused In Level One Data Cache And Line Is Valid And Dirty
App 20120191914 - Tran; Jonathan (Son) Hung ; et al. | 2012-07-26 |
Efficient Level Two Memory Banking To Improve Performance For Multiple Source Traffic And Enable Deeper Pipelining Of Accesses By Reducing Bank Stalls
App 20120191915 - Chachad; Abhijeet Ashok ; et al. | 2012-07-26 |
Robust Hamming Code Implementation for Soft Error Detection, Correction, and Reporting in a Multi-Level Cache System Using Dual Banking Memory Scheme
App 20120192027 - Tran; Jonathan (Son) Hung ; et al. | 2012-07-26 |
Requester Based Transaction Status Reporting in a System with Multi-Level Memory
App 20120079102 - Damodaran; Raguram ; et al. | 2012-03-29 |
Cache with Multiple Access Pipelines
App 20120079204 - Chachad; Abhijeet Ashok ; et al. | 2012-03-29 |
| 