Burnett; James D.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Burnett; James D..The latest application filed is for "methods and structures for multiport memory devices".

Company Profile

0.66.62

Burnett; James D. - Austin TX
Burnett; James D. - Meylan FR
Burnett; James D. - Martinsville VA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Methods and structures for multiport memory devices Grant 9,455,260 - Pelley , et al. September 27, 2	2016-09-27
Methods And Structures For Multiport Memory Devices App 20150357338 - PELLEY; PERRY H. ; et al.	2015-12-10
Semiconductor device with single-event latch-up prevention circuitry Grant 9,123,545 - Yang , et al. September 1, 2	2015-09-01
SRAM bit cell with reduced bit line pre-charge voltage Grant 9,111,638 - Burnett , et al. August 18, 2	2015-08-18
Methods and structures for multiport memory devices Grant 9,111,634 - Pelley , et al. August 18, 2	2015-08-18
Word line driver circuits and methods for SRAM bit cell with reduced bit line pre-charge voltage Grant 8,947,970 - Pelley , et al. February 3, 2	2015-02-03
Systems and methods for reduced coupling between digital signal lines Grant 8,836,371 - Pelley , et al. September 16, 2	2014-09-16
Systems And Methods For Reduced Coupling Between Digital Signal Lines App 20140203841 - Pelley; Perry H. ; et al.	2014-07-24
Method and apparatus for sensing on-chip characteristics Grant 8,766,703 - Yang , et al. July 1, 2	2014-07-01
Semiconductor Device With Single-event Latch-up Prevention Circuitry App 20140167102 - YANG; JIANAN ; et al.	2014-06-19
Single event latch-up prevention techniques for a semiconductor device Grant 8,685,800 - Yang , et al. April 1, 2	2014-04-01
Memory having a latching sense amplifier resistant to negative bias temperature instability and method therefor Grant 8,659,322 - Hoefler , et al. February 25, 2	2014-02-25
Multiple device types including an inverted-T channel transistor and method therefor Grant 8,643,066 - Min , et al. February 4, 2	2014-02-04
Single-event Latch-up Prevention Techniques For A Semiconductor Device App 20140027810 - Yang; Jianan ; et al.	2014-01-30
Transistors with immersed contacts Grant 8,633,515 - Orlowski , et al. January 21, 2	2014-01-21
Sram Bit Cell With Reduced Bit Line Pre-charge Voltage App 20140016402 - BURNETT; JAMES D. ; et al.	2014-01-16
Methods And Structures For Multiport Memory Devices App 20140015061 - PELLEY; PERRY H. ; et al.	2014-01-16
Word Line Driver Circuits And Methods For Sram Bit Cell With Reduced Bit Line Pre-charge Voltage App 20140016400 - PELLEY; PERRY H. ; et al.	2014-01-16
Methods for testing a memory embedded in an integrated circuit Grant 8,531,899 - Zhang , et al. September 10, 2	2013-09-10
Integrated circuit having an embedded memory and method for testing the memory Grant 8,379,466 - Zhang , et al. February 19, 2	2013-02-19
Methods For Testing A Memory Embedded In An Integrated Circuit App 20130019133 - Zhang; Shayan ; et al.	2013-01-17
Transistors With Immersed Contacts App 20130009222 - ORLOWSKI; MARIUS K. ; et al.	2013-01-10
Transistors with immersed contacts Grant 8,314,448 - Orlowski , et al. November 20, 2	2012-11-20
Method for forming one transistor DRAM cell structure Grant 8,283,244 - Burnett , et al. October 9, 2	2012-10-09
Memory Having A Latching Sense Amplifier Resistant To Negative Bias Temperature Instability And Method Therefor App 20120194222 - Hoefler; Alexander B. ; et al.	2012-08-02
Voltage-based memory size scaling in a data processing system Grant 8,156,357 - Zhang , et al. April 10, 2	2012-04-10
Integrated circuit using FinFETs and having a static random access memory (SRAM) Grant 8,088,657 - Burnett , et al. January 3, 2	2012-01-03
Transistors With Immersed Contacts App 20110210395 - Orlowski; Marius K. ; et al.	2011-09-01
Single transistor memory cell with reduced recombination rates Grant 7,986,006 - Orlowski , et al. July 26, 2	2011-07-26
Transistor with immersed contacts and methods of forming thereof Grant 7,968,394 - Orlowski , et al. June 28, 2	2011-06-28
Process for forming an electronic device including a fin-type transistor structure Grant 7,939,412 - Orlowski , et al. May 10, 2	2011-05-10
Method of forming an integrated circuit Grant 7,824,988 - Hoefler , et al. November 2, 2	2010-11-02
Integrated Circuit Having An Embedded Memory And Method For Testing The Memory App 20100246297 - Zhang; Shayan ; et al.	2010-09-30
Memory having self-timed bit line boost circuit and method therefor Grant 7,800,959 - Childs , et al. September 21, 2	2010-09-21
Transistor with asymmetry for data storage circuitry Grant 7,799,644 - White , et al. September 21, 2	2010-09-21
Integrated Circuit Using Finfets And Having A Static Random Access Memory (sram) App 20100230762 - Burnett; James D. ; et al.	2010-09-16
Interlayer Dielectric Under Stress For An Integrated Circuit App 20100190354 - Burnett; James D. ; et al.	2010-07-29
Electronic Device Including A Fin-type Transistor Structure And A Process For Forming The Electronic Device App 20100190308 - Orlowski; Marius K. ; et al.	2010-07-29
Voltage-based Memory Size Scaling In A Data Processing System App 20100191990 - Zhang; Shayan ; et al.	2010-07-29
Method Of Forming An Integrated Circuit App 20100181629 - Hoefler; Alexander ; et al.	2010-07-22
Integrated circuit using FinFETs and having a static random access memory (SRAM) Grant 7,754,560 - Burnett , et al. July 13, 2	2010-07-13
Circuit and method for optimizing memory sense amplifier timing Grant 7,733,711 - Burnett , et al. June 8, 2	2010-06-08
Electronic device including a fin-type transistor structure and a process for forming the electronic device Grant 7,723,805 - Orlowski , et al. May 25, 2	2010-05-25
Interlayer dielectric under stress for an integrated circuit Grant 7,718,485 - Burnett , et al. May 18, 2	2010-05-18
Process for forming an electronic device including a fin-type structure Grant 7,709,303 - Burnett , et al. May 4, 2	2010-05-04
Memory Having Self-timed Bit Line Boost Circuit And Method Therefor App 20100074032 - Childs; Lawrence F. ; et al.	2010-03-25
Memory system with RAM array and redundant RAM memory cells having a different designed cell circuit topology than cells of non redundant RAM array Grant 7,684,264 - Hunter , et al. March 23, 2	2010-03-23
Circuit And Method For Optimizing Memory Sense Amplifier Timing App 20100061162 - Burnett; James D. ; et al.	2010-03-11
One Transistor Dram Cell Structure And Method For Forming App 20100001326 - BURNETT; JAMES D. ; et al.	2010-01-07
One transistor DRAM cell structure Grant 7,608,898 - Burnett , et al. October 27, 2	2009-10-27
Single Transistor Memory Cell With Reduced Recombination Rates App 20090166700 - ORLOWSKI; Marius K. ; et al.	2009-07-02
Integrated circuit having a memory with low voltage read/write operation Grant 7,542,369 - Kenkare , et al. June 2, 2	2009-06-02
Single transistor memory cell with reduced recombination rates Grant 7,517,741 - Orlowski , et al. April 14, 2	2009-04-14
Multiple Device Types Including An Inverted-t Channel Transistor And Method Therefor App 20090039418 - Min; Byoung W. ; et al.	2009-02-12
Semiconductor structure with reduced gate doping and methods for forming thereof Grant 7,488,635 - Winstead , et al. February 10, 2	2009-02-10
Apparatus and method for adjusting an operating parameter of an integrated circuit Grant 7,483,327 - Qureshi , et al. January 27, 2	2009-01-27
Multiple device types including an inverted-T channel transistor and method therefor Grant 7,452,768 - Min , et al. November 18, 2	2008-11-18
Two-port SRAM having improved write operation Grant 7,440,313 - Abeln , et al. October 21, 2	2008-10-21
Electronic device including a static-random-access memory cell and a process of forming the electronic device Grant 7,414,877 - Burnett , et al. August 19, 2	2008-08-19
Memory System With Redundant Ram Memory Cells Having A Different Designed Cell Circuit Topology App 20080181034 - Hunter; Bradford L. ; et al.	2008-07-31
Switch device and method Grant 7,403,410 - Burnett July 22, 2	2008-07-22
Two-port Sram Having Improved Write Operation App 20080117665 - Abeln; Glenn C. ; et al.	2008-05-22
One Transistor Dram Cell Structure And Method For Forming App 20080099808 - Burnett; James D. ; et al.	2008-05-01
Semiconductor Device Having A P-mos Transistor With Source-drain Extension Counter-doping App 20080090359 - Goktepeli; Sinan ; et al.	2008-04-17
Methods for programming a floating body nonvolatile memory Grant 7,352,631 - Burnett , et al. April 1, 2	2008-04-01
Electronic device and method for operating a memory circuit Grant 7,336,533 - Hunter , et al. February 26, 2	2008-02-26
Transistor With Asymmetry For Data Storage Circuitry App 20080026529 - White; Ted R. ; et al.	2008-01-31
Integrated Circuit Having A Memory With Low Voltage Read/write Operation App 20080019206 - Kenkare; Prashant U. ; et al.	2008-01-24
Integrated circuit having a memory with low voltage read/write operation Grant 7,292,495 - Kenkare , et al. November 6, 2	2007-11-06
Multiport single transistor bit cell Grant 7,285,832 - Hoefler , et al. October 23, 2	2007-10-23
Apparatus and method for adjusting an operating parameter of an integrated circuit App 20070220388 - Quereshi; Qadeer A. ; et al.	2007-09-20
Interlayer Dielectric Under Stress For An Integrated Circuit App 20070218618 - Burnett; James D. ; et al.	2007-09-20
Switch device and method App 20070211526 - Burnett; James D.	2007-09-13
System and method for operating a memory circuit App 20070211517 - Burnett; James D.	2007-09-13
Memory access with consecutive addresses corresponding to different rows Grant 7,269,090 - Baker, Jr. , et al. September 11, 2	2007-09-11
Electronic device including a static-random-access memory cell and a process of forming the electronic device App 20070171700 - Burnett; James D. ; et al.	2007-07-26
Electronic device and method for operating a memory circuit App 20070171713 - Hunter; Bradford L. ; et al.	2007-07-26
Process for forming an electronic device including a fin-type structure App 20070161171 - Burnett; James D. ; et al.	2007-07-12
Electronic device including a fin-type transistor structure and a process for forming the electronic device App 20070158764 - Orlowski; Marius K. ; et al.	2007-07-12
Transistor with immersed contacts and methods of forming thereof App 20070161170 - Orlowski; Marius K. ; et al.	2007-07-12
Integrated circuit using FinFETs and having a static random access memory (SRAM) App 20070158730 - Burnett; James D. ; et al.	2007-07-12
Single transistor memory cell with reduced programming voltages Grant 7,238,555 - Orlowski , et al. July 3, 2	2007-07-03
Interlayer dielectric under stress for an integrated circuit Grant 7,238,990 - Burnett , et al. July 3, 2	2007-07-03
Semiconductor structure with reduced gate doping and methods for forming thereof App 20070093043 - Winstead; Brian A. ; et al.	2007-04-26
Multiple device types including an inverted-T channel transistor and method therefor App 20070093054 - Min; Byoung W. ; et al.	2007-04-26
Semiconductor device having a p-MOS transistor with source-drain extension counter-doping App 20070057329 - Goktepeli; Sinan ; et al.	2007-03-15
Multiport single transistor bit cell App 20070023789 - Hoefler; Alexander B. ; et al.	2007-02-01
Single transistor memory cell with reduced programming voltages App 20070001162 - Orlowski; Marius K. ; et al.	2007-01-04
Single transistor memory cell with reduced recombination rates App 20070001222 - Orlowski; Marius K. ; et al.	2007-01-04
Isolation trench perimeter implant for threshold voltage control Grant 7,135,379 - Orlowski , et al. November 14, 2	2006-11-14
Method of forming trench isolation in a semiconductor device App 20060234467 - Van Gompel; Toni D. ; et al.	2006-10-19
Interlayer dielectric under stress for an integrated circuit App 20060226490 - Burnett; James D. ; et al.	2006-10-12
Method for forming a semiconductor device having a notched control electrode and structure thereof Grant 7,105,430 - Orlowski , et al. September 12, 2	2006-09-12
NVM cell on SOI and method of manufacture App 20060186456 - Burnett; James D. ; et al.	2006-08-24
Methods for programming a floating body nonvolatile memory App 20060186457 - Burnett; James D. ; et al.	2006-08-24
Word line driver circuit for a static random access memory and method therefor Grant 7,085,175 - Remington , et al. August 1, 2	2006-08-01
Memory with recessed devices Grant 7,078,297 - Burnett , et al. July 18, 2	2006-07-18
Word line driver circuit for a static random access memory and method therefor App 20060104107 - Remington; Scott I. ; et al.	2006-05-18
Isolation trench perimeter implant for threshold voltage control App 20060068542 - Orlowski; Marius K. ; et al.	2006-03-30
Memory with recessed devices App 20050266643 - Burnett, James D. ; et al.	2005-12-01
Method for forming a semiconductor device having a notched control electrode and structure thereof App 20050215008 - Orlowski, Marius K. ; et al.	2005-09-29
One transistor DRAM cell structure and method for forming Grant 6,861,689 - Burnett March 1, 2	2005-03-01
One transistor DRAM cell structure and method for forming App 20040089890 - Burnett, James D.	2004-05-13
Multi-bit non-volatile memory cell and method therefor Grant 6,724,032 - Chindalore , et al. April 20, 2	2004-04-20
Write operation for capacitorless RAM Grant 6,714,436 - Burnett , et al. March 30, 2	2004-03-30
Multi-bit Non-volatile Memory Cell And Method Therefor App 20040016950 - Chindalore, Gowrishankar L. ; et al.	2004-01-29
Memory system and method of accessing thereof App 20020103959 - Baker, Frank K. JR. ; et al.	2002-08-01
Insulated gate semiconductor device and method of manufacture Grant 5,541,132 - Davies , et al. July 30, 1	1996-07-30
Insecticidal collar for animals Grant 4,141,322 - Evans , et al. February 27, 1	1979-02-27

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