Bhatt; Hemanshu

Patent Applications and Registrations

Patent applications and USPTO patent grants for Bhatt; Hemanshu.The latest application filed is for "system and method for dynamic balancing power in a battery pack".

Company Profile

0.12.10

Bhatt; Hemanshu - Maharashtra IN
Bhatt; Hemanshu - Mumbai IN
Bhatt; Hemanshu - Bangalore IN
Bhatt; Hemanshu - Vancouver WA
Bhatt; Hemanshu - Penang MY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
System And Method For Dynamic Balancing Power In A Battery Pack App 20220021221 - Tyagi; Sunit ; et al.	2022-01-20
DC-DC power conversion system Grant 11,183,839 - Apte , et al. November 23, 2	2021-11-23
Dc-dc Power Conversion System App 20180102646 - Apte; Jitendra ; et al.	2018-04-12
Power conversion for distributed DC source array Grant 9,577,548 - Tyagi , et al. February 21, 2	2017-02-21
Alternate Pad Structures/passivation Integration Schemes To Reduce Or Eliminate Imc Cracking In Post Wire Bonded Dies During Cu/low-k Beol Processing App 20140030541 - Bhatt; Hemanshu ; et al.	2014-01-30
Power Conversion For Distributed Dc Source Array App 20140008987 - Tyagi; Sunit ; et al.	2014-01-09
Power conversion for distributed DC source array Grant 8,552,587 - Tyagi , et al. October 8, 2	2013-10-08
Alternate pad structures/passivation inegration schemes to reduce or eliminate IMC cracking in post wire bonded dies during Cu/Low-K BEOL processing Grant 8,552,560 - Bhatt , et al. October 8, 2	2013-10-08
Power Conversion For Distributed Dc Source Array App 20120019072 - Tyagi; Sunit ; et al.	2012-01-26
Reduction of macro level stresses in copper/low-K wafers Grant 8,076,779 - Sun , et al. December 13, 2	2011-12-13
Spacer-less transistor integration scheme for high-K gate dielectrics and small gate-to-gate spaces applicable to Si, SiGe and strained silicon schemes Grant 7,955,919 - Pritchard , et al. June 7, 2	2011-06-07
Eliminate IMC cracking in post wirebonded dies: macro level stress reduction by modifying dielectric/metal film stack in be layers during Cu/Low-K processing Grant 7,531,442 - Pallinti , et al. May 12, 2	2009-05-12
Spacer-less Transistor Integration Scheme For High-k Gate Dielectrics And Small Gate-to-gate Spaces Applicable To Si, Sige And Strained Silicon Schemes App 20080102583 - Pritchard; David ; et al.	2008-05-01
Eliminate IMC cracking in post wirebonded dies: macro level stress reduction by modifying dielectric/metal film stack in be layers during Cu/Low-K processing App 20070123024 - Pallinti; Jayanthi ; et al.	2007-05-31
Alternate pad structures/passivation inegration schemes to reduce or eliminate IMC cracking in post wire bonded dies during Cu/Low-K BEOL processing App 20070114667 - Bhatt; Hemanshu ; et al.	2007-05-24
Reduction of macro level stresses in copper/Low-K wafers by altering aluminum pad/passivation stack to reduce or eliminate IMC cracking in post wire bonded dies App 20070102812 - Sun; Sey-Shing ; et al.	2007-05-10
Reduce or eliminate IMC cracking in post wire bonded dies by doping aluminum used in bond pads during Cu/Low-k BEOL processing Grant 7,205,673 - Pallinti , et al. April 17, 2	2007-04-17
Mechanism for improving the structural integrity of low-k films Grant 6,982,206 - Berman , et al. January 3, 2	2006-01-03
Spacer-less transistor integration scheme for high-k gate dielectrics and small gate-to-gate spaces applicable to Si, SiGe strained silicon schemes App 20050191812 - Pritchard, David ; et al.	2005-09-01
Semiconductor wafer arrangement of a semiconductor wafer Grant 6,707,114 - May , et al. March 16, 2	2004-03-16

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