Benavides; John A.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Benavides; John A..The latest application filed is for "system and method for generating a trigger signal".

Company Profile

0.8.7

Benavides; John A. - Garland TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
System and method to qualify data capture Grant 7,809,991 - Johnson , et al. October 5, 2	2010-10-05
System and method for data analysis Grant 7,752,016 - Johnson , et al. July 6, 2	2010-07-06
System and method for generating a trigger signal Grant 7,348,799 - Benavides , et al. March 25, 2	2008-03-25
System and method to control data capture Grant 7,228,472 - Johnson , et al. June 5, 2	2007-06-05
System and method for generating a trigger signal App 20060170452 - Benavides; John A. ; et al.	2006-08-03
System and method to qualify data capture App 20060156290 - Johnson; Tyler J. ; et al.	2006-07-13
System and method for data analysis App 20060155516 - Johnson; Tyler J. ; et al.	2006-07-13
System and method to control data capture App 20060156102 - Johnson; Tyler J. ; et al.	2006-07-13
Method and system for sensing IC package orientation in sockets App 20040242054 - Benavides, John A. ; et al.	2004-12-02
Method and system for sensing IC package orientation in sockets App 20040242053 - Benavides, John A. ; et al.	2004-12-02
Method and system for improving testability and reducing test time for packaged integrated circuits App 20040201394 - Benavides, John A.	2004-10-14
Method and system for sensing the status of a ZIF socket lever Grant 6,786,761 - Benavides September 7, 2	2004-09-07
Method and system for sensing IC package orientation in sockets Grant 6,786,760 - Benavides , et al. September 7, 2	2004-09-07
System and method for testing an interface between two digital integrated circuits Grant 6,634,005 - Lindsay , et al. October 14, 2	2003-10-14
System and method for parallel testing of IEEE 1149.1 compliant integrated circuits Grant 6,618,827 - Benavides September 9, 2	2003-09-09

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