Barth; Richard M.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Barth; Richard M..The latest application filed is for "chip having register to store value that represents adjustment to reference voltage".

Company Profile

0.100.69

Barth; Richard M. - Palo Alto CA US
Barth; Richard M. - Ashland OR

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Controlling DRAM at time DRAM ready to receive command when exiting power down Grant 8,756,395 - Barth , et al. June 17, 2	2014-06-17
Method and apparatus for indicating mask information Grant 8,560,797 - Barth , et al. October 15, 2	2013-10-15
Chip Having Register to Store Value that Represents Adjustment to Reference Voltage App 20130227214 - Horowitz; Mark A. ; et al.	2013-08-29
Chip having register to store value that represents adjustment to reference voltage Grant 8,458,385 - Horowitz , et al. June 4, 2	2013-06-04
Memory device having multiple power modes Grant 8,305,839 - Tsern , et al. November 6, 2	2012-11-06
Chip Having Register to Store Value that Represents Adjustment to Reference Voltage App 20120268199 - Horowitz; Mark A. ; et al.	2012-10-25
Method and apparatus for adjusting the performance of a synchronous memory system Grant 8,296,540 - Garlepp , et al. October 23, 2	2012-10-23
Method Of Operation Of A Memory Device And System Including Initialization At A First Frequency And Operation At A Second Frequencey And A Power Down Exit Mode App 20120216059 - Barth; Richard M. ; et al.	2012-08-23
Method of controlling a memory device having multiple power modes Grant 8,248,884 - Tsern , et al. August 21, 2	2012-08-21
Method and Apparatus for Delaying Write Operations App 20120173811 - Barth; Richard M. ; et al.	2012-07-05
Method and Apparatus for Indicating Mask Information App 20120173810 - Barth; Richard M. ; et al.	2012-07-05
Memory controller and method utilizing equalization co-efficient setting Grant 8,214,570 - Horowitz , et al. July 3, 2	2012-07-03
Memory controller for controlling write signaling Grant 8,205,056 - Barth , et al. June 19, 2	2012-06-19
Memory Device Having Multiple Power Modes App 20120113738 - Tsern; Ely K. ; et al.	2012-05-10
Memory Device Having Multiple Power Modes App 20120057424 - Tsern; Ely K. ; et al.	2012-03-08
Method of operation of a memory device and system including initialization at a first frequency and operation at a second frequency and a power down exit mode Grant 8,127,152 - Barth , et al. February 28, 2	2012-02-28
Memory Controller for Controlling Write Signaling App 20120005437 - Barth; Richard M. ; et al.	2012-01-05
Memory Controller and Method Utilizing Equalization Co-Efficient Setting App 20110289245 - Horowitz; Mark A. ; et al.	2011-11-24
Memory write signaling and methods thereof Grant 8,019,958 - Barth , et al. September 13, 2	2011-09-13
System and dynamic random access memory device having a receiver Grant 8,001,305 - Horowitz , et al. August 16, 2	2011-08-16
Memory device having multiple power modes Grant 7,986,584 - Tsern , et al. July 26, 2	2011-07-26
Memory Device Having Multiple Power Modes App 20110090755 - Tsern; Ely K. ; et al.	2011-04-21
Memory Write Signaling and Methods Thereof App 20100332719 - Barth; Richard M. ; et al.	2010-12-30
Interface for a semiconductor memory device and method for controlling the interface Grant 7,793,039 - Barth , et al. September 7, 2	2010-09-07
Memory Device Having a Read Pipeline and a Delay Locked Loop App 20100046314 - Tsern; Ely K. ; et al.	2010-02-25
Memory device having a read pipeline and a delay locked loop Grant 7,626,880 - Tsern , et al. December 1, 2	2009-12-01
System and Dynamic Random Access Memory Device Having a Receiver App 20090248971 - Horowitz; Mark A. ; et al.	2009-10-01
System for a memory device having a power down mode and method Grant 7,581,121 - Barth , et al. August 25, 2	2009-08-25
Memory device having a power down exit register Grant 7,574,616 - Barth , et al. August 11, 2	2009-08-11
System and module including a memory device having a power down mode Grant 7,571,330 - Barth , et al. August 4, 2	2009-08-04
Integrated circuit memory device and signaling method for adjusting drive strength based on topography of integrated circuit devices Grant 7,565,468 - Horowitz , et al. July 21, 2	2009-07-21
Integrated circuit device and signaling method with topographic dependent equalization coefficient Grant 7,546,390 - Horowitz , et al. June 9, 2	2009-06-09
Integrated circuit device and signaling method with phase control based on information in external memory device Grant 7,539,802 - Horowitz , et al. May 26, 2	2009-05-26
Integrated Circuit Memory Device Having Delayed Write Timing Based on Read Response Time App 20090129178 - Barth; Richard M. ; et al.	2009-05-21
Expandable slave device system with buffered subsystems Grant 7,536,494 - Garlepp , et al. May 19, 2	2009-05-19
Integrated circuit memory device having delayed write timing based on read response time Grant 7,496,709 - Barth , et al. February 24, 2	2009-02-24
Method And Apparatus For Adjusting The Performance Of A Synchronous Memory System App 20080162759 - Garlepp; Bruno Werner ; et al.	2008-07-03
Integrated circuit memory device having delayed write timing based on read response time App 20080091907 - Barth; Richard M. ; et al.	2008-04-17
Integrated circuit memory device having delayed write capability Grant 7,360,050 - Barth , et al. April 15, 2	2008-04-15
Apparatus and method for pipelined memory operations Grant 7,353,357 - Barth , et al. April 1, 2	2008-04-01
Memory Device Having a Configurable Oscillator for Refresh Operation Grant 7,349,279 - Tsern , et al. March 25, 2	2008-03-25
Integrated Circuit Device and Signaling Method with Phase Control Based on Information in External Memory Device App 20080071951 - Horowitz; Mark A. ; et al.	2008-03-20
Integrated Circuit Memory Device and Signaling Method with Topographic Dependent Signaling App 20080052440 - Horowitz; Mark A. ; et al.	2008-02-28
Integrated Circuit Device and Signaling Method with Topographic Dependent Equalization Coefficient App 20080052434 - Horowitz; Mark A. ; et al.	2008-02-28
Method and apparatus for adjusting the performance of a synchronous memory system Grant 7,337,294 - Garlepp , et al. February 26, 2	2008-02-26
Apparatus and method for pipelined memory operations Grant 7,330,951 - Barth , et al. February 12, 2	2008-02-12
Integrated circuit memory device having delayed write timing based on read response time Grant 7,330,952 - Barth , et al. February 12, 2	2008-02-12
Memory system having delayed write timing Grant 7,330,953 - Barth , et al. February 12, 2	2008-02-12
Power control system for synchronous memory device Grant 7,320,082 - Tsern , et al. January 15, 2	2008-01-15
Memory Device Having a Delay Locked Loop and Multiple Power Modes App 20080002516 - Tsern; Ely K. ; et al.	2008-01-03
Method and apparatus for fail-safe resynchronization with minimum latency Grant 7,288,973 - Zerbe , et al. October 30, 2	2007-10-30
Integrated circuit memory device with delayed write command processing Grant 7,287,119 - Barth , et al. October 23, 2	2007-10-23
Integrated Circuit Memory Device Having Delayed Write Timing Based on Read Response Time App 20070242532 - Barth; Richard M. ; et al.	2007-10-18
Integrated Circuit Device that Stores a Value Representative of an Equalization Co-Efficient Setting App 20070239914 - Horowitz; Mark A. ; et al.	2007-10-11
Method of transferring data by transmitting lower order and upper order memory address bits in separate words with respective op codes and start information Grant RE39,879 - Barth , et al. October 9, 2	2007-10-09
Expandable Slave Device System with Buffered Subsystems App 20070220188 - Garlepp; Bruno W. ; et al.	2007-09-20
Memory System Having Delayed Write Timing App 20070198868 - Barth; Richard M. ; et al.	2007-08-23
Integrated Circuit Memory Device with Delayed Write Command Processing App 20070159912 - Barth; Richard M. ; et al.	2007-07-12
Memory Device Having a Configurable Oscillator for Refresh Operation App 20070147155 - Tsern; Ely K. ; et al.	2007-06-28
Integrated Circuit Memory Device Having Delayed Write Capability App 20070147143 - Barth; Richard M. ; et al.	2007-06-28
Apparatus and Method for Pipelined Memory Operations App 20070140035 - Barth; Richard M. ; et al.	2007-06-21
Expandable slave device system Grant 7,222,209 - Garlepp , et al. May 22, 2	2007-05-22
Method And Apparatus For Adjusting The Performance Of A Synchronous Memory System App 20070083700 - Garlepp; Bruno Werner ; et al.	2007-04-12
Integrated circuit memory device having write latency function Grant 7,197,611 - Barth , et al. March 27, 2	2007-03-27
Integrated circuit device that stores a value representative of an equalization co-efficient setting Grant 7,174,400 - Horowitz , et al. February 6, 2	2007-02-06
Method and apparatus for adjusting the performance of a synchronous memory system Grant 7,149,856 - Garlepp , et al. December 12, 2	2006-12-12
Memory device having a configurable oscillator for refresh operation Grant 7,142,475 - Tsern , et al. November 28, 2	2006-11-28
Chip-to-chip communication system using an ac-coupled bus and devices employed in same Grant 7,130,944 - Perino , et al. October 31, 2	2006-10-31
Integrated circuit device that stores a value representative of a drive strength setting Grant 7,051,130 - Horowitz , et al. May 23, 2	2006-05-23
Memory device having programmable drive strength setting Grant 7,051,129 - Horowitz , et al. May 23, 2	2006-05-23
Memory system with channel multiplexing of multiple memory devices Grant 7,039,782 - Garrett, Jr. , et al. May 2, 2	2006-05-02
Integrated circuit with transmit phase adjustment Grant 7,032,057 - Horowitz , et al. April 18, 2	2006-04-18
Apparatus and method for topography dependent signaling Grant 7,032,058 - Horowitz , et al. April 18, 2	2006-04-18
Apparatus and method for topography dependent signaling Grant 7,024,502 - Horowitz , et al. April 4, 2	2006-04-04
Apparatus and method for pipelined memory operations App 20060059299 - Barth; Richard M. ; et al.	2006-03-16
Memory controller with power management logic Grant 7,003,639 - Tsern , et al. February 21, 2	2006-02-21
Method and apparatus for fail-safe resynchronization with minimum latency App 20060022724 - Zerbe; Jared LeVan ; et al.	2006-02-02
Integrated circuit device that stores a value representative of an equalization co-efficient setting App 20050251602 - Horowitz, Mark A. ; et al.	2005-11-10
Apparatus and method for pipelined memory operations Grant 6,963,956 - Barth , et al. November 8, 2	2005-11-08
System for a memory device having a power down mode and method App 20050235130 - Barth, Richard M. ; et al.	2005-10-20
System and module including a memory device having a power down mode App 20050216654 - Barth, Richard M. ; et al.	2005-09-29
Phase comparator capable of tolerating a non-50% duty-cycle clocks Grant 6,949,958 - Zerbe , et al. September 27, 2	2005-09-27
Method and apparatus for initializing dynamic random access memory (DRAM) devices App 20050193183 - Barth, Richard M. ; et al.	2005-09-01
Memory device having a read pipeline and a delay locked loop App 20050180255 - Tsern, Ely K. ; et al.	2005-08-18
High performance cost optimized memory App 20050160241 - Barth, Richard M. ; et al.	2005-07-21
Method of operation and controlling a memory device App 20050154817 - Barth, Richard M. ; et al.	2005-07-14
Memory device and method of operation of a memory device App 20050154853 - Barth, Richard M. ; et al.	2005-07-14
Apparatus and method for topography dependent signaling App 20050149659 - Horowitz, Mark A. ; et al.	2005-07-07
Chip-to-chip communication system using an ac-coupled bus and devices employed in same App 20050135182 - Perino, Donald V. ; et al.	2005-06-23
Methods of operation of a memory device and system App 20050120161 - Barth, Richard M. ; et al.	2005-06-02
Memory device having a power down exit register App 20050060487 - Barth, Richard M. ; et al.	2005-03-17
High performance cost optimized memory Grant 6,868,474 - Barth , et al. March 15, 2	2005-03-15
Memory device having a configurable oscillator for refresh operation App 20050041501 - Tsern, Ely K. ; et al.	2005-02-24
Integrated circuit device having a capacitive coupling element Grant 6,854,030 - Perino , et al. February 8, 2	2005-02-08
Method and apparatus for configuring access times of memory devices Grant 6,842,864 - Barth , et al. January 11, 2	2005-01-11
Memory module with offset data lines and bit line swizzle configuration Grant 6,839,266 - Garrett, Jr. , et al. January 4, 2	2005-01-04
Memory device having programmable drive strength setting App 20040243753 - Horowitz, Mark A. ; et al.	2004-12-02
Memory controller with power management logic App 20040230739 - Tsern, Ely K. ; et al.	2004-11-18
Expandable slave device system App 20040196064 - Garlepp, Bruno W. ; et al.	2004-10-07
Apparatus and method for topography dependent signaling App 20040199690 - Horowitz, Mark A. ; et al.	2004-10-07
Apparatus and method for pipelined memory operations App 20040193788 - Barth, Richard M. ; et al.	2004-09-30
Method and apparatus for adjusting the performance of a synchronous memory system App 20040168036 - Garlepp, Bruno Werner ; et al.	2004-08-26
Pipelined memory controller and method of controlling access to memory devices in a memory system Grant 6,782,460 - Satagopan , et al. August 24, 2	2004-08-24
Dram core refresh with reduced spike current Grant 6,778,458 - Tsern , et al. August 17, 2	2004-08-17
Power control system for synchronous memory device App 20040141404 - Tsern, Ely K. ; et al.	2004-07-22
Apparatus and method for topography dependent signaling App 20040139257 - Horowitz, Mark A. ; et al.	2004-07-15
System and method for controlling retire buffer operation in a memory system App 20040139293 - Barth, Richard M. ; et al.	2004-07-15
Memory controller with power management logic Grant 6,754,783 - Tsern , et al. June 22, 2	2004-06-22
Memory system with channel multiplexing of multiple memory devices App 20040081005 - Garrett, Billy Wayne JR. ; et al.	2004-04-29
Apparatus and method for pipelined memory operations Grant 6,718,431 - Barth , et al. April 6, 2	2004-04-06
Dram core refresh with reduced spike current App 20040062120 - Tsern, Ely K. ; et al.	2004-04-01
Memory system with channel multiplexing of multiple memory devices Grant 6,708,248 - Garrett, Jr. , et al. March 16, 2	2004-03-16
Power control system for synchronous memory device Grant 6,701,446 - Tsern , et al. March 2, 2	2004-03-02
Expandable slave device system Grant 6,687,780 - Garlepp , et al. February 3, 2	2004-02-03
Apparatus and method for topography dependent signaling Grant 6,684,263 - Horowitz , et al. January 27, 2	2004-01-27
System and method for controlling retire buffer operation in a memory system Grant 6,640,292 - Barth , et al. October 28, 2	2003-10-28
Pipelined memory controller and method of controlling access to memory devices in a memory system App 20030196059 - Satagopan, Ramprasad ; et al.	2003-10-16
Memory controller with power management logic App 20030159004 - Tsern, Ely K. ; et al.	2003-08-21
DRAM core refresh with reduced spike current Grant 6,597,616 - Tsern , et al. July 22, 2	2003-07-22
Apparatus and method for topography dependent signaling App 20030120848 - Horowitz, Mark A. ; et al.	2003-06-26
Integrated circuit device having a capacitive coupling element App 20030105908 - Perino, Donald V. ; et al.	2003-06-05
Pipelined memory controller and method of controlling access to memory devices in a memory system Grant 6,571,325 - Satagopan , et al. May 27, 2	2003-05-27
Synchronous memory device having a temperature register Grant 6,553,452 - Garlepp , et al. April 22, 2	2003-04-22
Method and apparatus for fail-safe resynchronization with minimum latency App 20030053489 - Zerbe, Jared LeVan ; et al.	2003-03-20
Memory controller with power management logic Grant 6,523,089 - Tsern , et al. February 18, 2	2003-02-18
Apparatus and method for topography dependent signaling Grant 6,516,365 - Horowitz , et al. February 4, 2	2003-02-04
Method and apparatus for adjusting the performance of a synchronous memory system Grant 6,513,103 - Garlepp , et al. January 28, 2	2003-01-28
Chip-to-chip communication system using an ac-coupled bus and devices employed in same Grant 6,496,889 - Perino , et al. December 17, 2	2002-12-17
High performance cost optimized memory App 20020178324 - Barth, Richard M. ; et al.	2002-11-28
Method and apparatus for fail-safe resynchronization with minimum latency Grant 6,473,439 - Zerbe , et al. October 29, 2	2002-10-29
Apparatus and method for pipelined memory operations App 20020095560 - Barth, Richard M. ; et al.	2002-07-18
Method and apparatus for adjusting the performance of a synchronous memory system App 20020087820 - Garlepp, Bruno Werner ; et al.	2002-07-04
DRAM core refresh with reduced spike current App 20020071329 - Tsern, Ely K. ; et al.	2002-06-13
Apparatus and method for topography dependent signaling App 20020056016 - Horowitz, Mark A. ; et al.	2002-05-09
Memory device and system including a low power interface Grant 6,378,018 - Tsern , et al. April 23, 2	2002-04-23
Apparatus and method for thermal regulation in memory subsystems Grant 6,373,768 - Woo , et al. April 16, 2	2002-04-16
High speed memory system capable of selectively operating in non-chip-kill and chip-kill modes Grant 6,370,668 - Garrett, Jr. , et al. April 9, 2	2002-04-09
Memory controller with power management logic App 20020040416 - Tsern, Ely K. ; et al.	2002-04-04
Apparatus and method for pipelined memory operations Grant 6,356,975 - Barth , et al. March 12, 2	2002-03-12
Apparatus and method for refreshing subsets of memory devices in a memory system Grant 6,345,009 - Tsern , et al. February 5, 2	2002-02-05
DRAM core refresh with reduced spike current Grant 6,343,042 - Tsern , et al. January 29, 2	2002-01-29
Power control system for synchronous memory device App 20010047493 - Tsern, Ely K. ; et al.	2001-11-29
Apparatus and method for topography dependent signaling Grant 6,321,282 - Horowitz , et al. November 20, 2	2001-11-20
Rambus DRAM (RDRAM) apparatus and method for performing refresh operations Grant 6,310,814 - Hampel , et al. October 30, 2	2001-10-30
Memory and method for sensing sub-groups of memory elements Grant RE37,409 - Barth , et al. October 16, 2	2001-10-16
Apparatus And Method For Thermal Regulation In Memory Subsystems App 20010014049 - WOO, STEVEN C. ; et al.	2001-08-16
DRAM core refresh with reduced spike current Grant 6,266,292 - Tsern , et al. July 24, 2	2001-07-24
Power control system for synchronous memory device Grant 6,263,448 - Tsern , et al. July 17, 2	2001-07-17
Apparatus and method for device timing compensation Grant 6,226,754 - Ware , et al. May 1, 2	2001-05-01
Apparatus and method for bus timing compensation Grant 6,226,757 - Ware , et al. May 1, 2	2001-05-01
Apparatus and method for refreshing subsets of memory devices in a memory system Grant 6,178,130 - Tsern , et al. January 23, 2	2001-01-23
Method and apparatus for initializing dynamic random access memory (DRAM) devices by levelizing a read domain Grant 6,154,821 - Barth , et al. November 28, 2	2000-11-28
Apparatus for sharing sense amplifiers between memory banks Grant 6,134,172 - Barth , et al. October 17, 2	2000-10-17
High performance cost optimized memory with delayed memory writes Grant 6,075,730 - Barth , et al. June 13, 2	2000-06-13
Method and apparatus for sharing sense amplifiers between memory banks Grant 6,075,743 - Barth , et al. June 13, 2	2000-06-13
Dram core refresh with reduced spike current Grant 6,075,744 - Tsern , et al. June 13, 2	2000-06-13
Method and apparatus for writing to memory components Grant 5,956,284 - Ware , et al. September 21, 1	1999-09-21
Memory and method for sensing sub-groups of memory elements Grant 5,748,554 - Barth , et al. May 5, 1	1998-05-05
Method and apparatus for writing to memory components Grant 5,680,361 - Ware , et al. October 21, 1	1997-10-21
Dynamic random access memory system Grant 5,511,024 - Ware , et al. April 23, 1	1996-04-23
Method and circuitry for minimizing clock-data skew in a bus system Grant 5,432,823 - Gasbarro , et al. July 11, 1	1995-07-11
Dynamic random access memory system Grant 5,430,676 - Ware , et al. July 4, 1	1995-07-04
Method and apparatus for power control in devices Grant 5,337,285 - Ware , et al. August 9, 1	1994-08-09
Phase controlled synchronization for direct sequence spread-spectrum communication systems Grant 5,101,417 - Richley , et al. March 31, 1	1992-03-31
Multiprocessor cache memory housekeeping Grant 5,045,996 - Barth , et al. September 3, 1	1991-09-03

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.