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name:-0.04524302482605
name:-0.037492036819458
name:-0.0094420909881592
Badaroglu; Mustafa Patent Filings

Badaroglu; Mustafa

Patent Applications and Registrations

Patent applications and USPTO patent grants for Badaroglu; Mustafa.The latest application filed is for "integrated circuits employing varied gate topography between an active gate region(s) and a field gate region(s) in a gate(s) fo".

Company Profile
7.31.37
  • Badaroglu; Mustafa - Kessel-Lo BE
  • Badaroglu; Mustafa - Kessel-Lo Leuven
  • Badaroglu; Mustafa - Leuven BE
  • Badaroglu; Mustafa - Waterlelielaan BE
  • Badaroglu; Mustafa - Heverlee BE
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Hybrid metallization interconnects for power distribution and signaling
Grant 11,121,075 - Badaroglu , et al. September 14, 2
2021-09-14
Method of forming gate of semiconductor device and semiconductor device having same
Grant 10,607,896 - Ragnarsson , et al.
2020-03-31
Integrated Circuits Employing Varied Gate Topography Between An Active Gate Region(s) And A Field Gate Region(s) In A Gate(s) Fo
App 20200020688 - Badaroglu; Mustafa ;   et al.
2020-01-16
Integrated Circuits (ics) Made Using Extreme Ultraviolet (euv) Patterning And Methods For Fabricating Such Ics
App 20200006122 - Badaroglu; Mustafa ;   et al.
2020-01-02
Hybrid Metallization Interconnects For Power Distribution And Signaling
App 20190295942 - BADAROGLU; Mustafa ;   et al.
2019-09-26
Integrated circuits employing a field gate(s) without dielectric layers and/or work function metal layers for reduced gate layout parasitic resistance, and related methods
Grant 10,411,091 - Badaroglu , et al. Sept
2019-09-10
Integrating a gate-all-around (GAA) field-effect transistor(s) (FET(S)) and a finFET(s) on a common substrate of a semiconductor die
Grant 10,332,881 - Badaroglu , et al.
2019-06-25
Standard cell circuits employing voltage rails electrically coupled to metal shunts for reducing or avoiding increases in voltage drop
Grant 10,283,526 - Zhu , et al.
2019-05-07
Digital Current Measurement For In-situ Device Monitoring
App 20190107569 - Kidd; David ;   et al.
2019-04-11
Nanowire Device With Reduced Parasitics
App 20190067435 - Badaroglu; Mustafa ;   et al.
2019-02-28
Nanowire device with reduced parasitics
Grant 10,157,992 - Badaroglu , et al. Dec
2018-12-18
Selectively recessing trench isolation in three-dimensional (3D) transistors to vary channel structure exposures from trench isolation to control drive strength
Grant 10,109,646 - Badaroglu October 23, 2
2018-10-23
Standard cell circuits employing high aspect ratio voltage rails for reduced resistance
Grant 10,090,244 - Xu , et al. October 2, 2
2018-10-02
Semiconductor device having a gap defined therein
Grant 10,079,293 - Xu , et al. September 18, 2
2018-09-18
Vertically stacked nanowire field effect transistors
Grant 10,043,796 - Machkaoutsan , et al. August 7, 2
2018-08-07
Semiconductor Devices Employing Reduced Area Conformal Contacts To Reduce Parasitic Capacitance, And Related Methods
App 20180212029 - Xu; Jeffrey Junhao ;   et al.
2018-07-26
Nanowire channel structures of continuously stacked nanowires for complementary metal oxide semiconductor (CMOS) devices
Grant 10,032,678 - Xu , et al. July 24, 2
2018-07-24
Standard Cell Circuits Employing Voltage Rails Electrically Coupled To Metal Shunts For Reducing Or Avoiding Increases In Voltage Drop
App 20180175060 - Zhu; John Jianhong ;   et al.
2018-06-21
Minimum track standard cell circuits for reduced area
Grant 9,985,014 - Xu , et al. May 29, 2
2018-05-29
Semiconductor Device Having A Gap Defined Therein
App 20180114848 - Xu; Jeffrey Junhao ;   et al.
2018-04-26
Contact wrap around structure
Grant 9,953,979 - Xu , et al. April 24, 2
2018-04-24
Minimum Track Standard Cell Circuits For Reduced Area
App 20180076189 - Xu; Jeffrey Junhao ;   et al.
2018-03-15
Standard Cell Circuits Employing High Aspect Ratio Voltage Rails For Reduced Resistance
App 20180033729 - Xu; Jeffrey Junhao ;   et al.
2018-02-01
Semiconductor device having a gap defined therein
Grant 9,871,121 - Xu , et al. January 16, 2
2018-01-16
Adjacent device isolation
Grant 9,824,936 - Machkaoutsan , et al. November 21, 2
2017-11-21
Method Of Forming Gate Of Semiconductor Device And Semiconductor Device Having Same
App 20170330801 - Ragnarsson; Lars-Ake ;   et al.
2017-11-16
Self-aligned structure
Grant 9,799,560 - Song , et al. October 24, 2
2017-10-24
Self-aligned metal cut and via for back-end-of-line (BEOL) processes for semiconductor integrated circuit (IC) fabrication, and related processes and devices
Grant 9,793,164 - Machkaoutsan , et al. October 17, 2
2017-10-17
Magnetic tunnel junction (MTJ) device array
Grant 9,728,718 - Machkaoutsan , et al. August 8, 2
2017-08-08
Vertically Stacked Nanowire Field Effect Transistors
App 20170221884 - Machkaoutsan; Vladimir ;   et al.
2017-08-03
Nanowire Device With Reduced Parasitics
App 20170186846 - Badaroglu; Mustafa ;   et al.
2017-06-29
Reduced height M1 metal lines for local on-chip routing
Grant 9,666,481 - Song , et al. May 30, 2
2017-05-30
Self-aligned Metal Cut And Via For Back-end-of-line (beol) Processes For Semiconductor Integrated Circuit (ic) Fabrication, And Related Processes And Devices
App 20170140986 - Machkaoutsan; Vladimir ;   et al.
2017-05-18
Nanowire Channel Structures Of Continuously Stacked Heterogeneous Nanowires For Complementary Metal Oxide Semiconductor (cmos) Devices
App 20170110541 - Xu; Jeffrey Junhao ;   et al.
2017-04-20
Nanowire Channel Structures Of Continuously Stacked Nanowires For Complementary Metal Oxide Semiconductor (cmos) Devices
App 20170110374 - Xu; Jeffrey Junhao ;   et al.
2017-04-20
Method And Apparatus For Source-drain Junction Formation In A Finfet With In-situ Doping
App 20170104088 - MACHKAOUTSAN; Vladimir ;   et al.
2017-04-13
Magnetic Tunnel Junction (mtj) Device Array
App 20170104153 - Machkaoutsan; Vladimir ;   et al.
2017-04-13
Magnetic tunnel junction (MTJ) device array
Grant 9,570,509 - Machkaoutsan , et al. February 14, 2
2017-02-14
Method and apparatus for source-drain junction formation in a FinFET with in-situ doping
Grant 9,564,518 - Machkaoutsan , et al. February 7, 2
2017-02-07
Adjacent Device Isolation
App 20170033020 - MACHKAOUTSAN; Vladimir ;   et al.
2017-02-02
Adjacent device isolation
Grant 9,502,414 - Machkaoutsan , et al. November 22, 2
2016-11-22
Sub-fin device isolation
Grant 9,496,181 - Song , et al. November 15, 2
2016-11-15
Self-aligned Structure
App 20160293485 - Song; Stanley Seungchul ;   et al.
2016-10-06
Adjacent Device Isolation
App 20160254261 - MACHKAOUTSAN; Vladimir ;   et al.
2016-09-01
Reduced Height M1 Metal Lines For Local On-chip Routing
App 20160240437 - SONG; Stanley Seungchul ;   et al.
2016-08-18
Magnetic Tunnel Junction (mtj) Device Array
App 20160225817 - Machkaoutsan; Vladimir ;   et al.
2016-08-04
Sub-fin Device Isolation
App 20160181161 - SONG; Stanley Seungchul ;   et al.
2016-06-23
Contact Wrap Around Structure
App 20160148936 - XU; Jeffrey Junhao ;   et al.
2016-05-26
Reduced height M1 metal lines for local on-chip routing
Grant 9,349,686 - Song , et al. May 24, 2
2016-05-24
Semiconductor Package With Incorporated Inductance Element
App 20160133614 - GU; Shiqun ;   et al.
2016-05-12
Method And Apparatis For Source-drain Junction Formation Finfet With Quantum Barrier And Ground Plane Doping
App 20160087070 - MACHKAOUTSAN; Vladimir ;   et al.
2016-03-24
Device Including Cavity And Self-aligned Contact And Method Of Fabricating The Same
App 20160049487 - Xu; Jeffrey Junhao ;   et al.
2016-02-18
Reduced Height M1 Metal Lines For Local On-chip Routing
App 20150262930 - SONG; Stanley Seungchul ;   et al.
2015-09-17
Semiconductor Device Having A Gap Defined Therein
App 20150255571 - Xu; Jeffrey Junhao ;   et al.
2015-09-10
Test circuit for testing through-silicon-vias in 3D integrated circuits
Grant 8,773,157 - Badaroglu , et al. July 8, 2
2014-07-08
Fault Mode Circuits
App 20130002272 - Badaroglu; Mustafa ;   et al.
2013-01-03
Devices comprising delay line for applying variable delay to clock signal
Grant 8,233,579 - Badaroglu July 31, 2
2012-07-31
Auto-calibrating A Magnetic Field Sensor
App 20120133356 - Charlier; Olivier ;   et al.
2012-05-31
Method of auto calibrating a magnetic field sensor for drift and structure therefor
Grant 8,134,358 - Charlier , et al. March 13, 2
2012-03-13
Method and apparatus for minimizing the influence of a digital sub-circuit on at least partially digital circuits
Grant 7,987,382 - Badaroglu July 26, 2
2011-07-26
Method for determining a pulse position in a signal
Grant 7,885,326 - Desset , et al. February 8, 2
2011-02-08
Devices Comprising Delay Line for Applying Variable Delay to Clock Signal
App 20100225369 - Badaroglu; Mustafa
2010-09-09
Auto-calibration Of Magnetic Sensor
App 20080238410 - Charlier; Olivier ;   et al.
2008-10-02
Method for determining a pulse position in a signal
App 20080025386 - Desset; Claude ;   et al.
2008-01-31
Method and apparatus for minimizing the influence of a digital sub-circuit on at least partially digital circuits
App 20070035428 - Badaroglu; Mustafa
2007-02-15
Method, apparatus and computer program product for determination of noise in mixed signal systems
Grant 6,941,258 - Van Heijningen , et al. September 6, 2
2005-09-06
Method, apparatus and computer program product for determination of noise in mixed signal systems
App 20020022951 - Heijningen, Marc Van ;   et al.
2002-02-21

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