Babcock; Jeffrey A.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Babcock; Jeffrey A..The latest application filed is for "integrated circuit with resurf region biasing under buried insulator layers".

Company Profile

3.51.48

Babcock; Jeffrey A. - Sunnyvale CA
Babcock; Jeffrey A. - Santa Clara CA
Babcock; Jeffrey A. - Richardson TX US
Babcock; Jeffrey A. - Neufahrn DE
Babcock; Jeffrey A. - Neufahm DE
Babcock, Jeffrey A. - Dallas TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Integrated circuit with resurf region biasing under buried insulator layers Grant 11,024,649 - Sadovnikov , et al. June 1, 2	2021-06-01
Integrated Circuit With Resurf Region Biasing Under Buried Insulator Layers App 20200227440 - Sadovnikov; Alexei ; et al.	2020-07-16
Integrated circuit with resurf region biasing under buried insulator layers Grant 10,636,815 - Sadovnikov , et al.	2020-04-28
Integrated circuit with resurf region biasing under buried insulator layers Grant 10,504,921 - Sadovnikov , et al. Dec	2019-12-10
Integrated Circuit With Resurf Region Biasing Under Buried Insulator Layers App 20190252410 - Sadovnikov; Alexei ; et al.	2019-08-15
Method for creating the high voltage complementary BJT with lateral collector on bulk substrate with resurf effect Grant 10,269,895 - Babcock , et al.	2019-04-23
Method For Creating The High Voltage Complementary Bjt With Lateral Collector On Bulk Substrate With Resurf Effect App 20170309703 - BABCOCK; Jeffrey A. ; et al.	2017-10-26
Method for creating the high voltage complementary BJT with lateral collector on bulk substrate with resurf effect Grant 9,741,790 - Babcock , et al. August 22, 2	2017-08-22
Integrated Circuit With Resurf Region Biasing Under Buried Insulator Layers App 20170194352 - Sadovnikov; Alexei ; et al.	2017-07-06
HV complementary bipolar transistors with lateral collectors on SOI with resurf regions under buried oxide Grant 9,640,611 - Sadovnikov , et al. May 2, 2	2017-05-02
BICMOS device having commonly defined gate shield in an ED-CMOS transistor and base in a bipolar transistor Grant 9,633,994 - Babcock , et al. April 25, 2	2017-04-25
Method of forming a gate shield in an ED-CMOS transistor and a base of a bipolar transistor using BICMOS technologies Grant 9,633,995 - Babcock , et al. April 25, 2	2017-04-25
Method For Creating The High Voltage Complementary Bjt With Lateral Collector On Bulk Substrate With Resurf Effect App 20160233294 - BABCOCK; Jeffrey A. ; et al.	2016-08-11
Method of forming a Gate Shield in an ED-CMOS Transistor and a base of a bipolar transistor using BICMOS Technologies App 20160172245 - Babcock; Jeffrey A. ; et al.	2016-06-16
Method Of Forming A Gate Shield In An Ed-cmos Transistor And A Baseof A Bipolar Transistor Using Bicmos Technologies App 20160172355 - Babcock; Jeffrey A. ; et al.	2016-06-16
Method for creating the high voltage complementary BJT with lateral collector on bulk substrate with resurf effect Grant 9,343,459 - Babcock , et al. May 17, 2	2016-05-17
Method of forming a gate shield in an ED-CMOS transistor and a base of a bipolar transistor using BICMOS technologies Grant 9,306,013 - Babcock , et al. April 5, 2	2016-04-05
Method For Creation Of The Gate Shield In Analog/rf Power Ed-cmos In Sige Bicmos Technologies App 20150340448 - Babcock; Jeffrey A. ; et al.	2015-11-26
Method For Creating The High Voltage Complementary Bjt With Lateral Collector On Bulk Substrate With Resurf Effect App 20150287716 - Babcock; Jeffrey A. ; et al.	2015-10-08
Hv Complementary Bipolar Transistors With Lateral Collectors On Soi With Resurf Regions Under Buried Oxide App 20150270335 - Sadovnikov; Alexei ; et al.	2015-09-24
Schottky diode with control gate for optimization of the on state resistance, the reverse leakage, and the reverse breakdown Grant 8,728,920 - Shafi , et al. May 20, 2	2014-05-20
Advanced CMOS using super steep retrograde wells Grant 8,703,568 - Babcock , et al. April 22, 2	2014-04-22
Non-volatile memory cell having a heating element and a substrate-based control gate Grant 8,669,157 - Babcock , et al. March 11, 2	2014-03-11
SiGe heterojunction bipolar transistor with an improved breakdown voltage-cutoff frequency product Grant 8,648,391 - Babcock , et al. February 11, 2	2014-02-11
Sige Heterojunction Bipolar Transistor With A Shallow Out-diffused P+ Emitter Region App 20130248935 - Babcock; Jeffrey A. ; et al.	2013-09-26
Sige Heterojunction Bipolar Transistor With An Improved Breakdown Voltage-cutoff Frequency Product App 20130249057 - Babcock; Jeffrey A. ; et al.	2013-09-26
SiGe heterojunction bipolar transistor with a shallow out-diffused P+ emitter region Grant 8,525,233 - Babcock , et al. September 3, 2	2013-09-03
Schottky-clamped bipolar transistor with reduced self heating Grant 8,455,980 - Babcock June 4, 2	2013-06-04
Gas detector that utilizes an electric field to assist in the collection and removal of gas molecules Grant 8,453,494 - Babcock , et al. June 4, 2	2013-06-04
Schottky-Clamped Bipolar Transistor with Reduced Self Heating App 20130009271 - Babcock; Jeffrey A.	2013-01-10
Schottky Diode With Control Gate For Optimization Of The On State Resistance, The Reverse Leakage, And The Reverse Breakdown App 20120244689 - Shafi; Zia Alan ; et al.	2012-09-27
Non-volatile Memory Cell Having A Heating Element And A Substrate-based Control Gate App 20120230118 - Babcock; Jeffrey A. ; et al.	2012-09-13
Control of dopant diffusion from buried layers in bipolar integrated circuits Grant 8,247,300 - Babcock , et al. August 21, 2	2012-08-21
Advanced Cmos Using Super Steep Retrograde Wells App 20120164802 - Babcock; Jeffrey A. ; et al.	2012-06-28
Schottky junction-field-effect-transistor (JFET) structures and methods of forming JFET structures Grant 8,207,559 - Babcock , et al. June 26, 2	2012-06-26
Schottky diode with control gate for optimization of the on state resistance, the reverse leakage, and the reverse breakdown Grant 8,193,602 - Shafi , et al. June 5, 2	2012-06-05
Non-volatile memory cell having a heating element and a substrate-based control gate Grant 8,183,621 - Babcock , et al. May 22, 2	2012-05-22
Gas Detector that Utilizes an Electric Field to Assist in the Collection and Removal of Gas Molecules App 20120060587 - Babcock; Jeffrey A. ; et al.	2012-03-15
Advanced CMOS using super steep retrograde wells Grant 8,129,246 - Babcock , et al. March 6, 2	2012-03-06
Schottky Diode with Control Gate for Optimization of the On State Resistance, the Reverse Leakage, and the Reverse Breakdown App 20110254118 - Shafi; Zia Alan ; et al.	2011-10-20
Non-Volatile Memory Cell Having a Heating Element and a Substrate-Based Control Gate App 20110147820 - Babcock; Jeffrey A. ; et al.	2011-06-23
Advanced Cmos Using Super Steep Retrograde Wells App 20110111553 - Babcock; Jeffrey A. ; et al.	2011-05-12
Non-volatile memory cell with heating element Grant 7,919,807 - Babcock , et al. April 5, 2	2011-04-05
Method of forming a semiconductor die with reduced RF attenuation Grant 7,902,013 - Babcock , et al. March 8, 2	2011-03-08
Advanced CMOS using super steep retrograde wells Grant 7,883,977 - Babcock , et al. February 8, 2	2011-02-08
Control Of Dopant Diffusion From Buried Layers In Bipolar Integrated Circuits App 20100279481 - Babcock; Jeffrey A. ; et al.	2010-11-04
Schottky Junction-field-effect-transistor (jfet) Structures And Methods Of Forming Jfet Structures App 20100032731 - Babcock; Jeffrey A. ; et al.	2010-02-11
Advanced CMOS using super steep retrograde wells Grant 7,655,523 - Babcock , et al. February 2, 2	2010-02-02
Semiconductor die with reduced RF attenuation Grant 7,598,575 - Babcock , et al. October 6, 2	2009-10-06
Advanced Cmos Using Super Steep Retrograde Wells App 20090130805 - Babcock; Jeffrey A. ; et al.	2009-05-21
Advanced CMOS using super steep retrograde wells Grant 7,501,324 - Babcock , et al. March 10, 2	2009-03-10
On chip heating for electrical trimming of polysilicon and polysilicon-silicon-germanium resistors and electrically programmable fuses for integrated circuits Grant 7,422,972 - Babcock , et al. September 9, 2	2008-09-09
Advanced CMOS Using Super Steep Retrograde Wells App 20080132012 - Babcock; Jeffrey A. ; et al.	2008-06-05
Method of fabricating an epitaxial silicon-germanium layer and an integrated semiconductor device comprising an epitaxial arsenic in-situ doped silicon-germanium layer Grant 7,217,322 - Babcock , et al. May 15, 2	2007-05-15
Advanced CMOS using super steep retrograde wells Grant 7,199,430 - Babcock , et al. April 3, 2	2007-04-03
Structure of semiconductor device with sinker contact region Grant 7,164,186 - Pinto , et al. January 16, 2	2007-01-16
Advanced CMOS using Super Steep Retrograde Wells App 20060197158 - Babcock; Jeffrey A. ; et al.	2006-09-07
Advanced CMOS using super steep retrograde wells App 20060175657 - Babcock; Jeffrey A. ; et al.	2006-08-10
Advanced CMOS using super steep retrograde wells Grant 7,064,399 - Babcock , et al. June 20, 2	2006-06-20
On chip heating for electrical trimming of polysilicon and polysilicon-silicon-germanium resistors and electrically programmable fuses for integrated circuits App 20050258990 - Babcock, Jeffrey A. ; et al.	2005-11-24
Control of dopant diffusion from buried layers in bipolar integrated circuits App 20050250289 - Babcock, Jeffrey A. ; et al.	2005-11-10
On chip heating for electrical trimming of polysilicon and polysilicon-silicon-germanium resistors and electrically programmable fuses for integrated circuits Grant 6,958,523 - Babcock , et al. October 25, 2	2005-10-25
Lateral heterojunction bipolar transistor Grant 6,927,428 - Babcock , et al. August 9, 2	2005-08-09
Method of fabricating an epitaxial silicon-germanium layer and an integrated semiconductor device comprising an epitaxial arsenic in-situ doped silicon-germanium layer App 20050098093 - Babcock, Jeffrey A. ; et al.	2005-05-12
Method for manufacturing and structure of semiconductor device with sinker contact region App 20050037588 - Pinto, Angelo ; et al.	2005-02-17
Integrated process for high voltage and high performance silicon-on-insulator bipolar devices Grant 6,838,348 - Babcock , et al. January 4, 2	2005-01-04
Method for manufacturing and structure of semiconductor device with shallow trench collector contact region App 20040209433 - Babcock, Jeffrey A. ; et al.	2004-10-21
Integrated process for high voltage and high performance silicon-on-insulator bipolar devices App 20040207046 - Babcock, Jeffrey A. ; et al.	2004-10-21
Method for manufacturing a semiconductor device with sinker contact region Grant 6,806,159 - Pinto , et al. October 19, 2	2004-10-19
Lateral heterojunction bipolar transistor App 20040188802 - Babcock, Jeffrey A. ; et al.	2004-09-30
Lateral heterojunction bipolar transistor Grant 6,794,237 - Babcock , et al. September 21, 2	2004-09-21
Semiconductor device with a collector contact in a depressed well-region Grant 6,774,455 - Babcock , et al. August 10, 2	2004-08-10
Integrated process for high voltage and high performance silicon-on-insulator bipolar devices Grant 6,770,952 - Babcock , et al. August 3, 2	2004-08-03
P-i-n transit time silicon-on-insulator device Grant 6,660,616 - Babcock , et al. December 9, 2	2003-12-09
Zero mask high density metal/insulator/metal capacitor Grant 6,646,323 - Dirnecker , et al. November 11, 2	2003-11-11
Lateral heterojunction bipolar transistor App 20030122154 - Babcock, Jeffrey A. ; et al.	2003-07-03
Method for manufacturing and structure of semiconductor assembly with a shallow trench device region App 20030113980 - Babcock, Jeffrey A.	2003-06-19
Control of dopant diffusion from polysilicon emitters in bipolar integrated circuits App 20030080394 - Babcock, Jeffrey A. ; et al.	2003-05-01
Control of dopant diffusion from buried layers in bipolar integrated circuits App 20030082882 - Babcock, Jeffrey A. ; et al.	2003-05-01
Method for manufacturing and structure of semiconductor device with shallow trench collector contact region App 20030062589 - Babcock, Jeffrey A. ; et al.	2003-04-03
Method for manufacturing and structure of semiconductor device with sinker contact region App 20030062598 - Pinto, Angelo ; et al.	2003-04-03
Integrated process for high voltage and high performance silicon-on-insulator bipolar devices App 20020160562 - Babcock, Jeffrey A. ; et al.	2002-10-31
P-i-n transit time silicon-on-insulator device App 20020100950 - Babcock, Jeffrey A. ; et al.	2002-08-01
Programmable neuron MOSFET on SOI Grant 6,407,425 - Babcock , et al. June 18, 2	2002-06-18
Method of manufacturing a zero mask high density metal/insulator/metal capacitor Grant 6,391,707 - Dirnecker , et al. May 21, 2	2002-05-21
Programmable neuron MOSFET on SOI App 20020047155 - Babcock, Jeffrey A. ; et al.	2002-04-25
Bipolar junction transistor App 20020041008 - Howard, Gregory E. ; et al.	2002-04-11
Advanced CMOS using super steep retrograde wells App 20020033511 - Babcock, Jeffrey A. ; et al.	2002-03-21
On chip heating for electrical trimming of polysilicon and polysilicon-silicon-germanium resistors and electrically programmable fuses for integrated circuits App 20020033519 - Babcock, Jeffrey A. ; et al.	2002-03-21
RF voltage controlled capacitor on thick-film SOI App 20020008268 - Babcock, Jeffrey A. ; et al.	2002-01-24