Aremallapur; Nagalinga Swamy Basayya
Patent Applications and Registrations
Patent applications and USPTO patent grants for Aremallapur; Nagalinga Swamy Basayya.The latest application filed is for "low power digital modes for duty-cycled integrated transceivers".
- Aremallapur; Nagalinga Swamy Basayya - Ranebennur IN
- AREMALLAPUR; Nagalinga Swamy Basayya - Bangalore IN
- Aremallapur; Nagalinga Swamy Basayya - Haveri IN
| Patent | Date |
|---|---|
| Phase coherent numerically controlled oscillator Grant 11,418,148 - Aremallapur , et al. August 16, 2 | 2022-08-16 |
| Offset Correction in High-Speed Serial Link Receivers App 20220182266 - Xavier; Ani ; et al. | 2022-06-09 |
| Low Power Digital Modes For Duty-cycled Integrated Transceivers App 20220182098 - RANGACHARI; Sundarrajan ; et al. | 2022-06-09 |
| Filtered Coarse Mixer Based Digital Down-Converter for RF Sampling ADCs App 20220173947 - BALAKRISHNAN; Jaiganesh ; et al. | 2022-06-02 |
| Bit Stream Transformation In Parallel Data Interfaces App 20220066975 - GANESAN; Aravind ; et al. | 2022-03-03 |
| Phase Coherent Numerically Controlled Oscillator App 20210075368 - AREMALLAPUR; Nagalinga Swamy Basayya ; et al. | 2021-03-11 |
| Phase coherent numerically controlled oscillator Grant 10,879,845 - Aremallapur , et al. December 29, 2 | 2020-12-29 |
| Frequency domain-based clock recovery Grant 10,840,919 - Subramanian , et al. November 17, 2 | 2020-11-17 |
| Phase Coherent Numerically Controlled Oscillator App 20200212844 - AREMALLAPUR; Nagalinga Swamy Basayya ; et al. | 2020-07-02 |
| Mixed signal circuit spur cancellation Grant 10,693,444 - Aremallapur , et al. | 2020-06-23 |
| Clock Pulse Generator App 20200177170 - KALE; Gautam Sanjay ; et al. | 2020-06-04 |
| Mixed Signal Circuit Spur Cancellation App 20200177168 - AREMALLAPUR; Nagalinga Swamy Basayya ; et al. | 2020-06-04 |
| Clock pulse generator Grant 10,651,836 - Kale , et al. | 2020-05-12 |
| Delay Modulated Clock Division App 20190273601 - BALAKRISHNAN; Jaiganesh ; et al. | 2019-09-05 |
| Delay modulated clock division Grant 10,341,082 - Balakrishnan , et al. | 2019-07-02 |
| Universal oscillator Grant 10,205,455 - Aremallapur Feb | 2019-02-12 |
| Universal Oscillator App 20160359490 - Aremallapur; Nagalinga Swamy Basayya | 2016-12-08 |
| Universal oscillator Grant 9,455,720 - Aremallapur September 27, 2 | 2016-09-27 |
| Universal Oscillator App 20160191061 - Aremallapur; Nagalinga Swamy Basayya | 2016-06-30 |
| Digital open loop duty cycle correction circuit Grant 9,344,066 - Aremallapur May 17, 2 | 2016-05-17 |
| Digital Open Loop Duty Cycle Correction Circuit App 20160094205 - Aremallapur; Nagalinga Swamy Basayya | 2016-03-31 |
| Delay circuits for simulating delays based on a single cycle of a clock signal Grant 8,786,347 - Chakraborty , et al. July 22, 2 | 2014-07-22 |
| Methods and circuits for enabling slew rate programmability and compensation of input/output circuits Grant 8,686,777 - Narang , et al. April 1, 2 | 2014-04-01 |
| Methods and delay circuits for generating a plurality of delays in delay lines Grant 8,542,049 - Bhaktavatson , et al. September 24, 2 | 2013-09-24 |
| Delay locked loop with delay programmability Grant 8,253,457 - Aremallapur August 28, 2 | 2012-08-28 |
| Delay Locked Loop With Delay Programmability App 20120119802 - Aremallapur; Nagalinga Swamy Basayya | 2012-05-17 |
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