U.S. patent number RE46,784 [Application Number 14/743,421] was granted by the patent office on 2018-04-10 for integrated circuit device having pads structure formed thereon and method for forming the same.
This patent grant is currently assigned to REALTEK SEMICONDUCTOR CORPORATION. The grantee listed for this patent is REALTEK SEMICONDUCTOR CORPORATION. Invention is credited to Ying-Hsi Lin.
United States Patent |
RE46,784 |
Lin |
April 10, 2018 |
Integrated circuit device having pads structure formed thereon and
method for forming the same
Abstract
The invention is to provide a structure of IC pad and its
forming method. The structure is arranged in an insulation layer
and is comprised of a lower electric-conduction layer, a compound
layer structure and a pad layer. The lower electric-conduction
layer is arranged at an appropriate position in the insulation
layer and is connected to an electric potential. The compound layer
structure is arranged on the insulation layer and is composed of at
least one electric-conduction layer and at least one
electric-conduction connecting layer, both are inter-overlapped to
each other. The pad layer is arranged on the compound layer
structure.
Inventors: |
Lin; Ying-Hsi (Hsinchu,
TW) |
Applicant: |
Name |
City |
State |
Country |
Type |
REALTEK SEMICONDUCTOR CORPORATION |
Hsinchu |
N/A |
TW |
|
|
Assignee: |
REALTEK SEMICONDUCTOR
CORPORATION (Hsinchu, TW)
|
Family
ID: |
1000002994346 |
Appl.
No.: |
14/743,421 |
Filed: |
June 18, 2015 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
Issue Date |
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Reissue of: |
10425973 |
Apr 30, 2003 |
6787928 |
Sep 7, 2004 |
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Foreign Application Priority Data
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Feb 26, 2003 [TW] |
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92104606 A |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L
24/03 (20130101); H01L 24/05 (20130101); H01L
24/05 (20130101); H01L 24/48 (20130101); H01L
24/03 (20130101); H01L 24/48 (20130101); H01L
2924/14 (20130101); H01L 2924/01005 (20130101); H01L
2924/14 (20130101); H01L 2924/01004 (20130101); H01L
2924/01006 (20130101); H01L 2924/30105 (20130101); H01L
2224/02166 (20130101); H01L 2224/48463 (20130101); H01L
2224/05095 (20130101); H01L 2924/01005 (20130101); H01L
2224/05558 (20130101); H01L 2224/85399 (20130101); H01L
2224/48463 (20130101); H01L 2924/00014 (20130101); H01L
2224/04042 (20130101); H01L 2224/05599 (20130101); H01L
2224/85399 (20130101); H01L 2224/05093 (20130101); H01L
2224/05599 (20130101); H01L 2224/04042 (20130101); H01L
2224/05095 (20130101); H01L 2224/05093 (20130101); H01L
2224/05558 (20130101); H01L 2924/01006 (20130101); H01L
2924/30105 (20130101); H01L 2924/01004 (20130101); H01L
2224/02166 (20130101); H01L 2924/00014 (20130101); H01L
2224/48463 (20130101); H01L 2224/48463 (20130101); H01L
2924/00014 (20130101); H01L 2924/00014 (20130101); H01L
2224/85399 (20130101); H01L 2224/85399 (20130101); H01L
2924/00014 (20130101); H01L 2924/00014 (20130101); H01L
2924/00014 (20130101); H01L 2924/00014 (20130101); H01L
2224/45099 (20130101); H01L 2224/45099 (20130101); H01L
2924/00014 (20130101); H01L 2924/00014 (20130101); H01L
2224/05599 (20130101); H01L 2224/05599 (20130101) |
Current International
Class: |
H01L
23/48 (20060101); H01L 23/485 (20060101); H01L
23/00 (20060101) |
Field of
Search: |
;257/779,782,784,786 |
References Cited
[Referenced By]
U.S. Patent Documents
Foreign Patent Documents
Primary Examiner: Torres Velazquez; Norca L
Attorney, Agent or Firm: Sughrue Mion, PLLC
Claims
What is claimed is:
1. An integrated circuit (IC) device having a pad structure formed
thereon, the IC device comprising: a) a substrate; b) an insulation
layer formed on the substrate; c) a .Iadd.plurality of
electric-conduction layers formed in the insulation layer,
including a .Iaddend.lower electric-conduction layer .[.formed in
the insulation layer.]..Iadd., each electric-conduction layer
having a thickness.Iaddend.; .Iadd.d) a plurality of connecting
layers, each connecting layer having a thickness, the connecting
layers interposed between the electric-conduction layers, the
plurality of connecting layers selectively coupling one or more of
the electric-conduction layers;.Iaddend. .[.d.]. .Iadd.e.Iaddend.)
a compound layer structure formed in the insulation layer; .[.e.].
.Iadd.f.Iaddend.) a first pad layer formed on the insulation layer
and coupled to the compound layer structure, wherein the first pad
layer and the compound layer structure are spaced apart .[.from the
lower electric-conduction.]. .Iadd.and substantially above from the
lower electric-conduction layer, wherein the compound layer
structure and the lower electric-conduction layer are spaced apart
by the thickness of at least one electric-conduction layer and the
thickness of at least one connecting .Iaddend.layer.Iadd., wherein
the first pad layer is designated for signal transmission.Iaddend.;
.[.and.]. .[.f.]. .Iadd.g.Iaddend.) a second pad layer formed on
the insulation layer and coupled to the lower electric-conduction
layer.Iadd., wherein the second pad layer is designated to be
coupled to a power source; h) at least one second connecting layer
for coupling the second pad layer to the lower electric-conduction
layer; and i) at least one second electric-conduction layer coupled
between the second pad layer and the lower electric-conduction
layer with the second connecting layer.Iaddend..
2. The IC device according to claim 1, wherein the compound layer
structure comprises a first electric-conduction layer and a first
connecting layer to couple the first electric-conduction layer to
the first pad layer.
3. The IC device according to claim 2, wherein the first connecting
layer comprises a plurality of via plugs.
4. The IC device according to claim 2, wherein the first
electric-conduction layer is shaped like a webbed railing.
5. The IC device according to claim 2, wherein the area of the
first electric-conduction layer is smaller than that of the first
pad layer.
6. The IC device according to claim 1, wherein the first pad layer
is shaped like a polygon.
7. The IC device according to claim 1, further comprising a
passivation layer formed on the insulation layer to cover a part of
the outer rim of at least one of the first and second pad
layers.
.[.8. The IC device according to claim 1, further comprising at
least one second connecting layer for coupling the second pad layer
to the lower electric-conduction layer..].
.[.9. The IC device according to claim 8, further comprising at
least one second electric-conduction layer coupled between the
second pad layer and the lower electric-conduction layer with the
second connecting layer..].
10. .[.The IC device according to claim 1,.]. .Iadd.An integrated
circuit (IC) device having a pad structure formed thereon, the IC
device comprising: a) a substrate; b) an insulation layer formed on
the substrate; c) a lower electric-conduction layer formed in the
insulation layer; d) a compound layer structure formed in the
insulation layer; e) a first pad layer formed on the insulation
layer, substantially formed above the lower electric-conduction
layer and coupled to the compound layer structure, wherein the
first pad layer and the compound layer structure are spaced apart
from the lower electric-conduction layer, wherein the first pad
layer is designated for signal transmission; f) a second pad layer
formed on the insulation layer and coupled to the lower
electric-conduction layer, wherein the second pad layer is
designated to be coupled to a power source; g) at least one second
connecting layer for coupling the second pad layer to the lower
electric-conduction layer; and h) at least one second
electric-conduction layer coupled between the second pad layer and
the lower electric-conduction layer with the second connecting
layer and disposed lower than the compound layer
structure;.Iaddend. wherein a noise from the substrate is kept away
from the first pad layer by the lower electric-conduction
layer.
11. An integrated circuit (IC) device having a pad structure formed
thereon, the IC device comprising: a) a substrate; b) an insulation
layer formed on the substrate; c) a lower electric-conduction layer
formed in the insulation layer; d) a compound layer structure
formed in the insulation layer; .[.and.]. e) a first pad layer
formed on the insulation layer and coupled to the compound layer
structure, wherein the first pad layer and the compound layer
structure are spaced apart from the lower electric-conduction
layer.Iadd., wherein the first pad layer is designated for signal
transmission; f) a second pad layer formed on the insulation layer
and coupled to the lower electric-conduction layer, wherein the
second pad layer is designated to be coupled to a power source; g)
at least one second connecting layer for coupling the second pad
layer to the lower electric-conduction layer; and h) at least one
second electric-conduction layer coupled between the second pad
layer and the lower electric-conduction layer with the second
connecting layer and disposed lower than the compound layer
structure.Iaddend..
12. The IC device according to claim 11, wherein the compound layer
structure comprises a first electric-conduction layer and a first
connecting layer to couple the first electric-conduction layer to
the first pad layer.
.[.13. The IC device according to claim 11, further comprising a
second pad layer formed on the insulation layer and coupled to the
lower electric-conduction layer..].
.[.14. The IC device according to claim 13, further comprising at
least one second connecting layer for coupling the second pad layer
to the lower electric-conduction layer; and at least one second
electric-conduction layer coupled between the second pad layer and
the lower electric-conduction layer with the second connecting
layer..].
15. The IC device according to claim .[.14.]. .Iadd.11.Iaddend.,
wherein, the area of the first electric-conduction layer is smaller
than that of the first pad layer.
16. The IC device according to claim 11, wherein the first pad
layer is shaped like a polygon.
17. The IC device according to claim 11, further comprising a
passivation layer formed on the insulation layer to cover a part of
the outer rim of at least one of the first and second pad
layers.
18. The IC device according to claim 11, wherein a noise from the
substrate is kept away from the first pad layer by the lower
electric-conduction layer.
19. A method for fabricating an IC device having a pad structure
formed thereon, the method comprising: a) providing a substrate; b)
forming an insulation layer formed on the substrate; c) forming a
lower electric-conduction layer formed in the insulation layer, at
least a part of the lower electric-conduction layer being covered
by the insulation layer; d) forming a compound layer structure
formed in the insulation layer, the compound layer structure being
spaced apart from and not connected to the lower
electric-conduction layer; .[.and.]. e) forming a first pad layer
formed on the insulation layer, .[.the first pad layer being.].
coupled to the compound layer, wherein .[.in the forming a first
pad layer step e).]. the first pad layer and the compound layer are
spaced apart from the lower electric-conduction layer.Iadd.; f)
forming a second pad layer formed on the insulation layer and
coupled to the lower electric-conduction layer, wherein the second
pad layer is designated to be coupled to a power source; g) forming
at least one second connecting layer for coupling the second pad
layer to the lower electric-conduction layer; and h) forming at
least one second electric-conduction layer coupled between the
second pad layer and the lower electric-conduction layer with the
second connecting layer.Iaddend..
20. The method according to claim 19, wherein a noise from the
substrate is kept away .[.form.]. .Iadd.from .Iaddend.the first pad
layer by the lower electric-conduction layer.
21. The method according to claim 19, wherein the forming a
compound layer structure step d) further comprises the steps of:
forming at least one first electric-conduction layer on the
insulation layer; and forming at least one first connecting layer
on the insulation layer, wherein the first connecting layer is to
couple the first electric-conduction layer to the first pad
layer.
22. The method according to claim 21, wherein the area of the first
electric-conduction layer is smaller than that of the first pad
layer.
.Iadd.23. The IC device according to claim 1, wherein the lower
electric-conduction layer is lowest in depth of the plurality of
electric-conduction layers..Iaddend.
.Iadd.24. The IC device according to claim 1, wherein the at least
one electric-conduction layer is not substantially disposed between
the first pad layer and an area of the lower electric-conduction
layer beneath the first pad layer..Iaddend.
.Iadd.25. The IC device according to claim 1, wherein the lower
electric-conduction layer is disposed such that an area of the
first pad layer substantially intersects the lower
electric-conduction layer when superimposed on the lower
electric-conduction layer..Iaddend.
.Iadd.26. The IC device according to claim 25, wherein the lower
electric-conduction layer is comprised of a plurality of sub-layers
disposed at the same depth..Iaddend.
.Iadd.27. The IC device according to claim 1, wherein the second
pad layer is designated to be coupled to a ground
potential..Iaddend.
.Iadd.28. The IC device according to claim 1, wherein the second
pad layer is designated to be coupled to a voltage
potential..Iaddend.
.Iadd.29. The IC device according to claim 1, wherein the first pad
layer is designated to be coupled to a high frequency
signal..Iaddend.
.Iadd.30. The IC device according to claim 10, wherein the compound
layer structure comprises a first electric-conduction layer and a
first electric-conduction connecting layer for coupling the first
electric-conduction layer to the first pad layer..Iaddend.
.Iadd.31. The IC device according to claim 30, further comprising:
a second electric-conduction layer, comprised of a first and second
sub-layers at the same depth, a second electric-conduction
connecting layer, comprised of first and second sub-layers at the
same depth, wherein the first sub-layer of the second
electric-conduction layer and the first sub-layer of the second
electric-conduction connecting layer couple the second pad layer
with a first portion of the lower electric-conduction
layer..Iaddend.
.Iadd.32. The IC device according to claim 31, further comprising:
a third electric-conduction layer, comprised of a first and second
sub-layers at the same depth, a third electric-conduction
connecting layer, comprised of a first and second sub-layers at the
same depth; wherein the second sub-layer of the third
electric-conduction layer and the second sub-layer of the third
electric-conduction connecting layer couple a third pad layer with
a second portion of the lower electric-conduction
layer..Iaddend.
.Iadd.33. The IC device according to claim 31, wherein the second
pad layer is designated to be coupled to a ground
potential..Iaddend.
.Iadd.34. The IC device according to claim 31, wherein the second
pad layer is designated to be coupled to a voltage
potential..Iaddend.
.Iadd.35. The IC device according to claim 31, wherein the first
pad layer is designated to be coupled to a high frequency
signal..Iaddend.
.Iadd.36. The IC device according to claim 29, wherein the compound
layer structure and the lower electric-conduction layer are spaced
apart by at least one electric-conduction layer and at least one
connecting layer..Iaddend.
.Iadd.37. The IC device according to claim 36, further comprising
multiple second electric-conduction layers, multiple second
electric-conduction connecting layers, multiple third
electric-conduction layers, multiple third electric-conduction
connecting layers; wherein the multiple second electric-conduction
layers and the multiple second electric-conduction connecting
layers are used to couple the second pad layer with one side of the
lower electric-conduction layer, and the multiple third
electric-conduction layers and the multiple third
electric-conduction connecting layers are used to couple the other
second pad layer with the other side of the lower
electric-conduction layer..Iaddend.
.Iadd.38. The IC device according to claim 37, wherein the multiple
second electric-conduction layers, multiple second
electric-conduction connecting layers, multiple third
electric-conduction layers, multiple third electric-conduction
connecting layers and the lower electric-conduction layer are
formed as a U-shaped structure..Iaddend.
.Iadd.39. The IC device according to claim 38, further comprising a
passivation layer formed on the insulation layer, wherein the
bonding zone of the passivation layer is smaller than the area of
first and second pad layers..Iaddend.
.Iadd.40. The IC device according to claim 39, wherein the second
pad layer and the other second pad layer are coupled to a power
source..Iaddend.
.Iadd.41. The IC device according to claim 10, wherein the noise
from the substrate is generated by an integrated
circuit..Iaddend.
.Iadd.42. The IC device according to claim 10, further comprising
multiple second electric-conduction layers, multiple second
electric-conduction connecting layers, multiple third
electric-conduction layers, multiple third electric-conduction
connecting layers; wherein the multiple second electric-conduction
layers and the multiple second electric-conduction connecting
layers are used to couple the second pad layer with one side of the
lower electric-conduction layer, and the multiple third
electric-conduction layers and the multiple third
electric-conduction connecting layers are used to couple the other
second pad layer with the other side of the lower
electric-conduction layer..Iaddend.
.Iadd.43. The IC device according to claim 42, wherein the multiple
second electric-conduction layers, multiple second
electric-conduction connecting layers, multiple third
electric-conduction layers, multiple third electric-conduction
connecting layers and the lower electric-conduction layer are
formed as a U-shaped structure..Iaddend.
.Iadd.44. The IC device according to claim 10, wherein first pad
layer is designated to be coupled to a high frequency signal and
the second pad layer is designated to be coupled to a voltage
potential or ground potential..Iaddend.
Description
.Iadd.This application and its continuation application, U.S.
patent application Ser. No. 15/253,539, filed Aug. 31, 2016, are
reissue applications of U.S. patent application Ser. No.
10/425,973, filed Apr. 30, 2003, now U.S. Pat. No. 6,787,928,
issued Sep. 7, 2004, which claims priority from Taiwanese Patent
Application No. 92104606, filed on Feb. 26, 2003, the disclosure of
which is incorporated herein by reference in its
entirety..Iaddend.
FIELD OF THE INVENTION
The invention relates to a structure of IC pad and its forming
method, in particular to a structure and method that are adapted to
form a pad of integrated circuit of high frequency and low noise;
not only the noise from the semiconductor substrate be separated
effectively and the value of equivalent electric capacitance of the
pad be lowered, but also the bonding adherence be further
enhanced.
BACKGROUND OF THE INVENTION
Recently, since the requirement of transceiver of low power and low
cost is steadily on the increase, so the technology of mainstream
IC competitively concentrates on how to realize further more
functions of radio frequency on one single chip. Except making
integrated circuit be able to arrange on the package substrate, the
external circuit connected by the external legs of package
substrate must be electrically connected to the integrated circuit.
So, when packaging the integrated circuit, the technology of pad
has become an important factor that influences the yield and
quality of a product. This pad adapted for providing electric
connection between the integrated circuit and the external circuit
is usually arranged in the metal zone around the IC die. When the
pad is formed, the metal connecting wire must contact with the pad
accurately and connect to the external legs of the IC packaging
substrate. Because of the limitation of the prior arts and the
characteristics of metal connecting wire and pad, the area of pad
is sometimes too large to occupy too much area of chip.
Furthermore, during high frequency, the performance of the
integrated circuit is influenced because the equivalent electric
capacitance is too large.
Additionally, because of the market growth of communication IC
recently, the operational frequency of integrated circuit is also
growing in indexing type. The low noise and low loss of high
frequency signal are always the pursuing goals for communication
IC.
In 1987, the U.S. Pat. No. 4,636,832 "Semiconductor device with an
improved bonding section" proposed a design method of the pad of
integrated circuit. Please refer to FIG. 1, which is a
cross-sectional diagram of the IC device disclosed in the U.S. Pat.
No. 4,636,832. The characteristic of this prior art is that the
semiconductor element 10 is arranged below the pad 15. Although it
may reduce the area of layout, this kind of pad can not be adapted
to high frequency circuit with low noise because the noise coming
from the semiconductor substrate 20 will directly influence the
signal of high frequency when it passes through the pad.
To overcome the tensile and tension of bonding, the U.S. Pat. No.
5,248,903 "Composite pads for semiconductor devices" proposed a
kind of pad. Please refer to FIG. 2, which is the cross-sectional
diagram of the IC device disclosed in the U.S. Pat. No. 5,248,903.
Wherein, the pad 30 has at least two layers of electric-conduction
layer 30a and 30c and a connection layer 30b. But, this kind of pad
is not adapted for the signals of high frequency and low noise
because the noise of semiconductor substrate 35 will directly
influence the quality of signal.
The U.S. Pat. No. 5,502,337 "Semiconductor device structure
including multiple interconnection layers with interlayer
insulating films" proposed a different designing method for pad.
Please refer to FIG. 3, which is a cross-sectional diagram for the
IC device disclosed in the U.S. Pat. No. 5,502,337, which arranges
the connection layer 40a in the pad 40 around the bonding zone 45.
When the integrated circuit is manufactured, a bonding zone of arc
shape will be formed on the pad 40 to thereby enhance the bonding
adherence. However, the technology of current integrated circuit
has stepped into the levels of sub micrometer or deep sub
micrometer, and CMP (Chemical-Mechanical Polish) is already a
standard procedure for current semiconductor process. So, this kind
of prior art no longer generates original effectiveness in current
semiconductor process, besides this technique has the same drawback
as that of previous techniques; i.e., it can not separate the noise
coming from the semiconductor substrate 50.
From above discussion, we know that the prior arts described there
are unable to propose an effective solution that aims for the high
frequency, low noise and bonding adherence. Therefore, the emphasis
of the invention is to provide a pad structure adapted for a
integrated circuit of high frequency and low noise to lower down
the equivalent electric capacitance and enhance the bonding
adherence, such that it can prevent the entire pad from being drawn
out of the semiconductor chip by the tension generated in the
bonding procedure.
SUMMARY OF THE INVENTION
The main objective of the present invention is to provide a
structure of IC pad and its forming method, which are adapted for
the structure of the pad of an integrated circuit of high frequency
and low noise, such that the effective area of the pad may be
reduced effectively to thereby reduce its value of equivalent
electric capacitance.
The second objective of the present invention is to provide a
structure of IC pad and its forming method effectively separate the
noise coming from the semiconductor substrate.
The further objective of the present invention is to provide a
structure of IC pad and its forming method effectively enhance the
bonding adherence, such that it prevent the entire pad from being
drawn out of the semiconductor chip by the tension generated in the
bonding procedure.
To achieve above objectives, the invention provides an IC pad
structure arranged in an insulation layer comprises a lower
electric-conduction layer, a compound layer structure and a pad
layer.
The lower electric-conduction layer is arranged in the insulation
layer and is connected to an electric potential.
The compound layer structure arranged on the insulation layer
comprises at least one electric-conduction layer and at least one
electric-conduction connecting layer, each of the
electric-conduction layer are connected to each other.
The pad layer is arranged on the compound layer structure.
To achieve above objectives, the invention further presents method
for forming IC pad structure, comprising the following steps
of:
Step (a): providing a substrate arranged with an insulation
layer.
Step (b): forming a lower electric-conduction layer which prepared
connect to an electric potential.
Step (c): forming a compound layer structure composed by
inter-overlapping or connect at least one electric-conduction layer
and at least one electric-conduction connecting layer on the
insulation layer.
Step (d): forming a pad layer on the compound layer structure, of
which area is larger than that of the electric-conduction layer of
the compound layer structure.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a cross-sectional diagram for the IC device disclosed in
the U.S. Pat. No. 4,636,832.
FIG. 2 is a cross-sectional diagram for the IC device disclosed in
the U.S. Pat. No. 5,248,903.
FIG. 3 is a cross-sectional diagram for the IC device disclosed in
the U.S. Pat. No. 5,502,337.
FIG. 4 is an upper side view for the structural illustration of a
preferable embodiment of the IC pad according to the invention.
FIG. 5 is a cross-sectional view along the A-A line cutting through
FIG. 4 illustrating the preferable embodiment of the IC pad
according to the invention.
FIG. 6 is a flowchart illustrating the preferable embodiment of the
method forming the IC pad according to the invention.
DETAILED DESCRIPTION OF THE INVENTION
For your esteemed member of reviewing committee to further
recognize and understand the characteristics, objectives, and
functions of the present invention, a detailed description together
with corresponding drawings are presented thereinafter.
The invention discloses a structure of IC pad and its forming
method. Its embodiments are described according to referential
drawings, in which similar referential numbers represent similar
elements.
Please refer to FIG. 4 and FIG. 5, which are structural
illustrations for the preferable embodiments of the IC pad
according to the present invention. The IC pad structure includes a
lower electric-conduction layer 300, a compound layer structure
100, and a first pad layer 600. The lower electric-conduction layer
300 formed at an appropriate position in the insulation layer 500
is coupled with plural electric-conduction layers 202 and plural
electric-conduction connecting layers 201, shown in FIG. 5, such
that the lower electric-conduction layer 300 may a voltage signal
from a second pad layer 700 formed on the upper surface exposing on
the insulation layer 500 through provide electric-conduction layers
202 and electric-conduction connecting layers 201 shown in FIG. 5,
which further provides a connection to a device providing the
voltage signal (not shown in the drawings). The second pad layer
700 further forms a bonding zone with a chip passivation layer 205
and 105. The noise transferred from the substrate .[.40.].
.Iadd.400 .Iaddend.will be kept away by the lower
electric-conduction layer 300 which may be connected to a power
source or voltage signal by the second pad layer 700.
The compound layer structure 100 is arranged on the insulation
layer 500 and is composed of at least one electric-conduction layer
102 and at least one electric-conduction connecting layer 101, both
which are inter-overlapped to each other. The pad layer 600 is
arranged on the compound layer structure 100 and is adjacent to the
top face side of the insulation layer 500. In the preferable
embodiments according to the invention and in order to lower down
the value of the effective capacitance of the entire pad, the pad
layer 600 is realized by the structuring method of polygon shape
and the area of the electric-conduction layer 102 is designed to be
smaller than that of the pad layer 600, such that the value of the
equivalent electric capacitance to the lower electric-conduction
layer 300 may be further effectively lowered down. The
electric-conduction layer 102 may be realized by the methods of
railing structure or honeycomb structure that may reduce the area
of electric-conduction layer 102. The electric-conduction
connecting layer 101 further includes plural vias and plural via
plugs. The structure of this electric-conduction connecting layer
101 may be modified and implemented by those who are skilled in
such art according to above disclosure, but it still possesses the
merits of the invention and is also within the spirit and scope of
the invention, so repetitious description is not presented
herein.
In the preferable embodiments according to the invention, the IC
pad structure further includes a passivation layer 105, which is
arranged on the insulation layer 500 and is partially connected to
the pad layer 600. From above design, the compound layer structure
100 is signally connected and structured to the pad layer 600, and
a steady bonding zone is thereby formed, such that it may enhance
the boding tension and effectively raise the bonding adherence.
Therefore, the tension generated during the bonding procedure to
draw the entire structure of the IC pad out of the semiconductor
chip may be prevented.
In order to further recognize and understand the characteristics,
objectives and functions of the present invention, please refer to
FIG. 6, which is a flowchart illustrating the preferable embodiment
of the method forming the IC pad according to the invention,
wherein the numbers 91, 92, 93, 94 and 95 shown in the drawing
respectively illustrate the steps from (a) to (e) of the method
forming the IC pad according to the invention.
Step (a): providing a substrate that is arranged with an insulation
layer thereon.
Step (b): forming a lower electric-conduction layer at an
appropriate position in the insulation layer; the lower
electric-conduction layer is composed of plural electric-conduction
layers and plural electric-conduction connecting layers. In this
embodiment, each of the electric-conduction layer is
interlaced-connected to the corresponding electric-conduction
connecting layers, as shown in FIG. 5, such that a signal
connection may be provided to a bond-pad electric-connection layer,
which further forms a bonding zone with a passivation layer, such
that the pad layer may be connected to a potential of cleaner power
source or electric potential.
Step (c): a compound layer structure formed on the insulation layer
is composed of at least one electric-conduction layer and at least
one electric-conduction connecting layer, each of the
electric-conduction layer is interlaced-connected to the
corresponding electric-conduction connecting layers, as shown in
FIG. 5, and the area of the electric-conduction layer can be
reduced by the methods of railing structure or honeycomb structure,
and the electric-conduction connecting layer further includes the
structure of plural vias and plural via plugs.
Step (d): forming a pad layer on the compound layer structure,
wherein the area of the former is larger than that of the
electric-conduction layer of the latter, and the pad layer is
structured as a polygon shape.
Step (e): forming a passivation layer on the insulation layer, such
that the pad layer may form a bonding zone with the passivation
layer.
Accordingly, the structure of an IC pad and its forming method
according to the invention may indeed reduce the value of
equivalent electric capacitance of the entire pad, separate the
noise coming from the semiconductor substrate, and increase the
bonding adherence, so this kind of designing method may be adapted
to integrated circuit of high frequency and fulfill the requirement
of high frequency and low noise.
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