U.S. patent number RE37,505 [Application Number 08/628,287] was granted by the patent office on 2002-01-15 for stacked capacitor construction.
This patent grant is currently assigned to Micron Technology, Inc.. Invention is credited to Guy Blalock, Phillip G. Wald.
United States Patent |
RE37,505 |
Blalock , et al. |
January 15, 2002 |
Stacked capacitor construction
Abstract
A method of forming a capacitor on a semiconductor wafer
includes: a) in a dry etching reactor, selectively anisotropically
dry etching a capacitor contact opening having a minimum selected
open dimension into an insulating dielectric layer utilizing
selected gas flow rates of a reactive gas component and an inert
gas bombarding component, the flow rate of the bombarding component
significantly exceeding the flow rate of the reactive component to
effectively produce a capacitor contact opening having grooved
striated sidewalls and thereby defining female capacitor contact
opening striations; b) providing a layer of an electrically
conductive storage node material within the striated capacitor
contact opening; c) removing at least a portion of the conductive
material layer to define an isolated capacitor storage node within
the insulating dielectric having striated sidewalls; d) etching the
insulating dielectric layer selectively relative to the conductive
material sufficiently to expose at least a portion of the external
male striated conductive material sidewalls; and e) providing
conformal layers of capacitor dielectric and capacitor cell
material atop the etched conductive material and over its exposed
striated sidewalls. The invention also includes a stacked capacitor
construction having an electrically conductive storage node with
upwardly rising external sidewalls. Such sidewalls have
longitudinally extending striations to maximize surface area and
corresponding capacitance in a resulting construction.
Inventors: |
Blalock; Guy (Boise, ID),
Wald; Phillip G. (Boise, ID) |
Assignee: |
Micron Technology, Inc. (Boise,
ID)
|
Family
ID: |
25318683 |
Appl.
No.: |
08/628,287 |
Filed: |
April 5, 1996 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
Issue Date |
|
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854435 |
Mar 18, 1992 |
5238862 |
|
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Reissue of: |
058778 |
Apr 28, 1993 |
05300801 |
Apr 5, 1994 |
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Current U.S.
Class: |
257/309;
257/303 |
Current CPC
Class: |
H01L
27/10808 (20130101); H01L 27/10852 (20130101); H01L
28/84 (20130101); H01L 28/91 (20130101); Y10S
438/964 (20130101) |
Current International
Class: |
H01L
21/70 (20060101); H01L 21/02 (20060101); H01L
21/8242 (20060101); H01L 27/108 (20060101); H01L
029/78 () |
Field of
Search: |
;257/303,306,309 |
References Cited
[Referenced By]
U.S. Patent Documents
Foreign Patent Documents
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2-166760 |
|
Jun 1990 |
|
JP |
|
2-203557 |
|
Aug 1990 |
|
JP |
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3-266460 |
|
Nov 1991 |
|
JP |
|
Other References
Ema et al "3-Dimensional Stacked Capacitor Cell for 16M and 64M
DRAMs" IEDM Tech. Digest, 1988, pp. 592-595.* .
S. Inoue et al "A Spread Stacked Capacitor (SSC) Cell for 64 MBit
DRAMs" IEDM Tech. Digest, 1989, pp. 31-34..
|
Primary Examiner: Munson; Gene M.
Attorney, Agent or Firm: TraskBritt
Parent Case Text
RELATED PATENT DATA
This patent resulted from a divisional application of U.S. patent
application Ser. No. 07/854,435, filed Mar. 18, 1992, which is now
U.S. Pat. No. 5,238,862.
Claims
We claim:
1. A stacked capacitor construction formed within a semiconductor
substrate comprising:
an electrically conductive storage node, the storage node having
upwardly rising external sidewalls, the upwardly rising external
sidewalls having longitudinally extending striations to maximize
surface area and corresponding capacitance;
a striated cell dielectric layer provided over the storage node and
its associated longitudinally extending striations; and
an electrically conductive striated cell layer provided over the
striated cell dielectric layer.
2. The stacked capacitor construction of claim 1 wherein the
electrically conductive material of the storage node comprises
conductively doped polysilicon.
3. The stacked capacitor construction of claim 1 wherein the
electrically conductive material of the cell layer comprises
conductively doped polysilicon.
4. The stacked capacitor construction of claim 1 wherein the
electrically conductive material of the storage node comprises
conductively doped polysilicon, and the electrically conductive
material of the cell layer comprises conductively doped
polysilicon..Iadd.
5. A stacked capacitor construction formed within a semiconductor
substrate comprising:
a layer of insulating dielectric material located on the
semiconductor substrate having at least one contact opening
therein, the contact opening having a striated sidewall;
an electrically conductive storage node formed within the at least
one contact opening the storage node having external sidewalls, the
external sidewalls each having a surface thereon to maximize
surface area and corresponding capacitance, the surfaces of the
external sidewalls including striations;
a dielectric layer provided over the storage node and its
associated external sidewalls, the dielectric layer including
striations; and
an electrically conductive cell layer provided over the cell
dielectric layer, the electrically conductive cell layer including
striations. .Iaddend..Iadd.
6. The stacked capacitor construction of claim 5 wherein the
electrically conductive material of the storage node comprises
conductively doped polysilicon. .Iaddend..Iadd.
7. The stacked capacitor construction of claim 5 wherein the
electrically conductive material of the cell layer comprises
conductively doped polysilicon. .Iaddend..Iadd.
8. The stacked capacitor construction of claim 5 wherein the
electrically conductive material of the storage node comprises
conductively doped polysilicon, and the electrically conductive
material of the cell layer comprises conductively doped
polysilicon. .Iaddend..Iadd.
9. A stacked capacitor construction formed within a semiconductor
substrate comprising:
a layer of insulating dielectric material located on the
semiconductor substrate having at least one contact opening
therein, the contact opening having a striated sidewall;
an electrically conductive storage node formed within the at least
one contact opening, the storage node having rising external
sidewalls, the rising external sidewalls each having a surface
thereon to maximize surface area and corresponding capacitance, the
surfaces of the rising external sidewalls including striations;
a dielectric layer provided over the storage node and its
associated rising external sidewalls, the dielectric layer
including striations; and
an electrically conductive cell layer provided over the cell
dielectric layer, the electrically conductive cell layer including
striations. .Iaddend..Iadd.
10. The stacked capacitor construction of claim 9 wherein the
electrically conductive material of the storage node comprises
conductively doped polysilicon. .Iaddend..Iadd.
11. The stacked capacitor construction of claim 9 wherein the
electrically conductive material of the cell layer comprises
conductively doped polysilicon. .Iaddend..Iadd.
12. The stacked capacitor construction of claim 9 wherein the
electrically conductive material of the storage node comprises
conductively doped polysilicon, and the electrically conductive
material of the cell layer comprises conductively doped
polysilicon. .Iaddend..Iadd.
13. A stacked capacitor construction formed within a semiconductor
substrate comprising:
a layer of insulating dielectric material located on the
semiconductor substrate having at least one contact opening
therein, the contact opening having a striated sidewall;
an electrically conductive storage node, the storage node having
upwardly rising external sidewalls, the upwardly rising external
sidewalls each having a surface thereon to maximize surface area
and corresponding capacitance, the surfaces of the external
sidewalls including striations;
a dielectric layer provided over the storage node and its
associated upwardly rising sidewalls, the cell dielectric layer
including striations; and
an electrically conductive cell layer provided over the cell
dielectric layer, the electrically conductive cell layer including
striations. .Iaddend..Iadd.
14. The stacked capacitor construction of claim 13 wherein the
electrically conductive material of the storage node comprises
conductively doped polysilicon. .Iaddend..Iadd.
15. The stacked capacitor construction of claim 13 wherein the
electrically conductive material of the cell layer comprises
conductively doped polysilicon. .Iaddend..Iadd.
16. The stacked capacitor construction of claim 13 wherein the
electrically conductive material of the storage node comprises
conductively doped polysilicon and the electrically conductive
material of the cell layer comprises conductively doped
polysilicon. .Iaddend..Iadd.
17. A stacked capacitor construction formed within a semiconductor
substrate comprising:
a layer of insulating dielectric material located on the
semiconductor substrate having at least one contact opening
therein, the contact opening having a pretexturized striated
sidewall;
an electrically conductive storage node, the storage node having
external sidewalls, the external sidewalls each having a surface
thereon to maximize surface area and corresponding capacitance, the
surfaces of the external sidewalls including striated
sidewalls;
a dielectric layer provided over the storage node and its
associated external sidewalls, the dielectric layer including
striations; and
an electrically conductive layer provided over the dielectric
layer, the electrically conductive layer including striations.
.Iaddend..Iadd.
18. The stacked capacitor construction of claim 17 wherein the
electrically conductive material of the storage node comprises
conductively doped polysilicon. .Iaddend..Iadd.
19. The stacked capacitor construction of claim 17 wherein the
electrically conductive material of the cell layer comprises
conductively doped polysilicon. .Iaddend..Iadd.
20. The stacked capacitor construction of claim 17 wherein the
electrically conductive material of the storage node comprises
conductively doped polysilicon, and the electrically conductive
material of the cell layer comprises conductively doped
polysilicon. .Iaddend..Iadd.
21. A stacked capacitor construction formed within a semiconductor
substrate comprising:
a layer of insulating dielectric material located on the
semiconductor substrate having at least one contact opening
therein, the contact opening having a pretexturized striated
sidewall;
an electrically conductive storage node, the storage node having
rising external sidewalls, the rising external sidewalls each
having a surface thereon to maximize surface area and corresponding
capacitance, the surfaces of the external sidewalls including
striations;
a dielectric layer provided over the storage node and its
associated rising external sidewalls, the dielectric layer
including striations; and
an electrically conductive layer provided over the dielectric
layer, the electrically conductive layer including striations.
.Iaddend..Iadd.
22. The stacked capacitor construction of claim 21 wherein the
electrically conductive material of the storage node comprises
conductively doped polysilicon. .Iaddend..Iadd.
23. The stacked capacitor construction of claim 21 wherein the
electrically conductive material of the cell layer comprises
conductively doped polysilicon. .Iaddend..Iadd.
24. The stacked capacitor construction of claim 21 wherein the
electrically conductive material of the storage node comprises
conductively doped polysilicon, and the electrically conductive
material of the cell layer comprises conductively doped
polysilicon. .Iaddend..Iadd.
25. A stacked capacitor construction formed within a semiconductor
substrate comprising:
a layer of insulating dielectric material located on the
semiconductor substrate having at least one contact opening
therein, the contact opening having a pretexturized striated
sidewall;
an electrically conductive storage node, the storage node having
upwardly rising external sidewalls, the upwardly rising external
sidewalls each having a surface thereon to maximize surface area
and corresponding capacitance, the surfaces of the external
sidewalls including striations;
a dielectric layer provided over the storage node and its
associated upwardly rising external sidewalls, the dielectric layer
including striations; and
an electrically conductive layer provided over the dielectric
layer, the electrically conductive layer including striations.
.Iaddend..Iadd.
26. The stacked capacitor construction of claim 25 wherein the
electrically conductive material of the storage node comprises
conductively doped polysilicon. .Iaddend..Iadd.
27. The stacked capacitor construction of claim 25 wherein the
electrically conductive material of the cell layer comprises
conductively doped polysilicon. .Iaddend..Iadd.
28. The stacked capacitor construction of claim 25 wherein the
electrically conductive material of the storage node comprises
conductively doped polysilicon, and the electrically conductive
material of the cell layer comprises conductively doped
polysilicon. .Iaddend..Iadd.
29. A stacked capacitor construction formed within a semiconductor
substrate comprising:
a layer of insulating dielectric material located on the
semiconductor substrate having at least one contact opening
therein, the contact opening having a grooved striated
sidewall;
an electrically conductive storage node, the storage node having
external sidewalls, the external sidewalls each having a surface
thereon to maximize surface area and corresponding capacitance, the
surfaces of the external sidewalls including striations;
a dielectric layer provided over the storage node and its
associated external sidewalls, the dielectric layer including
striations; and
an electrically conductive layer provided over the dielectric
layer, the electrically conductive layer including striations.
.Iaddend..Iadd.
30. The stacked capacitor construction of claim 29 wherein the
electrically conductive material of the storage node comprises
conductively doped polysilicon. .Iaddend..Iadd.
31. The stacked capacitor construction of claim 29 wherein the
electrically conductive material of the cell layer comprises
conductively doped polysilicon. .Iaddend..Iadd.
32. The stacked capacitor construction of claim 29 wherein the
electrically conductive material of the storage node comprises
conductively doped polysilicon, and the electrically conductive
material of the cell layer comprises conductively doped
polysilicon. .Iaddend..Iadd.
33. A stacked capacitor construction formed within a semiconductor
substrate comprising:
a layer of insulating dielectric material located on the
semiconductor substrate having at least one contact opening
therein, the contact opening having a grooved striated
sidewall;
an electrically conductive storage node, the storage node having
rising external sidewalls, the rising external sidewalls each
having a surface thereon including to maximize surface area and
corresponding capacitance, the surfaces of the external sidewalls
including striations;
a dielectric layer provided over the storage node and its
associated rising external sidewalls, the dielectric layer
including striations; and
an electrically conductive layer provided over the dielectric
layer, the electrically conductive layer including striations.
.Iaddend..Iadd.
34. The stacked capacitor construction of claim 33 wherein the
electrically conductive material of the storage node comprises
conductively doped polysilicon. .Iaddend..Iadd.
35. The stacked capacitor construction of claim 33 wherein the
electrically conductive material of the cell layer comprises
conductively doped polysilicon. .Iaddend..Iadd.
36. The stacked capacitor construction of claim 33 wherein the
electrically conductive material of the storage node comprises
conductively doped polysilicon, and the electrically conductive
material of the cell layer comprises conductively doped
polysilicon. .Iaddend..Iadd.
37. A stacked capacitor construction formed within a semiconductor
substrate comprising:
a layer of insulating dielectric material located on the
semiconductor substrate having at least one contact opening
therein, the contact opening having a grooved striated
sidewall;
an electrically conductive storage node, the storage node having
upwardly rising external sidewalls, the upwardly rising external
sidewalls each having a surface thereon to maximize surface area
and corresponding capacitance, the surfaces of the upwardly rising
external sidewalls including striations;
a dielectric layer provided over the storage node and its
associated upwardly rising sidewalls, the dielectric layer
including striations; and
an electrically conductive layer provided over the dielectric
layer, the electrically conductive layer including striations.
.Iaddend..Iadd.
38. The stacked capacitor construction of claim 37 wherein the
electrically conductive material of the storage node comprises
conductively doped polysilicon. .Iaddend..Iadd.
39. The stacked capacitor construction of claim 37 wherein the
electrically conductive material of the cell layer comprises
conductively doped polysilicon. .Iaddend..Iadd.
40. The stacked capacitor construction of claim 37 wherein the
electrically conductive material of the storage node comprises
conductively doped polysilicon, and the electrically conductive
material of the cell layer comprises conductively doped
polysilicon. .Iaddend..Iadd.
41. A stacked capacitor construction formed within a semiconductor
substrate comprising:
a layer of insulating dielectric material located on the
semiconductor substrate having at least one contact opening
therein, the contact opening having striations in the sidewall;
an electrically conductive storage node, the storage node having
external sidewalls, the external sidewalls each having a surface
thereon to maximize surface area and corresponding capacitance, the
surfaces of the external sidewalls including complementary
striations therein to the striations in the sidewall of the at
least one contact opening of the layer of insulating dielectric
material;
a dielectric layer provided over the storage node and its
associated external sidewalls; and
an electrically conductive layer provided over the dielectric
layer, the electrically conductive layer including striations.
.Iaddend..Iadd.
42. The stacked capacitor construction of claim 41 wherein the
electrically conductive material of the storage node comprises
conductively doped polysilicon. .Iaddend..Iadd.
43. The stacked capacitor construction of claim 41 wherein the
electrically conductive material of the cell layer comprises
conductively doped polysilicon. .Iaddend..Iadd.
44. The stacked capacitor construction of claim 41 wherein the
electrically conductive material of the storage node comprises
conductively doped polysilicon and the electrically conductive
material of the cell layer comprises conductively doped
polysilicon. .Iaddend..Iadd.
45. A stacked capacitor construction formed within a semiconductor
substrate comprising:
a layer of insulating dielectric material located on the
semiconductor substrate having at least one contact opening
therein, the contact opening having striations in the sidewall;
an electrically conductive storage node, the storage node having
rising external sidewalls, the rising external sidewalls each
having a surface thereon to maximize surface area and corresponding
capacitance, the surfaces of the rising external sidewalls
including complementary striations therein to the striations in the
sidewall of the at least one contact opening of the layer of
insulating dielectric material;
a dielectric layer provided over the storage node and its
associated rising external surfaces, the dielectric layer including
striations; and
an electrically conductive layer provided over the dielectric
layer, the electrically conductive layer including striations.
.Iaddend..Iadd.
46. The stacked capacitor construction of claim 45 wherein the
electrically conductive material of the storage node comprises
conductively doped polysilicon. .Iaddend..Iadd.
47. The stacked capacitor construction of claim 45 wherein the
electrically conductive material of the cell layer comprises
conductively doped polysilicon. .Iaddend..Iadd.
48. The stacked capacitor construction of claim 45 wherein the
electrically conductive material of the storage node comprises
conductively doped polysilicon, and the electrically conductive
material of the cell layer comprises conductively doped
polysilicon. .Iaddend..Iadd.
49. A stacked capacitor construction formed within a semiconductor
substrate comprising:
a layer of insulating dielectric material located on the
semiconductor substrate having at least one contact opening
therein, the contact opening having striations in the sidewall;
an electrically conductive storage node, the storage node having
upwardly rising external sidewalls, the upwardly rising external
sidewalls each having a surface thereon to maximize surface area
and corresponding capacitance, the surfaces of the upwardly rising
external sidewalls including complementary striations therein to
the striations in the sidewall of the at least one contact opening
of the layer of insulating dielectric material;
a dielectric layer provided over the storage node and its
associated upwardly rising external surfaces, the dielectric layer
including striations; and
an electrically conductive layer provided over the dielectric
layer, the electrically conductive layer including striations.
.Iaddend..Iadd.
50. The stacked capacitor construction of claim 49 wherein the
electrically conductive material of the storage node comprises
conductively doped polysilicon. .Iaddend..Iadd.
51. The stacked capacitor construction of claim 49 wherein the
electrically conductive material of the cell layer comprises
conductively doped polysilicon. .Iaddend..Iadd.
52. The stacked capacitor construction of claim 49 wherein the
electrically conductive material of the storage node comprises
conductively doped polysilicon, and the electrically conductive
material of the cell layer comprises conductively doped
polysilicon. .Iaddend..Iadd.
53. A stacked capacitor construction formed within a semiconductor
substrate comprising:
a layer of insulating dielectric material located on the
semiconductor substrate having at least one contact opening
therein, the contact opening having striations in the sidewall;
an electrically conductive storage node, the storage node having
external sidewalls, the external sidewalls each having a surface
thereon to maximize surface area and corresponding capacitance, the
surfaces of the external side walls including striations;
a dielectric layer provided over the storage node and its
associated external sidewalls, the dielectric layer including
striations; and
an electrically conductive layer provided over the dielectric
layer, the surface of the electrically conductive layer including
partial striations. .Iaddend..Iadd.
54. The stacked capacitor construction of claim 53 wherein the
electrically conductive material of the storage node comprises
conductively doped polysilicon. .Iaddend..Iadd.
55. The stacked capacitor construction of claim 53 wherein the
electrically conductive material of the cell layer comprises
conductively doped polysilicon. .Iaddend..Iadd.
56. The stacked capacitor construction of claim 53 wherein the
electrically conductive material of the storage node comprises
conductively doped polysilicon, and the electrically conductive
material of the cell layer comprises conductively doped
polysilicon. .Iaddend..Iadd.
57. A stacked capacitor construction formed within a semiconductor
substrate comprising:
a layer of insulating dielectric material located on the
semiconductor substrate having at least one contact opening
therein, the contact opening having striations in the sidewall;
an electrically conductive storage node, the storage node having
raised external sidewalls, the raised external sidewalls each
having a surface thereon to maximize surface area and corresponding
capacitance, the surfaces of the raised external sidewalls
including striations;
a dielectric layer provided over the storage node and its
associated raised external sidewalls, the dielectric layer
including striations; and
an electrically conductive layer provided over the dielectric
layer, the surface of the electrically conductive layer including
partial striations. .Iaddend..Iadd.
58. The stacked capacitor construction of claim 57 wherein the
electrically conductive material of the storage node comprises
conductively doped polysilicon. .Iaddend..Iadd.
59. The stacked capacitor construction of claim 57 wherein the
electrically conductive material of the cell layer comprises
conductively doped polysilicon. .Iaddend..Iadd.
60. The stacked capacitor construction of claim 57 wherein the
electrically conductive material of the storage node comprises
conductively doped polysilicon, and the electrically conductive
material of the cell layer comprises conductively doped
polysilicon. .Iaddend..Iadd.
61. A stacked capacitor construction formed within a semiconductor
substrate comprising:
a layer of insulating dielectric material located on the
semiconductor substrate having at least one contact opening
therein, the contact opening having striations in the sidewall;
an electrically conductive storage node, the storage node having
upwardly raised external sidewalls, the upwardly raised external
sidewalls each having a surface thereon to maximize surface area
and corresponding capacitance, the surfaces of the upwardly raised
external sidewalls including striations;
a dielectric layer provided over the storage node and its
associated upwardly raising external sidewalls, the dielectric
layer including striations; and
an electrically conductive layer provided over the dielectric
layer, the surface of the electrically conductive layer including
partial striations. .Iaddend..Iadd.
62. The stacked capacitor construction of claim 61 wherein the
electrically conductive material of the storage node comprises
conductively doped polysilicon. .Iaddend..Iadd.
63. The stacked capacitor construction of claim 61 wherein the
electrically conductive material of the cell layer comprises
conductively doped polysilicon. .Iaddend..Iadd.
64. The stacked capacitor construction of claim 61 wherein the
electrically conductive material of the storage node comprises
conductively doped polysilicon, and the electrically conductive
material of the cell layer comprises conductively doped
polysilicon. .Iaddend..Iadd.
65. A stacked capacitor construction formed within a semiconductor
substrate comprising:
a layer of insulating dielectric material located on the
semiconductor substrate having at least one contact opening
therein;
an electrically conductive storage node formed within the at least
one contact opening, the storage node having external sidewalls,
the external sidewalls each having a surface thereon to maximize
surface area and corresponding capacitance, the surfaces of the
external sidewalls including striations;
a dielectric layer provided over the storage node and its
associated external sidewalls, the dielectric layer including
striations; and
an electrically conductive cell layer provided over the cell
dielectric layer, the electrically conductive cell layer including
striations. .Iaddend..Iadd.
66. A stacked capacitor construction formed within a semiconductor
substrate comprising:
a layer of insulating dielectric material located on the
semiconductor substrate having at least one contact opening
therein;
an electrically conductive storage node, the storage node having
external sidewalls, the external sidewalls each having a texturized
surface thereon to maximize surface area and corresponding
capacitance, the surfaces of the external side walls including
striations;
a dielectric layer provided over the storage node and its
associated external sidewalls, the dielectric layer including
striations; and
an electrically conductive layer provided over the dielectric
layer, the surface of the electrically conductive layer including
partial striations. .Iaddend..Iadd.
67. A stacked capacitor construction formed within a semiconductor
substrate comprising:
a layer of insulating dielectric material located on the
semiconductor substrate having at least one contact opening
therein;
an electrically conductive storage node, the storage node having
external sidewalls, the external sidewalls each having a surface
thereon to maximize surface area and corresponding capacitance, the
surfaces of the external side walls including striations;
a dielectric layer provided over the storage node and its
associated external sidewalls, the dielectric layer including
striations; and
an electrically conductive layer provided over the dielectric
layer, a portion of the surface of the electrically conductive
layer including partial striations. .Iaddend..Iadd.
68. A stacked capacitor construction formed within a semiconductor
substrate comprising:
an electrically conductive storage node, the storage node having
external sidewalls, the external sidewalls each having a surface
thereon to maximize surface area and corresponding capacitance, the
surfaces of the external sidewalls including striations;
a dielectric layer provided over the storage node and its
associated external sidewalls, the dielectric layer including
striations; and
an electrically conductive layer provided over the dielectric
layer, the surface of the electrically conductive layer including
partial striations. .Iaddend..Iadd.
69. The stacked capacitor construction of claim 68 wherein the
electrically conductive storage node comprises conductively doped
polysilicon. .Iaddend..Iadd.
70. The stacked capacitor construction of claim 68 wherein the
electrically conductive layer provided over the dielectric layer
comprises conductively doped polysilicon. .Iaddend..Iadd.
71. The stacked capacitor construction of claim 68 wherein the
electrically conductive storage node comprises conductively doped
polysilicon and the electrically conductive layer provided over the
dielectric layer comprises conductively doped polysilicon.
.Iaddend..Iadd.
72. A stacked capacitor construction formed within a semiconductor
substrate comprising:
a layer of insulating dielectric material located on the
semiconductor substrate having at least one contact opening
therein, the contact opening having a minimum selected open contact
dimension;
an electrically conductive storage node, the storage node having
external sidewalls, the external sidewalls each having a surface
thereon to maximize surface area and corresponding capacitance, the
surfaces of the external sidewalls including striations, the
electrically conductive storage node having a thickness, the
thickness less than about 30% of the minimum selected open contact
dimension of the contact opening in the layer of insulating
dielectric material;
a dielectric layer provided over the storage node and its
associated external sidewalls, the dielectric layer including
striations; and
an electrically conductive layer provided over the dielectric
layer, the surface of the electrically conductive layer including
partial striations. .Iaddend..Iadd.
73. The stacked capacitor construction of claim 72 wherein the
electrically conductive storage node comprises conductively doped
polysilicon. .Iaddend..Iadd.
74. The stacked capacitor construction of claim 72 wherein the
electrically conductive layer provided over the dielectric layer
comprises conductively doped polysilicon. .Iaddend..Iadd.
75. The stacked capacitor construction of claim 72 wherein the
electrically conductive storage node comprises conductively doped
polysilicon and the electrically conductive layer provided over the
dielectric layer comprises conductively doped polysilicon.
.Iaddend..Iadd.
76. A stacked capacitor construction formed within a semiconductor
substrate comprising:
a layer of insulating dielectric material located on the
semiconductor substrate having at least one contact opening
therein, the contact opening having a minimum selected open contact
dimension;
an electrically conductive storage node, the storage node having
external sidewalls, the external sidewalls each having a surface
thereon to maximize surface area and corresponding capacitance, the
surfaces of the external sidewalls including striations the
electrically conductive storage node having a thickness, the
thickness less equal to about 30% of the minimum selected open
contact dimension of the contact opening in the layer of insulating
dielectric material;
a dielectric layer provided over the storage node and its
associated external sidewalls, the dielectric layer including
striations; and
an electrically conductive layer provided over the dielectric
layer, the surface of the electrically conductive layer including
partial striations. .Iaddend..Iadd.
77. The stacked capacitor construction of claim 76 wherein the
electrically conductive storage node comprises conductively doped
polysilicon. .Iaddend..Iadd.
78. The stacked capacitor construction of claim 76 wherein the
electrically conductive layer provided over the dielectric layer
comprises conductively doped polysilicon. .Iaddend..Iadd.
79. The stacked capacitor construction of claim 76 wherein the
electrically conductive storage node comprises conductively doped
polysilicon and the electrically conductive layer provided over the
dielectric layer comprises conductively doped polysilicon.
.Iaddend..Iadd.
80. A stacked capacitor construction formed within a semiconductor
substrate comprising:
a layer of insulating dielectric material located on the
semiconductor substrate having at least one contact opening
therein, the contact opening having a selected open contact
dimension;
an electrically conductive storage node, the storage node having
external sidewalls, the external sidewalls each having a surface
thereon to maximize surface area and corresponding capacitance, the
surfaces of the external sidewalls including striations, the
electrically conductive storage node having a thickness, the
thickness less than the minimum selected open contact dimension of
the contact opening in the layer of insulating dielectric
material;
a dielectric layer provided over the storage node and its
associated external sidewalls, the dielectric layer including
striations; and
an electrically conductive layer provided over the dielectric
layer, the surface of the electrically conductive layer including
partial striations. .Iaddend..Iadd.
81. The stacked capacitor construction of claim 80 wherein the
electrically conductive storage node comprises conductively doped
polysilicon. .Iaddend..Iadd.
82. The stacked capacitor construction of claim 80 wherein the
electrically conductive layer provided over the dielectric layer
comprises conductively doped polysilicon. .Iaddend..Iadd.
83. The stacked capacitor construction of claim 80 wherein the
electrically conductive storage node comprises conductively doped
polysilicon and the electrically conductive layer provided over the
dielectric layer comprises conductively doped polysilicon.
.Iaddend.
Description
TECHNICAL FIELD
This invention relates generally to three dimensional sack
capacitors and the fabrication thereof.
BACKGROUND OF THE INVENTION
As DRAMs increase in memory cell density, there is a continuous
challenge to maintain sufficiently high storage capacitance despite
decreasing cell area A principal way of increasing cell capacitance
is through cell structure techniques. Such techniques include three
dimensional cell capacitors such as trenched or stacked capacitors.
This invention concerns stacked capacitor cell constructions.
With the conventional stacked capacitor, the capacitor is formed
immediately above and electrically connected to the active device
area of the associated MOS transistor of the memory cell.
Typically, only the upper surface of the lower storage polysilicon
node of the capacitor is utilized for capacitance. However, some
attempts have been made to provide constructions to increase
capacitance, whereby the back side of one capacitor terminal is
used to store charge. Such is shown by way of example by T. Ema et
al. "3-Dimensional Stacked Capacitor Cell For 16M and 64M DRAMS",
IEDM Tech. Digest, pp. 592, 595, 1988 and S. Inoue et al., "A
Spread Stacked Capacitor (SSC) Cell For 64 MBit DRAMs", IEDM Tech.
Digest, pp. 31-34, 1989.
One standard prior art technique for forming a stacked "crown" cell
capacitor is described with reference to FIGS. 1-4. "Crown"
capacitors are characterized by upward spire-like, or fin-like
projections, thereby increasing surface area and corresponding
capacitance as compared to planar capacitors. FIG. 1 illustrates a
semiconductor wafer fragment 10 comprised of a bulk substrate 12,
word lines 14, 16, field oxide region 18, and an active area 20 for
connection with a capacitor. Wafer 10 also comprises a layer of
insulating dielectric 22 through which a desired contact opening 24
has been provided to active area 20. Referring to FIGS. 1 and 2,
contact opening 24 has an elliptical or circular shape with walls
26. The vertical lines illustrated in FIG. 1 illustrate shading
only for identifying sidewalls 26 and depicting a smooth surface
which arcs into the page. Such lines do not indicate texture or
other patterning. Sidewalls 26 are typically smooth and straight.
The elliptical shape of contact 24 can be produced by depositing a
photoresist film over the bulk substrate 10 and transferring the
contact 24 pattern by photolithographic means using the proper
image mask.
Referring to FIG. 3, a layer 28 of conductive material, such as
conductively doped polysilicon, is deposited atop wafer 10 and to
within contact opening 24. Layer 28 will provide the storage node
poly for formation of one of the capacitor plates.
Referring to FIG. 4, polysilicon layer 28 is first chemical
mechanical polished or resist planerization dry etched to be flush
with the upper surface of insulating layer 22. Thereafter,
insulating layer 22 is etched selectively relative to polysilicon
to produce an isolated storage node 30 having the illustrated crown
portions projecting upwardly from layer 22. Thereafter, a cell
dielectric would be deposited, followed by a cell polysilicon layer
to complete the capacitor construction.
It is an object of this invention to enable such and similar
stacked capacitor constructions to have increased capacitance.
BRIEF DESCRIPTION OF THE DRAWINGS
Preferred embodiments of the invention are described below with
reference to the following accompanying drawings.
FIG. 1 is a cross sectional/elevational view of a semiconductor
wafer fragment processed in accordance with prior art techniques,
and is described in the "Background" section above.
FIG. 2 is a top view of the FIG. 1 wafer fragment, with the line
1--1 illustrating where the FIG. 1 section cut is taken.
FIG. 3 is a cross section/elevational view of the FIG. 1 wafer
fragment illustrated at a processing step subsequent to that shown
by FIGS. 1 and 2.
FIG. 4 is a cross sectional/elevational view of the FIG. 1 wafer
fragment illustrated at a processing step subsequent to that shown
by FIG. 3.
FIG. 5 is a cross sectional/elevational view of a semiconductor
wafer fragment processed in accordance with the invention.
FIG. 6 is a top view of the FIG. 5 wafer fragment, with the line
5--5 illustrating where the FIG. 5 section cut is taken.
FIG. 7 is a cross sectional/elevational view of the FIG. 5 wafer
fragment illustrated at a processing step subsequent to that shown
by FIGS. 5 and 6.
FIG. 8 is a top view of the FIG. 7 wafer fragment, with the line
7--7 illustrating where the FIG. 7 section cut is taken.
FIG. 9 is a cross sectional/elevational view of the FIG. 5 wafer
fragment illustrated at a processing step subsequent to that shown
by FIGS. 7 and 8.
FIG. 10 is a cross sectional/elevational view of the FIG. 9 wafer
fragment taken through line 10--10 in FIG. 9.
FIG. 11 is a cross sectional/elevational view of the FIG. 5 wafer
fragment illustrated at a processing step subsequent to that shown
by FIGS. 9 and 10.
FIG. 12 is a cross sectional/elevational view of the FIG. 11 wafer
fragment taken through line 12--12 in FIG. 11.
FIG. 13 is a cross sectional/elevational view of the FIG. 5 wafer
illustrated at a processing step subsequent to that shown by FIG.
12.
FIG. 14 is a top view of a prior art capacitor contact opening.
FIG. 15 is a top view of a capacitor contact opening produced in
accordance with the invention.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
This disclosure of the invention is submitted in furtherance of the
constitutional purposes of the U.S. Patent Laws "to promote the
progress of science and useful arts" (Article 1, Section 8).
In accordance with one aspect of the invention, a method of forming
a capacitor on a semiconductor wafer comprises the following
steps:
providing a layer of insulating dielectric atop a semiconductor
wafer to a selected thickness;
in a dry etching reactor, selectively anisotropically dry etching a
capacitor contact opening having a minimum selected open dimension
into the insulating dielectric layer utilizing selected gas flow
rates of a reactive gas component and an inert gas bombarding
component, the flow rate of the bombarding component significantly
exceeding the flow rate of the reactive component to effectively
produce a capacitor contact opening having grooved striated
sidewalls and thereby defining female capacitor contact opening
striations;
providing a layer of electrically conductive material atop the
wafer and within the striated capacitor contact opening to a
selected thickness which is less than the selected open dimension,
the electrically conductive material filling the grooved striations
of the capacitor contact opening thereby defining striated external
conductive material sidewalls within the capacitor contact opening
which are male complementary its shape to the female capacitor
contact opening striations;
removing at least a portion of the conductive material layer to
define an isolated capacitor storage node within the insulating
dielectric;
etching the insulating dielectric layer selectively relative to the
conductive material sufficiently to expose at least a portion of
the external male striated conductive material sidewalls;
providing a conformal capacitor dielectric layer atop the etched
conductive material and over its exposed striated sidewalls;
and
providing a conformal capacitor cell layer of electrically
conductive material atop the capacitor dielectric layer.
In accordance with another aspect of the invention, a stacked
capacitor construction formed within a semiconductor substrate
comprises:
an electrically conductive storage node, the storage node having
upwardly rising external sidewalls, the upwardly rising external
sidewalls having longitudinally extending striations to maximize
surface area and corresponding capacitance;
a striated cell dielectric layer provided over the storage node and
its associated longitudinally extending striations; and
an electrically conductive striated cell layer provided over the
striated cell dielectric layer.
More particularly and with reference to the figures, FIG. 5
illustrates a semiconductor wafer fragment 40 comprised of a bulk
silicon substrate 42, word lines 44, 46, field oxide region 48, and
active area 50. A layer 52 of insulating dielectric, such as
SiO.sub.2, is also provided to a selected thickness. A unique
capacitor contact opening 54 is etched through insulating layer 52
to upwardly expose contact opening 54.
More specifically, contact opening 54 results from a selective
anisotropic dry etch in a dry etching reactor to produce a minimum
selected open dimension "A" into insulating dielectric layer 52. A
wider open dimension "C" for contact opening 54 results from the
elliptical shape. Such etching is conducted utilizing selected gas
flow rates of a reactive gas component and an inert gas bombarding
component. The flow rate of the bombarding component significantly
and effectively exceeds the flow rate of the reactive component to
produce capacitor contact opening 54 having grooved striated
sidewalls 56. As illustrated, striated sidewalls have peak ridges
55 and low valleys 57, which define (for purposes of continuing
discussion) female capacitor contact opening striations 58.
Effective excess flow of an inert gas bombarding component, as
compared to the reactive gas component, has been determined to
enable controllable production of the illustrated striations.
The bombarding gas component is preferably selected from the group
consisting of argon, krypton and xenon or mixtures thereof. The
invention was reduced to practice utilizing argon. The reactive gas
component need be reactive with the insulating material of layer
52. Where such layer comprises SiO.sub.2, reactive gas components
of CF.sub.4 and CHF.sub.3 would be operable. Preferably, the flow
rate to the reactor of the bombarding gas component is sufficient
to produce a partial pressure of bombarding gas within the reactor
of greater than or equal to about 31 mTorr.
Argon, CF.sub.4 and CF.sub.3 are known prior art components for
etching smooth-walled contact openings through SiO.sub.2 layers but
not utilized in the manner claimed in this document For example, a
conventional prior art process for etching a prior art contact
opening 24 (FIG. 1) into a SiO.sub.2 layer of dielectric in an
Applied Materials P5000.TM. etcher includes argon at 50 sccm,
CF.sub.4 at 20 sccm, and CHF.sub.3 at 25 sccm, providing a total
reactor pressure of 100 mTorr. Such provides a partial pressure of
argon within the reactor of approximately 50 mTorr, with such an
etch producing substantially smooth contact opening sidewalls. This
invention was reduced to practice, in part, utilizing the same
Applied Materials P5000.TM. reactor and flow rates of Ar at 90
sccm, CF.sub.4 at 20 sccm, and CHF.sub.3 at 25 sccm. Total reactor
pressure was 50 mTorr, power supplied was 700, magnetic field
strength was 75 gauss, oxide thickness was 2 microns, and the runs
were conducted for 300 seconds. The P5000.TM. etcher has an
internal volume of 4.6 liters, which produced a partial pressure of
Ar at a 90 sccm flow rate of 31 mTorr. Example runs were also
conducted at Ar flow rates of 60 sccm and 110 sccm, with the flow
rates of CF.sub.4 and CHF.sub.3 for each such run being maintained
at 20 sccm and 25 sccm, respectively. The 60 sccm Ar flow rate
example produced no striations, while the 110 sccm Ar flow rate
produced significant striations equal or greater in magnitude than
that produced by the 90 sccm example above. From such data, it is
apparent that the desired striations can be produced where the flow
rate of the bombarding gas component significantly exceeds the flow
rate of the reactive component in an amount sufficient to
effectively produce grooved striated contact opening sidewalls and
thereby define female capacitor contact opening striations.
Referring to FIGS. 7 and 8, a layer 60 of electrically conductive
material such as conductively doped polysilicon, is provided atop
wafer 10 and within striated capacitor contact opening 54 to a
selected thickness "B" which is less than the selected open
dimension "A". Electrically conductive material 60 fills grooved
striations 58 of capacitor contact opening 54. This thereby defines
a striated external conductive material sidewall 62 within
capacitor contact opening 54 which has external male striations 59
which are complementary in shape to female capacitor contact
opening striations 58. Selected thickness "B" is most preferably
less than or equal to about 30% of minimum selected open contact
dimension "A" to provide sufficient space within contact opening 54
for subsequent provision of a capacitor dielectric layer and cell
polysilicon layer. An example preferred thickness for poly layer 60
would be 1200 Angstroms. Such could be deposited by known
techniques, and thereafter further texturized as desired. As
illustrated, striations from external conductive material sidewall
62 transfer to an internal conductive material sidewall 65,
producing internal male striations 59a
Referring to FIGS. 9 and 10, thickness "B" of polysilicon layer 60
is removed atop dielectric 52 by a conventional polish or etching
technique to define an isolated capacitor storage node within
insulating dielectric layer 52. Insulating dielectric layer 52 is
then selectively etched relative to polysilicon layer 60 to expose
at least a portion of external male striated conductive material
sidewalls 62 and associated external male striations 59 (FIG.
10).
Referring to FIGS. 11 and 12, a conformal capacitor dielectric
layer 64 such as Si.sub.3 N.sub.4, is conformally deposited atop
the etched conductive material 60 and over its exposed striated
sidewalls 62. Such striations translate through capacitor
dielectric layer 64 such that its external surface 67 is as well
striated. Additionally, internal conductive material striations 59a
translate to striate internal capacitor dielectric material
sidewalls 69.
Referring to FIG. 13, a conformal capacitor cell layer 66 of
conductive material, such as conductively doped polysilicon, is
conformally deposited atop capacitor dielectric layer 64.
Striations from internal and external surfaces of layer 64 will
probably only partially translate to outer surfaces of layer 66 due
to the increasing thickness and corresponding smoothing effect
imparted by subsequent layers. Layers 66 and 64 may be subsequently
etched, as desired, to pattern desired capacitor constructions.
The above-described technique and construction increases contact
sidewall surface area significantly over the prior art for
maximization of capacitance for a given photo feature size. The
prior art embodiment of FIGS. 1-4 and the embodiment of the
invention of FIGS. 5-13 utilize the same photo tool. Yet, a greater
surface area of the contact opening is produced as a result of the
described anisotropic dry etch which effectively increases the
radius of the inventive contact over that of the standard prior art
contact. The effect is shown in contrast in FIGS. 14 and 15. FIG.
14 shows a prior art contact 100, while FIG. 15 shows a contact 200
in accordance with the invention, both of which are made from the
same photo tool. Contact 100 has some effective or average radius
"r", while contact 200 has an effective or average radius "r",
which is slightly greater than "r", thus increasing surface
area.
The intent is to maximize flow of the bombarding component, while
minimizing total reactor pressure, and thereby increase the flow
rate of argon relative to the reactive gas components. The
invention functions by providing a pretexturized, striated surface
before polysilicon is deposited to maximize surface area in both
external and internal portions of the deposited polysilicon. The
resultant product is improved over the prior art the result of
increased capacitance.
In compliance with the statute, the invention has been described in
language more or less specific as to structural and methodical
features. It is to be understood, however, that the invention is
not limited to the specific features shown and described, since the
means herein disclosed comprise preferred forms of putting the
invention into effect. The invention is, therefore, claimed in any
of its forms or modifications within the proper scope of the
appended claims appropriately interpreted in accordance with the
doctrine of equivalents.
* * * * *