Set of buttons on motherboard

Wu , et al. March 16, 2

Patent Grant D611916

U.S. patent number D611,916 [Application Number D/325,367] was granted by the patent office on 2010-03-16 for set of buttons on motherboard. This patent grant is currently assigned to Asustek Computer Inc.. Invention is credited to Meng-Jia Guo, Yu-Chen Lee, Chih-Shien Lin, Chien-Chin Wang, Chao-Chung Wu.


United States Patent D611,916
Wu ,   et al. March 16, 2010

Set of buttons on motherboard

Claims

CLAIM The ornamental design for set of buttons on motherboard, as shown and described.
Inventors: Wu; Chao-Chung (Taipei, TW), Guo; Meng-Jia (Taipei, TW), Lin; Chih-Shien (Taipei, TW), Wang; Chien-Chin (Taipei, TW), Lee; Yu-Chen (Taipei, TW)
Assignee: Asustek Computer Inc. (Taipei, TW)
Appl. No.: D/325,367
Filed: September 30, 2008

Foreign Application Priority Data

May 5, 2008 [TW] 97302629
Current U.S. Class: D13/171
Current International Class: 1303
Field of Search: ;D13/171 ;174/66 ;200/5R,5A,1B,293,296,329,406,513,520,530,302.1,302.2,314,315,341,344 ;315/291-296 ;338/198-200

References Cited [Referenced By]

U.S. Patent Documents
1747896 February 1930 Gates
4127838 November 1978 Neveux
D266084 September 1982 Colavecchio
4454397 June 1984 Kim
5077454 December 1991 Lorenzo
D362841 October 1995 Roza
D377337 January 1997 Schaeffer
6103982 August 2000 Chien
D469411 January 2003 Decosse
D496336 September 2004 Wang
6965085 November 2005 Orrico et al.
7180021 February 2007 Birdwell et al.
2007/0221485 September 2007 Yang et al.
2007/0235312 October 2007 Takeuchi
Primary Examiner: Sikder; Selina
Attorney, Agent or Firm: Kirton & McConkie Witt; Evan R.

Description



FIG. 1 is a perspective view of set of buttons on motherboard showing our new design;

FIG. 2 is a right side view of FIG. 1;

FIG. 3 is a top view of FIG. 1;

FIG. 4 is a front view of FIG. 1;

FIG. 5 is a bottom view of FIG. 1;

FIG. 6 is a left side view of FIG. 1;

FIG. 7 is a rear view of FIG. 1;

FIG. 8 is a top plan view showing the buttons of FIG. 1 disposed on a motherboard;

FIG. 9 is a top plan view showing an alternate location of the buttons of FIG. 1 disposed on a motherboard; and,

FIG. 10 is a partial front side view of FIG. 8.

The broken lines shown are for illustrative purposes only and form no part of the claimed design.

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