Tray for semiconductor devices with castellations

Description

FIG. 1 is a perspective view of a tray for semiconductor devices with castellations showing my new design;

FIG. 2 is a top plan view thereof;

FIG. 3 is a front elevational view, the rear elevational view being a mirror image thereof;

FIG. 4 is a right side elevational view, the left side elevational view being a mirror image thereof; and,

FIG. 5 is a bottom plan view thereof.

The broken line showing of the environment is for illustrative purposes only and forms no part of the claimed design.

Claims

CLAIM The ornamental design for tray for semiconductor devices with castellations, as shown and described.

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Inventors:	Di Stefano; Thomas H. (Monte Sereno, CA)
Assignee:	Centipede Systems, Inc. (San Jose, CA)
Appl. No.:	D/304,013
Filed:	February 22, 2008

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Current U.S. Class:	D13/182
Current International Class:	1303
Field of Search:	;D13/182 ;206/701,706,707,710,716,724,725

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References Cited [Referenced By]

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U.S. Patent Documents

4881639	November 1989	Matsuoka et al.
5103976	April 1992	Murphy
5957293	September 1999	Pakeriasamy
5960961	October 1999	Gutentag
6021904	February 2000	Kozol et al.
6179127	January 2001	Kato et al.
6227372	May 2001	Thomas et al.
6296122	October 2001	Nakazono et al.
6474477	November 2002	Chang
D496339	September 2004	Stanley
6857524	February 2005	Duban-Hu et al.
D522471	June 2006	Sisson
2002/0162770	November 2002	Chang
2006/0071656	April 2006	Joung et al.

Primary Examiner: Sikder; Selina
Attorney, Agent or Firm: Townsend and Townsend and Crew LLP Allen; Kenneth R.