Semiconductor wafer measuring instrument

Description

FIG. 1 is a top, front and right side perspective view of a semiconductor wafer measuring instrument showing my new design;

FIG. 2 is a front elevational view;

FIG. 3 is a right side elevational view, the left side elevational view being a mirror image;

FIG. 4 is a top plan view;

FIG. 5 is a rear elevational view; and

FIG. 6 is a bottom plan view thereof.

Claims

The ornamental design for a semiconductor wafer measuring instrument, as shown and described.

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Inventors:	Takao; Itaru (Yamanashi, JP)
Assignee:	Tokyo Electron Limited (Tokyo, JP)
Appl. No.:	07/343,124
Filed:	April 25, 1989

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Current U.S. Class:	D10/46
Field of Search:	;D10/46,75,81 ;269/13,14,20,21,296,903 ;324/158P ;414/222,225,589,590,627,673,752

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References Cited [Referenced By]

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U.S. Patent Documents

D188789	September 1960	Hannon
D223174	March 1972	Pettavel
D262950	February 1982	Orr, II
D277979	March 1985	Brown et al.
D307397	April 1990	Lehtikoski
D314347	February 1991	Garnish et al.
4530635	July 1985	Engelbrecht et al.
4684113	August 1987	Douglas et al.
4700488	October 1987	Curti
4719705	January 1988	Laganza et al.
4723766	February 1988	Beeding
4907931	March 1990	Mallory et al.
4938654	July 1990	Schram
4941800	July 1990	Koike et al.
4955590	September 1990	Narushima et al.

Foreign Patent Documents

	733184		Jan 1988		JP

Primary Examiner: Dunkins; Bruce W.
Assistant Examiner: Davis; Antoine D.
Attorney, Agent or Firm: Oblon, Spivak, McClelland, Maier & Neustadt