High density component mounting back panel for electronic equipment

Littlefield , et al. August 28, 1

Patent Grant D275279

U.S. patent number D275,279 [Application Number 06/178,641] was granted by the patent office on 1984-08-28 for high density component mounting back panel for electronic equipment. This patent grant is currently assigned to Redcom Laboratories, Inc.. Invention is credited to Charles J. Breidenstein, Jerome S. Caplan, Bruce G. Littlefield.


United States Patent D275,279
Littlefield ,   et al. August 28, 1984

High density component mounting back panel for electronic equipment

Claims

The ornamental design for high density component mounting back panel for electronic equipment as shown and described.
Inventors: Littlefield; Bruce G. (Honeoye Falls, NY), Caplan; Jerome S. (Henrietta, NY), Breidenstein; Charles J. (Rochester, NY)
Assignee: Redcom Laboratories, Inc. (Fairport, NY)
Appl. No.: 06/178,641
Filed: August 15, 1980

Current U.S. Class: D13/147; D13/182
Field of Search: ;D13/24,41,12,99,40 ;339/17C,17M,18R,18B ;174/68.5 ;361/415,412,403,399

References Cited [Referenced By]

U.S. Patent Documents
3300686 January 1967 Johnson et al.
3838317 September 1974 Coyne
4160880 July 1979 Brey
Primary Examiner: Lucas; Susan J.
Attorney, Agent or Firm: LuKacher; Martin

Description



FIG. 1 is a top, front perspective view of a high density component mounting back panel for electronic equipment showing our new design;

FIG. 2 is a bottom rear perspective view thereof;

FIg. 3 is an enlarged top plan view thereof, the mounted receptacle blocks being omitted for purposes of disclosure;

FIG. 4 is an enlarged bottom plan view thereof, the mounted elements being omitted for purposes of disclosure;

FIG. 5 is a side elevational view thereof;

FIG. 6 is a front elevational view thereof; and

FIG. 7 is a rear elevational view thereof.

The characteristic feature of the invention is the front and rear surface ornamentation provided by dark areas of conductive material as shown in FIGS. 3 and 4 and the arrangement of receptacles upon the front and rear surfaces as shown in FIGS. 1, 2, and 5-7. The contrasting dark areas on the circuit board are omitted in FIGS. 1 and 2 for ease of illustration.

The receptacle blocks and the apertures thereon are partially shown for convenience of illustration, it being understood that the receptacles and apertures are continuous across the board and receptacles respectively as indicated by the broken lines.

* * * * *


uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed