U.S. patent number 9,509,305 [Application Number 14/151,337] was granted by the patent office on 2016-11-29 for power gating techniques with smooth transition.
This patent grant is currently assigned to FREESCALE SEMICONDUCTOR, INC.. The grantee listed for this patent is Freescale Semiconductor, Inc.. Invention is credited to Akshat Gupta, Sunny Gupta, Ivan Carlos Ribeiro Nascimento, Akshay K. Pathak, Adriano Marques Pereira, Garima Sharda, Pedro Barbosa Zanetta.
United States Patent |
9,509,305 |
Nascimento , et al. |
November 29, 2016 |
Power gating techniques with smooth transition
Abstract
In an embodiment, an electronic device includes an integrated
circuit (IC) having a plurality of power domains, a first regulator
coupled to a given power domain, a second regulator coupled to the
given power domain, and a switching circuit coupled between the
first and second regulators and configured to control an amount of
current drawn by the power domain from the first and/or second
regulators. In another embodiment, a method includes controlling an
impedance of a switching circuit to change an amount of current,
the switching circuit coupled to a given power domain of an IC
configured to operate in a first mode followed by a second mode,
where the switching circuit is coupled to a first regulator
configured to provide more power to the IC than a second regulator,
and a transition period includes turning off the first regulator
and turning on the second regulator.
Inventors: |
Nascimento; Ivan Carlos Ribeiro
(Campinas, BR), Gupta; Akshat (New Delhi,
IN), Gupta; Sunny (Noida, IN), Pathak;
Akshay K. (Noida, IN), Pereira; Adriano Marques
(Campinas, BR), Sharda; Garima (Ghaziabad,
IN), Zanetta; Pedro Barbosa (Campinas,
BR) |
Applicant: |
Name |
City |
State |
Country |
Type |
Freescale Semiconductor, Inc. |
Austin |
TX |
US |
|
|
Assignee: |
FREESCALE SEMICONDUCTOR, INC.
(Austin, TX)
|
Family
ID: |
53495946 |
Appl.
No.: |
14/151,337 |
Filed: |
January 9, 2014 |
Prior Publication Data
|
|
|
|
Document
Identifier |
Publication Date |
|
US 20150194887 A1 |
Jul 9, 2015 |
|
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H03K
19/0013 (20130101) |
Current International
Class: |
H03K
5/08 (20060101); H03K 19/00 (20060101) |
Field of
Search: |
;327/309-330
;323/271-272 |
References Cited
[Referenced By]
U.S. Patent Documents
Primary Examiner: Donovan; Lincoln
Assistant Examiner: Retebo; Metasebia
Claims
The invention claimed is:
1. An electronic device, comprising: an integrated circuit
including a plurality of power domains; a first voltage regulator
coupled to a given one of the plurality of power domains; a second
voltage regulator coupled to the given one of the plurality of
power domains; and a switching circuit coupled between the first
power regulator and the second power regulator, the switching
circuit configured to gradually change an amount of current drawn
by the given one of the plurality of power domains from at least
one of the first or second voltage regulators during a transition
period, wherein the switching circuit is conductive during the
entire transition period.
2. The electronic device of claim 1, wherein the transition period
includes a turning off of the first voltage regulator and a turning
on of the second voltage regulator.
3. The electronic device of claim 1, wherein the first voltage
regulator is configured to enable operation of at least a portion
of the integrated circuit in a first power mode, wherein the second
voltage regulator is configured to enable operation of the at least
one portion of the integrated circuit in a second power mode, and
wherein the first power mode provides more current than the second
power mode.
4. The electronic device of claim 1, wherein the integrated
circuit, the second voltage regulator, and the switching circuit
are within a same electronic package, and wherein the first voltage
regulator is external to the electronic package.
5. The electronic device of claim 1, further comprising a logic
circuit coupled to the switching circuit, the logic circuit
configured to gradually decrease the amount of current in discrete
time intervals during the transition period.
6. The electronic device of claim 5, wherein the logic circuit is
further configured to reduce the amount of current from a first
value to a second value, wait until an output of the second voltage
regulator has settled, and reduce the amount of current from the
second value to a third value, wherein a difference between the
first and second values is equal to a difference between the second
and third values.
7. The electronic device of claim 5, wherein the logic circuit is
further configured to decrease the amount of current until a
minimum predetermined amount of current is reached.
8. The electronic device of claim 5, wherein the logic circuit is
further configured to decrease the amount of current until the
second voltage regulator outputs a predetermined voltage level or a
predetermined amount of current.
9. The electronic device of claim 1, the switching circuit further
comprising: a first current mirror including a first transistor and
a second transistor, the first transistor including a first current
terminal coupled to an output of the first voltage regulator, the
first transistor including a second current terminal coupled to the
second voltage regulator, the second transistor including a first
current terminal coupled to the first current terminal of the first
transistor, and the second transistor including a control terminal
coupled to a control terminal of the first transistor; and a second
current mirror including a third transistor and a fourth
transistor, the third transistor including a first current terminal
coupled to a second current terminal of the second transistor, the
third transistor including a second current terminal coupled to a
first current source and directly coupled to the control terminals
of the first and second transistors, the fourth transistor
including a first current terminal coupled to the second current
terminal of the first transistor, the fourth transistor including a
second current terminal coupled to a second current source, and the
fourth transistor including a control terminal coupled to a control
terminal of the third transistor and to the second current terminal
of the fourth transistor.
10. The electronic device of claim 9, wherein the amount of current
is proportional to an aspect ratio of the first transistor divided
by an aspect ratio of the second transistor.
11. The electronic device of claim 10, wherein an aspect ratio of
the fourth transistor is greater than an aspect ratio of the third
transistor.
12. A method, comprising: controlling an impedance of a switching
circuit to change an amount of current flowing through the
switching circuit, wherein the switching circuit is coupled to a
given one of a plurality of power domains of an integrated circuit,
wherein the integrated circuit is configured to operate in a first
mode followed by a second mode such that a transition period occurs
between the first and second modes, wherein the switching circuit
is conductive during the entire transition period, wherein the
switching circuit is coupled to a first regulator and to a second
regulator, wherein the first regulator is configured to provide
more power to the integrated circuit than the second regulator, and
wherein the transition period includes a turning off of the first
voltage regulator and a turning on of the second voltage
regulator.
13. The method of claim 12, further comprising decoupling the
switching circuit from a ground node in response to a determination
that the transition period has ended.
14. The method of claim 12, wherein controlling the amount of
current includes decreasing the amount of current until a minimum
predetermined amount of current is reached.
15. The method of claim 12, wherein controlling the amount of
current includes decreasing the amount of current until the second
voltage regulator outputs a predetermined voltage or a
predetermined current.
16. The method of claim 12, wherein controlling the amount of
current includes gradually changing a resistance presented by the
switching circuit in discrete time intervals during the transition
period.
17. The method of claim 16, wherein gradually changing the
resistance includes reducing the amount of current from a first
value to a second value, waiting until an output of the second
voltage regulator settles, and reducing the amount of current from
the second value to a third value.
18. An integrated circuit, comprising: switching circuitry coupled
between a first voltage regulator and a second voltage regulator,
the first and second voltage regulators configured to provide power
to an integrated circuit, and the switching circuitry configured to
remain conductive during an entire transition period, to impose
gradually increasing limits upon an amount of current drawn by the
integrated circuit from the first voltage regulator during the
transition period.
19. The integrated circuit of claim 18, wherein the transition
period includes a turning off of the first voltage regulator and a
turning on of the second voltage regulator.
20. The integrated circuit of claim 18, the switching circuitry
further configured to consume zero Direct Current (DC) power
outside of the transition period.
Description
FIELD
This disclosure relates generally to electronic circuits and
devices, and more specifically, to systems and methods for enabling
power gating techniques with smooth transition.
BACKGROUND
Techniques for managing the power consumption of electronic devices
may include the use of Integrated Circuits (ICs) having multiple
power domains. Generally speaking, each power domain may allow a
circuit block within the IC to use a different amount of power than
other circuit blocks. For example, the use of power domains may
enable one or more circuit blocks to receive different amounts of
power depending upon the device's mode of operation, which can
change over time.
In some cases, different power domains may be separated by one or
more power switches or the like. For example, when a circuit block
within a given power domain is turned on, a corresponding switch
may allow that circuit to draw electrical current from a power
source. These techniques are often referred to as "power
gating."
BRIEF DESCRIPTION OF THE DRAWINGS
The present invention(s) is/are illustrated by way of example and
is/are not limited by the accompanying figures, in which like
references indicate similar elements. Elements in the figures are
illustrated for simplicity and clarity and have not necessarily
been drawn to scale.
FIG. 1 is a block diagram of an example of an electronic device
according to some embodiments.
FIG. 2 is a circuit diagram of an example of a power switch with
current limitation according to some embodiments.
FIG. 3 shows graphs illustrating aspects of the operation of a
power switch with current limitation according to some
embodiments.
FIG. 4 is a circuit diagram of an example of a power switch with
current limitation and zero Direct Current (DC) power consumption
according to some embodiments.
FIG. 5 is a flowchart of a method for enabling power gating
techniques with smooth transition according to some
embodiments.
FIG. 6 shows graphs illustrating methods for enabling power gating
techniques with smooth transition according to some
embodiments.
FIG. 7 is a diagram of an example of an electronic system having
one or more electronic microelectronic device packages, according
to some embodiments.
DETAILED DESCRIPTION
Turning to FIG. 1, a block diagram of an example of an electronic
device 100 is depicted according to some embodiments. In this
example, first regulator 101 and second regulator 102 are coupled
to integrated circuit 104 having two or more power domains (PDs)
111 and 112, respectively. First regulator 101 and second regulator
102 are also coupled to switching circuit 103. In some
implementations, second regulator 102, switching circuit 103, and
integrated circuit 104 may all be within the same electronic
package, and first voltage regulator 101 may be external to that
electronic package. For example, first regulator 101 may be a high
power voltage regulator and second regulator 102 may be a low power
(or ultra-low power) voltage regulator.
For sake of illustration, first regulator 101 is shown as receiving
V.sub.SUPPLY at transistor 105 and outputting V.sub.DD at an output
node between transistor 105 and capacitor 106, which in turn is
coupled to a reference node (GND). Similarly, second regulator 102
receives V.sub.SUPPLY at transistor 107 and outputs V.sub.DDO at an
output node between transistor 107 and capacitor 108, which in turn
is coupled to GND. It should be understood, however, that each of
regulators 101 and 102 may include a number of other internal
electronic components in addition to and/or as an alternative to
those shown herein. In some implementations, each of regulators 101
and 102 may be a different type of voltage regulator including, but
not limited to, linear regulators, switching regulators, etc.
Generally speaking, switching circuit 103 operates to separate the
various power domains 111 and 112. Even when power domains 111 and
112 are configured to operate based on the same supply voltage,
they may each be configured to draw up to a maximum amount of
current from regulators 101 and/or 102. For example, power domain
111 may be configured to use up to 500 mA and power domain 112 may
be configured to use up to 50 mA.
In some embodiments, switching circuit 103 may be configured to
limit an amount of current drawn by a given one of power domains
111 and 112 from regulators 101 and/or 102 during a transition
period--e.g., during a switching between (i) a high power mode
where V.sub.DD is provided by first regulator 101 and second
regulator 102 is turned off, and (ii) a low power mode where
V.sub.DDO is provided by second regulator 102 and first regulator
101 is turned off. In some implementations, during at least a part
of such a transition period, both the first and second regulators
101 and 102 may be turned on. Outside of the transition period,
switching circuit 103 may be configured to consume zero Direct
Current (DC) power, also known as static power, be it closed or
open (excluding consumption due to leakage effects or the
like).
For example, when device 100 is operating in high power mode, first
regulator 101 may output a voltage V.sub.DD slightly higher than
voltage V.sub.DDO that would otherwise be output by second
regulator 102, and therefore second regulator 102 may be turned
off. Particularly, when both first and second regulators 101 and
102 have the same nominal output voltage (e.g., 1.2 V), certain
variations may still cause them to output slightly different
voltages (e.g., 1.21 and 1.18 V). Then, at some point during
operation of device 100, a determination may be made that device
100 begin operating in a low power mode.
At the beginning of the transition period, switch 109 within
switching circuit 103 may be in a closed state--i.e., fully
conductive--and, at the end of the transition period, switch 109
may be in an open state--i.e., fully non-conductive. In between
these two states, current limitation element 110 of switching
circuit 103 may operate to control an amount of current that is
allowed to flow from first regulator 101 to second regulator 102,
and therefore it may also control an amount of current that can be
drawn by a given one of power domains 111 and/or 112 from the first
and/or second regulators 101 and 102. In some cases, the current
limitation provided by switching circuit 103 may impose gradually
increasing limits upon that amount of current, which then promotes
a smooth transition between the two operating modes (e.g., from a
high power mode to a low power mode), as described in more detail
below.
In some embodiments, power domains 111 and 112 may represent
different areas of integrated circuit 104 responsible for
performing different operations. For example, each of power domains
111 and 112 may include analog circuits, digital memories,
processors, etc. Moreover, it should be noted that device 100 is
shown for sake of illustration only. In various embodiments, any
number of power supplies, switches, and/or power domains may be
used, and these elements may be coupled to one another in any
suitable manner.
FIG. 2 is a circuit diagram of an example of switching circuit 103
with current limitation according to some embodiments. For sake of
context, switching circuit 103 is shown coupled between first
regulator 101 and second regulator 102, as originally discussed in
FIG. 1. It will be understood, however, that switching circuit 103
may be used in other contexts as well.
As illustrated, switching circuit 103 includes first P-type
Metal-Oxide-Semiconductor (PMOS) transistor M1 having its source
terminal (more generally referred to as a first current terminal or
electrode) coupled to first regulator 101, thus receiving supply
voltage V.sub.DD, and its drain terminal (more generally referred
to as a second current terminal or electrode) coupled to power
domain 105B, thus providing V.sub.DDO (where V.sub.DDO is equal to
V.sub.DD minus the voltage drop across M1). Second PMOS transistor
M2 has its source terminal coupled to first regulator 101, thus
also receiving supply voltage V.sub.DD, and its gate (more
generally referred to as a control terminal or electrode) coupled
to the gate of first PMOS transistor M1. In combination,
transistors M1 and M2 form first current mirror 201. As shown in
more detail below, M1 operates as a current limitation transistor,
whereas M2 operates as a main switching transistor.
Switch 103 also includes third PMOS transistor M3 having its source
terminal coupled to the drain terminal of second PMOS transistor
M2, and its drain terminal coupled to node n1 and to the gates of
the first and second PMOS transistors M1 and M2, respectively.
Fourth PMOS transistor M4 has its source terminal coupled to the
drain terminal of first PMOS transistor M1, its drain terminal
coupled to node n0, and its gate terminal coupled to the gate
terminal of third PMOS transistor M3 and to node n0. As such,
transistors M3 and M4 form second current mirror 202. Current
source I10 is coupled between node n1 and a reference node (GND)
106, and current source I11 is coupled between node n0 and the
reference node 106. Current sources I10 and I11 may be implemented
using well-known components.
Nodes n0, n1, and n3 are shown such that node n1 is the node
between the gate terminals of transistors M1 and M2, the drain
terminal of transistor M3, and current source I10. Node n0 is the
node between the gate terminals of transistors M3 and M4, the drain
terminal of transistor M4, and current source I11. Node n3 is the
node between the drain of transistor M2 and the source of
transistor M3.
In operation, switching circuit 103 allows only a limited amount of
electrical current I.sub.LIM to flow through it. The analysis that
follows shows, among other things, that I.sub.LIM is a function of
the current at the drain terminals of transistors M3 and M4,
designated as I.sub.1, as well as of the aspect ratios of
transistors M1 and M2.
For transistors M3 and M4 let us define:
##EQU00001##
where W.sub.n is the width and L.sub.n is the length of the channel
formed in transistor M.sub.n such that W.sub.3/L.sub.3 is the
aspect ratio of transistor M3 and W.sub.4/L.sub.4 is the aspect
ratio of transistor M4. For example, in some embodiments,
transistors M3 and M4 may be unbalanced such that W.sub.4/L.sub.4
is greater than W.sub.3/L.sub.3. Also, in some implementations, the
gate-to-source voltage of transistor M3 (V.sub.GS3) is greater than
the gate-to-source voltage of transistor M4 (V.sub.GS4), such that
K.sub.34<1. As such, the current equations for transistors M3
and M4 in saturation are:
.times..times..times..times. ##EQU00002##
.times..times..times..times. ##EQU00002.2##
where I.sub.Dn is the drain current of transistor M.sub.n. If we
use V.sub.T as the threshold voltage and K.sub.p as the
transconductance parameter for transistor M3, then:
.times..times. ##EQU00003##
Considering M3 to be in its saturation region, this yields:
.times..times..times..times. ##EQU00004##
.times..times..times..times. ##EQU00004.2##
The difference of V.sub.GS drop voltages, in saturation region,
considering the same I.sub.1 current pass by M3 and M4 is
calculated. The .DELTA.V.sub.GS34 is then calculated as:
.DELTA..times..times..times..times..times..times..times..times..times..ti-
mes. ##EQU00005##
In conclusion, while (V.sub.GS3-V.sub.GS4) is equal or greater than
.DELTA.V.sub.GS34, transistor M.sub.3 allows I.sub.1 current to
pass, and, therefore, V.sub.DSM3 will be low (whether transistor
M.sub.3 is in saturation, triode or linear regions). Conversely, if
V.sub.GS3 is not higher than V.sub.GS4 by at least
.DELTA.V.sub.GS34, then transistor M.sub.3 just allow a current
lower than I.sub.1 to pass, and V.sub.DS3 increases.
The remainder of the analysis depends upon whether transistors
M.sub.1 and M.sub.2 are operating either in saturation mode or in
triode/linear modes. Particularly, when V.sub.DD>>V.sub.DDO,
transistors M1 and M2 are in saturation region. The saturation
region is defined as the region where the V.sub.DS drop voltages of
M.sub.1 and M.sub.2 are above the saturation V.sub.DS, that is,
V.sub.DS1>.sub.VDS.sub._.sub.SAT.sub._.sub.M1 and
V.sub.DS2>V.sub.DS.sub._.sub.SAT.sub._.sub.M2, where:
V.sub.DS1=V.sub.DD-V.sub.DDO and V.sub.DS2=V.sub.DD-V(n3)
According to the MOS model, the minimum V.sub.DS for saturation is
given by:
V.sub.DS.sub._.sub.SAT.sub._.sub.M2=V.sub.GSM2-V.sub.T=V.sub.DD-V(n1)-
-V.sub.T and
V.sub.DS.sub._.sub.SAT.sub._.sub.M1=V.sub.GSM1-V.sub.T=V.sub.DD-V(n1)-V.s-
ub.T
In order to ensure that M1 and M2 are in the saturation region, the
equations above can be rewritten as:
V.sub.DD-V.sub.DDO>V.sub.DD-V(n1)-V.sub.T and
V.sub.DD-V(n3)>V.sub.DD-V(n1)-V.sub.T
Writing the saturation region equation for M.sub.2 and considering
I.sub.D2=I.sub.1 yields:
.times..times..times..times. ##EQU00006##
Further, writing the saturation region equation for M.sub.1
considering V.sub.GS1=V.sub.GS2 we obtain I.sub.D1:
.times..times..times..times..times..times. ##EQU00007##
Finally, combining both equations for transistors M.sub.1 and
M.sub.2 provides the following equation for I.sub.LIM:
.times..times..times..times. ##EQU00008##
In other words, when transistors M.sub.1 and M.sub.2 are in
saturation, the current provided to power domain 105B is limited to
I.sub.LIM. This current is a function of I.sub.1 as well as the
sizes of M2 and M1, and can be held constant.
Transistors M1 and M2 are in triode and linear regions when their
drain-to source voltages (V.sub.DS) are equal or below the
saturation V.sub.DS, that is
V.sub.DSM1<=.sub.VDS.sub._.sub.SAT.sub._.sub.M1 and
V.sub.DSM2<=V.sub.DS.sub._.sub.SAT.sub._.sub.M2. These
conditions yield:
V.sub.DD-V.sub.DDO<=V.sub.DD-V(n1)-V(n1)-V.sub.T and
V.sub.DD-V(n3)<=V.sub.DD-V(n1)-V.sub.T
From the equations above we deduct that V.sub.DSM3>=V.sub.T.
Hence, writing the I.sub.D2 equation in triode region results
in:
.times..times..times..times..times..times..times..times.
##EQU00009##
By circuit inspection is possible to see that:
V.sub.DS2+V.sub.GS3=V.sub.DS1+V.sub.GS4. Because:
V.sub.DS1=V.sub.DD-V.sub.DDO and
V.sub.GS3-V.sub.GS4=.DELTA.V.sub.GS34 it results that:
V.sub.DS2=V.sub.DS1-.DELTA.V.sub.GS34=V.sub.DD-V.sub.DDO-.DELTA.V.sub.GS3-
4
Accordingly,
.times..times..times..times..times..times. ##EQU00010##
.times..times..times..times..times..times..times..times..times..times.
##EQU00010.2##
As such, current I.sub.LIM, when M1 and M2 are in triode region,
depends on .DELTA.V.sub.GS34 voltage, I.sub.1 current, and
V.sub.DD-V.sub.DDO=V.sub.DS1. Looking into the above equations is
possible to notice that V.sub.DS2 has the -.DELTA.V.sub.GS34 term
when compared to V.sub.DS1. This way V.sub.DS2 will decrease more
than V.sub.DS1. Also considering that V.sub.GS2 is inversely
proportional to V.sub.DS2, the net effect is that while V.sub.DDO
approaches to V.sub.DD value, V.sub.DS1 decreases, V.sub.DS2
decreases more and V.sub.GS2 increases making I.sub.LIM also
increase.
V.sub.GS2 voltage will increase until reach its limit, in this case
current source I10 will have a decay from I.sub.1 value when node
n1 voltage is close to reference node 106 voltage (0 V) and also
because of reaching the limit V.sub.GS2=V.sub.DD. After this point,
as V.sub.DDO approaches V.sub.DD, only V.sub.DS1 decreases
(V.sub.DS1=V.sub.DD-V.sub.DDO) and therefore I.sub.LIM decreases.
Notice that it is possible to limit V.sub.GS2 voltage in other
ways, such as, for instance, by using a zener diode or the
like.
In sum, when V.sub.DD is greater than V.sub.DDO and transistor M2
is in saturation, transistors M1 and M2 act as a current mirror.
When the value of V.sub.DD is close to V.sub.DDO and M2 is in
triode, the value of the current limitation provided by transistor
M1 rises because (W.sub.4/L.sub.4)>(W.sub.3/L.sub.3). Moreover,
when V.sub.DD has approximately the same value as V.sub.DDO and M2
is in its linear region, M3 has less current capability than M4,
and node n1 is pulled down to reference node 106, and therefore
transistor M1, in this state, provides no current limitation.
To illustrate the foregoing, the graphs of FIG. 3 show aspects of
the operation of switching circuit 103 according to some
embodiments. Particularly, graph 301 shows the values of V.sub.DD
and V.sub.DDO change during a transition (e.g., power-up) period.
In this example, it may be noted that V.sub.DD voltage is constant
(1.2 V), whereas it takes V.sub.DDO approximately 20 .mu.s to reach
the same value as V.sub.DD. In some cases, the transition period
may last 30 .mu.s or less.
Graph 302 shows the various node voltages of n0, n1, and n2 as
V.sub.DDO changes over the course of the transition period, as well
as the V.sub.GS voltages for transistors M3 and M2. Meanwhile,
graph 303 shows the variations of current I.sub.LIM during the
transition. It may be noted that, while transistor M2 is in
saturation (between approximately 10 .mu.s and 22 .mu.s) and in
triode (between approximately 22 .mu.s and 29 .mu.s) modes, the
value of I.sub.LIM stays constant. When transistor M2 switches from
triode to linear modes (at approximately 29 .mu.s when V.sub.DDO
voltage is very close to V.sub.DD), the voltage at node n1 is
pulled to reference node 106 and the value of I.sub.LIM increases
before dropping to zero.
FIG. 4 is a circuit diagram of an example of switching circuit 103
with current limitation and zero Direct Current (DC) consumption.
In contrast with in FIG. 3, this embodiment adds PMOS transistors
M46, M47, M48, and M49, as well as inverter 401 and logic block
402. Transistor M48 has its source coupled to the source of
transistor M1 and its drain coupled to the gate of transistor M46.
Transistor M46 has its source coupled to the drain of transistor M1
and its drain coupled to node n2 and to current source I12.
Transistor M47 has its source coupled to the source of transistor
M3 and its drain coupled to node n1, to drain of M3 and to source
current I10.
In operation, transistor M46 is configured to operate as an
end-of-transition sensor. When an "on-off" signal is applied to
make transistor M48 non-conductive as the transition begins,
transistor M46 detects whether the difference between V.sub.DDO and
V.sub.DD is below a threshold level (this means V.sub.DDO is very
close to V.sub.DD), and provides a signal indicative of whether the
transition period has ended to inverter 401. Inverter 401 is in
turn coupled to logic circuitry 402, and is configured to receive
that indication and to turn off current sources I10, I11, and I12,
and make transistor M49 conductive in response to the transition
period having ended. As such, upon receiving the same "on-off"
signal as transistor M48, logic circuitry 403 is able to null
current consumption if switch 103 is stable, whether M1 is
conductive (that is, switch 103 is "on") or non-conductive (that
is, switch 103 is "off").
As explained above, after the transition period is complete,
transistor M1 is fully conductive and does not provide current
limitation. In this case, the current limitation feature may be
retriggered by making transistor M47 conductive and by turning on
current sources I10, I11, and I12, while making transistor M49
non-conductive. In this configuration, transistors M1 and M2 are
forced to a current mirror configuration and the current limitation
feature is active.
It should also be noted that, although the foregoing circuit
analysis has been done with MOS transistor equations for strong
inversion, the circuits described herein perform the same
operations with MOS transistors operating in moderate or weak
inversion regions. In this scenario, the current limitation has the
same value as in the strong inversion region, while transistors M1
and M2 are in saturation mode.
As a person of ordinary skill in the art will understand in light
of this disclosure, each of the various transistors discussed above
may itself represent a plurality of transistors in suitable
configurations (e.g., in parallel with each other). Moreover,
although the examples described above make use of PMOS transistors,
similar principles may be applied to design a power switch with
current limitation and zero DC consumption using NMOS
technologies.
FIG. 5 is a flowchart of method 500 for enabling power gating
techniques with smooth transition. In some embodiments, method 500
may be performed, at least in part, by switching circuit 103 shown
in FIGS. 1, 2, and 4. At block 501, method 500 includes setting
switching circuit 103 to provide a current limitation with a
maximum value of switch passing current, for example, by setting
the I.sub.FORCE signal shown in FIG. 4 to a low state and setting
the I.sub.1 current(s) to a maximum value (which increases the
resistance of switch 103 such that the amount of switch voltage
drop is slightly increased. Block 502 includes turning on second
regulator 102, at least in part, due to the reduced current flowing
through switching circuit 103. In some cases, pull down circuit
within second regulator 102 may be enabled so that, even when there
is no load condition, there is a finite voltage drop across
switching circuit 103, causing second regulator 102 to turn on.
At block 503, method 500 includes waiting a predetermined amount of
time for the output of second regulator 102 to settle and/or
detecting another change in the circuit. At block 504, method 500
includes increasing the current limitation imposed by switching
circuit 103, for example, by decreasing the I.sub.1 current(s)
and/or decreasing the size ratio of transistors M1/M2 (which
increases the resistance of switch 103). Block 505 includes again
waiting for the second regulator 102's output to settle.
Block 506 determines whether the maximum current limitation reached
its minimum value (or maximum resistance short of being completely
open) offered by switching circuit 103. If so, the switching
circuit 103 is opened at block 508 and block 509 turns off first
regulator 101. Otherwise, control returns to block 504 and the
current limitation of switching circuit 103 is increased
further.
In some cases, the output of the second regulator may be sensed and
evaluated at block 507, even when the maximum current limitation
(or minimum current value allowed to pass by switch 103) offered by
switching circuit 103 has not yet been reached. In those
situations, method 500 may end sooner--that is, before the maximum
current limitation has been reached--in response to the output of
second regulator 102 having met a preset voltage and/or current
value, in which case control passes to block 508.
FIG. 6 shows graphs illustrating methods for enabling power gating
techniques with smooth transition according to some embodiments.
Particularly, in graph 601, curve 602 shows an amount of current
limitation provided by switching circuit 103 over time, and curve
603 shows the current provided by second regulator 102 over time.
In graph 604, curve 605 shows the voltage applied to integrated
circuit 104 (or portions thereof) during a transition period when
first regulator 101 is turned off and second regulator 102 is
turned on.
It may be noted from FIG. 6 that point 606 is the instant when
switching circuit 103 begins to limit the current flowing through
it, and that limitation occurs in incremental steps up until point
608, when switching circuit 103 provides a maximum amount of
current limitation. After that point, first regulator 101 is turned
off. Point 607 shows the instant when second regulator 102 begins
to supply current. Prior to point 607, second regulator 102 was
turned on, but because the value of V.sub.DDO was above the
regulation point of second regulator 102, no current passed it. As
a result, curve 605 shows a well-behaved, smooth voltage variation
during the transition period (between points 606 and 608). In the
absence of switching circuit 103 with current limitation, curve 103
would include an impulse response due to a sudden change in supply
voltage (from approximately 1.35 V to approximately 1.28 V).
To illustrate curve 608 further, table I below shows an example of
a range of 4-bit words that logic circuit 402 may use in order to
control the current limitation and/or resistance presented by
switching circuit 103:
TABLE-US-00001 TABLE I bit 3 bit 2 bit 1 bit 0 I.sub.LIM (mA) 0 0 0
0 62.1 0 0 0 1 56.6 0 0 1 0 51.0 0 0 1 1 45.5 0 1 0 0 40.0 0 1 0 1
34.5 0 1 1 0 29.0 0 1 1 1 23.4 1 0 0 0 20.7 1 0 0 1 17.9 1 0 1 0
15.2 1 0 1 1 12.4 1 1 0 0 9.7 1 1 0 1 6.9 1 1 1 0 4.1 1 1 1 1
1.4
As described herein, in an illustrative, non-limiting embodiment,
an electronic device may include an integrated circuit including a
plurality of power domains; a first voltage regulator coupled to a
given one of the plurality of power domains; a second voltage
regulator coupled to the given one of the plurality of power
domains; and a switching circuit coupled between the first power
regulator and the second power regulator, the switching circuit
configured to control an amount of current drawn by the given one
of the plurality of power domains from at least one of the first or
second voltage regulators during a transition period.
The transition period may include a turning off of the first
voltage regulator and a turning on of the second voltage regulator.
The first voltage regulator may be configured to enable operation
of at least a portion of the integrated circuit in a first power
mode, the second voltage regulator may be configured to enable
operation of the at least one portion of the integrated circuit in
a second power mode, and the first power mode may provide more
current than the second power mode. In some implementations, the
integrated circuit, the second voltage regulator, and the switching
circuit may be within a same electronic package, and the first
voltage regulator may be external to the electronic package.
The electronic device may further include a logic circuit coupled
to the switching circuit, the logic circuit configured to gradually
change the amount of current in discrete time intervals during the
transition period. The logic circuit may be further configured to
reduce the amount of current from a first value to a second value,
wait until an output of the second voltage regulator has settled,
and reduce the amount of current from the second value to a third
value, where a difference between the first and second values is
equal to a difference between the second and third values.
Additionally or alternatively, the logic circuit may be further
configured to decrease the amount of current until a minimum
predetermined amount of current is reached. Additionally or
alternatively, the logic circuit is further configured to decrease
the amount of current until the second voltage regulator outputs a
predetermined voltage level or a predetermined amount of
current.
In some implementations, the switching circuit may include a first
current mirror including a first transistor and a second
transistor, the first transistor including a first current terminal
coupled to an output of the first voltage regulator, the first
transistor including a second current terminal coupled to the
second voltage regulator, the second transistor including a first
current terminal coupled to the first current terminal of the first
transistor, and the second transistor including a control terminal
coupled to a control terminal of the first transistor. The
switching circuit may also include a second current mirror
including a third transistor and a fourth transistor, the third
transistor including a first current terminal coupled to a second
current terminal of the second transistor, the third transistor
including a second current terminal coupled to a first current
source and to the control terminals of the first and second
transistors, the fourth transistor including a first current
terminal coupled to the second current terminal of the first
transistor, the fourth transistor including a second current
terminal coupled to a second current source, and the fourth
transistor including a control terminal coupled to a control
terminal of the third transistor and to the second current terminal
of the fourth transistor.
In some cases, the amount of current may be proportional to an
aspect ratio of the first transistor divided by an aspect ratio of
the second transistor. Also, an aspect ratio of the fourth
transistor may be greater than an aspect ratio of the third
transistor.
In another illustrative, non-limiting embodiment, a method may
include controlling an impedance of a switching circuit to change
an amount of current flowing through the switching circuit, wherein
the switching circuit is coupled to a given one of a plurality of
power domains of an integrated circuit, wherein the integrated
circuit is configured to operate in a first mode followed by a
second mode such that a transition period occurs between the first
and second modes, wherein the switching circuit is coupled to a
first regulator and to a second regulator, wherein the first
regulator is configured to provide more power to the integrated
circuit than the second regulator, and wherein the transition
period includes a turning off of the first voltage regulator and a
turning on of the second voltage regulator.
The method may further include decoupling the switching circuit
from a ground node in response to a determination that the
transition period has ended. Controlling the amount of current may
include decreasing the amount of current until a minimum
predetermined amount of current is reached. Additionally or
alternatively, controlling the amount of current may include
decreasing the amount of current until the second voltage regulator
outputs a predetermined voltage or a predetermined current.
Additionally or alternatively, controlling the amount of current
may include gradually changing a resistance presented by the
switching circuit in discrete time intervals during the transition
period. In some cases, Gradually changing the resistance may
include reducing the amount of current from a first value to a
second value, waiting until an output of the second voltage
regulator settles, and reducing the amount of current from the
second value to a third value.
In yet another illustrative, non-limiting embodiment, an integrated
circuit may include switching circuitry coupled between a first
voltage regulator and a second voltage regulator, the first and
second voltage regulators configured to provide power to an
integrated circuit, and the switching circuitry configured to
impose gradually increasing limits upon an amount of current drawn
by the integrated circuit from the first voltage regulator during a
transition period. The transition period may include a turning off
of the first voltage regulator and a turning on of the second
voltage regulator, and the switching circuitry may be further
configured to consume zero Direct Current (DC) power outside of the
transition period.
In many implementations, the systems and methods disclosed herein
may be incorporated into a wide range of electronic devices
including, for example, computer systems or Information Technology
(IT) products such as servers, desktops, laptops, memories,
switches, routers, etc.; telecommunications hardware; consumer
devices or appliances such as mobile phones, tablets, television
sets, cameras, sound systems, etc.; scientific instrumentation;
industrial robotics; medical or laboratory electronics such as
imaging, diagnostic, or therapeutic equipment, etc.; transportation
vehicles such as automobiles, buses, trucks, trains, watercraft,
aircraft, etc.; military equipment, etc. More generally, these
systems and methods may be incorporated into any device or system
having one or more electronic parts or components.
Turning to FIG. 7, a block diagram of electronic system 700 is
depicted. In some embodiments, electronic system 700 may be include
of the aforementioned electronic devices, or any other electronic
device. As illustrated, electronic system 700 includes one or more
Printed Circuit Boards (PCBs) 701, and at least one of PCBs 701
includes one or more microelectronic device packages(s) 702. In
some implementations, device package(s) 702 may include one or more
circuits for enabling power gating techniques with smooth
transition as discussed above.
Examples of device package(s) 702 may include, for instance, a
System-On-Chip (SoC), an Application Specific Integrated Circuit
(ASIC), a Digital Signal Processor (DSP), a Field-Programmable Gate
Array (FPGA), a processor, a microprocessor, a controller, a
microcontroller (MCU), a Graphics Processing Unit (GPU), or the
like. Additionally or alternatively, device package(s) 502 may
include a memory circuit or device such as, for example, a Random
Access Memory (RAM), a Static RAM (SRAM), a Magnetoresistive RAM
(MRAM), a Nonvolatile RAM (NVRAM, such as "FLASH" memory, etc.),
and/or a Dynamic RAM (DRAM) such as Synchronous DRAM (SDRAM), a
Double Data Rate RAM, an Erasable Programmable ROM (EPROM), an
Electrically Erasable Programmable ROM (EEPROM), etc. Additionally
or alternatively, device package(s) 702 may include one or more
mixed-signal or analog circuits, such as, for example,
Analog-to-Digital Converter (ADCs), Digital-to-Analog Converter
(DACs), Phased Locked Loop (PLLs), oscillators, filters,
amplifiers, etc. Additionally or alternatively, device package(s)
702 may include one or more Micro-ElectroMechanical Systems (MEMS),
Nano-ElectroMechanical Systems (NEMS), or the like.
Generally speaking, device package(s) 702 may be configured to be
mounted onto PCB 701 using any suitable packaging technology such
as, for example, Ball Grid Array (BGA) packaging or the like. In
some applications, PCB 701 may be mechanically mounted within or
fastened onto electronic device 700. It should be noted that, in
certain implementations, PCB 701 may take a variety of forms and/or
may include a plurality of other elements or components in addition
to device package(s) 702. It should also be noted that, in some
embodiments, PCB 701 may not be used and/or device package(s) 702
may assume any other suitable form(s).
Although the invention(s) is/are described herein with reference to
specific embodiments, various modifications and changes can be made
without departing from the scope of the present invention(s), as
set forth in the claims below. Accordingly, the specification and
figures are to be regarded in an illustrative rather than a
restrictive sense, and all such modifications are intended to be
included within the scope of the present invention(s). Any
benefits, advantages, or solutions to problems that are described
herein with regard to specific embodiments are not intended to be
construed as a critical, required, or essential feature or element
of any or all the claims.
Unless stated otherwise, terms such as "first" and "second" are
used to arbitrarily distinguish between the elements such terms
describe. Thus, these terms are not necessarily intended to
indicate temporal or other prioritization of such elements. The
terms "coupled" or "operably coupled" are defined as connected,
although not necessarily directly, and not necessarily
mechanically. The terms "a" and "an" are defined as one or more
unless stated otherwise. The terms "comprise" (and any form of
comprise, such as "comprises" and "comprising"), "have" (and any
form of have, such as "has" and "having"), "include" (and any form
of include, such as "includes" and "including") and "contain" (and
any form of contain, such as "contains" and "containing") are
open-ended linking verbs. As a result, a system, device, or
apparatus that "comprises," "has," "includes" or "contains" one or
more elements possesses those one or more elements but is not
limited to possessing only those one or more elements. Similarly, a
method or process that "comprises," "has," "includes" or "contains"
one or more operations possesses those one or more operations but
is not limited to possessing only those one or more operations.
* * * * *