U.S. patent number 9,348,355 [Application Number 12/862,298] was granted by the patent office on 2016-05-24 for display link clocking method and apparatus.
This patent grant is currently assigned to ATI Technologies ULC. The grantee listed for this patent is Collis Quinn Carter, Ngar Sze Nancy Chan, Michael Foxcroft, David I. J. Glen, Natan Shtutman. Invention is credited to Collis Quinn Carter, Ngar Sze Nancy Chan, Michael Foxcroft, David I. J. Glen, Natan Shtutman.
United States Patent |
9,348,355 |
Glen , et al. |
May 24, 2016 |
Display link clocking method and apparatus
Abstract
An apparatus includes a clock circuit and a plurality of display
interface circuits. The clock circuit provides a common clock
signal. The display interface circuits each provide a respective
display link clock signal in response to the common clock signal.
One of the display link clock signals is at a different clock speed
that another of the display link clock signals.
Inventors: |
Glen; David I. J. (Toronto,
CA), Carter; Collis Quinn (Richmond Hill,
CA), Shtutman; Natan (Richmond Hill, CA),
Chan; Ngar Sze Nancy (Markham, CA), Foxcroft;
Michael (Toronto, CA) |
Applicant: |
Name |
City |
State |
Country |
Type |
Glen; David I. J.
Carter; Collis Quinn
Shtutman; Natan
Chan; Ngar Sze Nancy
Foxcroft; Michael |
Toronto
Richmond Hill
Richmond Hill
Markham
Toronto |
N/A
N/A
N/A
N/A
N/A |
CA
CA
CA
CA
CA |
|
|
Assignee: |
ATI Technologies ULC (Markham,
Ontario, CA)
|
Family
ID: |
43623934 |
Appl.
No.: |
12/862,298 |
Filed: |
August 24, 2010 |
Prior Publication Data
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Document
Identifier |
Publication Date |
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US 20110050314 A1 |
Mar 3, 2011 |
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Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
Issue Date |
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61236444 |
Aug 24, 2009 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
G09G
5/006 (20130101); G06F 1/06 (20130101) |
Current International
Class: |
G09G
5/00 (20060101); G06F 1/06 (20060101) |
Field of
Search: |
;345/204-215,690-699 |
References Cited
[Referenced By]
U.S. Patent Documents
Primary Examiner: Chang; Kent
Assistant Examiner: Lu; William
Attorney, Agent or Firm: Faegre Baker Daniels LLP
Parent Case Text
CROSS-REFERENCE TO RELATED APPLICATION
This application claims priority to the provisional patent
application having Application No. 61/236,444, filed Aug. 24, 2009,
having inventors Quinn Carter et al., titled "DISPLAY LINK CLOCKING
METHOD AND APPARATUS" and owned by instant assignee. This
application is related to application, filed on even date, having
inventors David Glen et al., titled "PIXEL CLOCKING METHOD AND
APPARATUS", owned by instant assignee, which claims priority to
provisional patent application having Application No. 61/236,446,
filed Aug. 24, 2009, having inventors David Glen et al., titled
"PIXEL CLOCKING METHOD AND APPARATUS" and owned by instant
assignee.
Claims
What is claimed is:
1. An apparatus comprising: a clock circuit that is operative to
provide a common clock signal synthesized from a reference clock
signal; and a plurality of display interface circuits that are
operative to provide a plurality of respective display link clock
signals in response to the common clock signal, wherein a first of
the plurality of display link clock signals is at a different clock
speed than the common clock signal while a second of the plurality
of display link clock signals is simultaneously at a different
clock speed than both the first of the plurality of display link
clock signals and the common clock signal, wherein the clock speeds
of the first and second of the plurality of display link clock
signals are adjusted in response to display configuration
information from each of a first and a second of a plurality of
displays respectively for simultaneously driving the first and the
second of the plurality of displays respectively.
2. The apparatus of claim 1 wherein each of the plurality of
display interface circuits comprises a clock signal adjuster
circuit that is operative to provide the display link clock signal
by selectively scaling the common clock signal.
3. The apparatus of claim 1 further comprising a display interface
link rate control circuit that is operative to control the clock
signal adjuster circuit to scale the common clock signal based on
the display configuration information from each of the first and
the second of the plurality of displays respectively.
4. The apparatus of claim 1 wherein each respective link clock
signal is operative to drive a respective display link.
5. The apparatus of claim 1 wherein each of the first and the
second of the plurality of displays operate using different timing
schemes.
6. The apparatus of claim 1 wherein the common clock signal is
scaled to have the respective clock speed that matches a link clock
speed of the respective device in response to the display
configuration information.
7. The apparatus of claim 1 wherein the display configuration
information includes at least one of a type and make information of
the respective display.
8. A method comprising: providing a common clock signal synthesized
from a reference clock signal; providing a plurality of display
link clock signals in response to the common clock signal, wherein
a first of the plurality of display link clock signals is at a
different clock speed than the common clock signal while a second
of the plurality of display link clock signals is simultaneously at
a different clock speed than both the first of the plurality of
display link clock signals and the common clock signal, wherein the
clock speeds of the first and second of the plurality of display
link clock signals are adjusted in response to display
configuration information from each of a first and a second of a
plurality of displays respectively for simultaneously driving the
first and the second of the plurality of displays respectively.
9. The method of claim 8 wherein providing the plurality of display
link clock signals comprises selectively scaling the common clock
signal.
10. The method of claim 9 selectively scaling the common clock
signal is based on the display configuration information from each
of the first and the second of the plurality of displays
respectively.
11. A non-transitory computer readable medium comprising
information that when executed by at least one processor causes the
at least one processor to layout an integrated circuit that
comprises: a clock circuit that is operative to provide a common
clock signal synthesized from a reference clock signal; and a
plurality of display interface circuits that are operative to
provide a plurality of respective link clock signals in response to
the common clock signal, wherein a first of the plurality of link
clock signals is at a different clock speed than the common clock
signal while a second of the plurality of link clock signals is
simultaneously at a different clock speed than both the first of
the plurality of link clock signals and the common clock signal,
wherein the clock speeds of the first and second of the plurality
of link clock signals are adjusted in response to display
configuration information from each of a first and a second of a
plurality of displays respectively for simultaneously driving the
first and the second of the plurality of displays respectively.
12. The computer readable medium of claim 11 wherein each of the
plurality of display interface circuits comprises a clock signal
adjuster circuit that is operative to provide the link clock signal
by selectively scaling the common clock signal.
13. The computer readable medium of claim 11 further comprising a
display interface link rate control circuit that is operative to
control the clock signal adjuster circuit to scale the common clock
signal based on the display configuration information from each of
the first and the second of the plurality of displays
respectively.
14. The computer readable medium of claim 11 wherein the display
configuration information includes at least one of a type and make
information of the respective display.
15. The computer readable medium of claim 11 wherein the
information comprises hardware description language.
16. The computer readable medium of claim 11 wherein each of the
first and the second of the plurality of displays operate using
different timing schemes.
17. The method of claim 8 wherein each of the first and the second
of the plurality of displays operate using different timing
schemes.
18. The method of claim 8 wherein the display configuration
information includes at least one of a type and make information of
the respective display.
19. The method of claim 11 wherein the display configuration
information includes at least one of a type and make information of
the respective display.
Description
FIELD
The present disclosure generally relates to display link clocking
methods and apparatus, and more particularly, to methods and
apparatus for providing multiple display link clocking signals for
multiple displays.
BACKGROUND
Traditional display interfaces such as VGA, DVI, HDMI, LVDS require
a dedicated clock generation circuit for each simultaneously active
output connected to a source device such as a PC or GPU. The
relatively high cost of implementing several of these clock source
circuits has been one factor that has limited the total number of
simultaneous displays that could be driven at a time by a single
GPU.
It is known to drive multiple displays at a time with a shared
clock synthesis circuit using a reference clock such as a crystal,
only if all these displays use the exact same timing (e.g.,
resolution, refresh rate and pixel clock rate). However, in many
applications, the multiple displays may not have the same exact
timing. For example, a consumer may have one type of display that
operates using one timing scheme and another display that operates
at a different timing scheme. In this example, the two monitors
could not be driven using a shared clock synthesis circuit because
they both don't have the exact same timing scheme. Therefore, in
this example, a dedicated clock generation circuit is required for
each of the displays.
Accordingly, a need exists for a method and apparatus that requires
less clock source circuits than known source devices and has the
capability drive multiple displays that operate using different
timing schemes.
BRIEF DESCRIPTION OF THE DRAWINGS
The invention will be more readily understood in view of the
following description when accompanied by the below figures,
wherein like reference numerals represent like elements:
FIG. 1 is an exemplary depiction of a device including an apparatus
according to the present disclosure;
FIG. 2 is an exemplary functional block diagram of a virtual pixel
clock circuit included in the apparatus;
FIG. 3 is a flowchart depicting exemplary operations that can be
performed by the apparatus to provide multiple display link clock
signals at one or more different clock speeds; and
FIG. 4 is a flowchart depicting exemplary operations that can be
performed by the apparatus to provide multiple pixel clock signals
at one or more different clock speeds.
DETAILED DESCRIPTION
In one example, an apparatus includes a display link clock circuit
and a plurality of display interface circuits. The phase lock loop
circuit provides a common display link clock signal. The display
interface circuits each provide a respective display link clock
signal in response to the common display link clock signal. One of
the display link clock signals is at a different clock speed than
another of the display link clock signals. In another example, the
apparatus includes a pixel phase lock loop circuit and a virtual
pixel clock circuit. The pixel phase lock loop circuit provides a
common pixel clock signal. The virtual pixel clock circuit provides
a plurality of pixel clock signals in response to the common pixel
clock signal. One of the virtual pixel clock signals is at a
different clock speed than another of the virtual pixel clock
signals. A related method is also disclosed.
The method and apparatus provide, among other advantages, a reduced
number of phase lock loop circuits required to drive multiple
displays having various timing characteristics. Reducing the number
of required phase lock loop circuits in the apparatus
advantageously reduces the size and cost of the apparatus. In
addition, power consumption is also reduced due to the reduced
number of clock circuits. Other advantages will be recognized by
those of ordinary skill in the art.
In one example, each of the display interface circuits include a
clock signal adjuster circuit. The clock signal adjuster circuit
provides the display link clock signal by selectively scaling the
common display link clock signal.
In one example, the apparatus includes a display interface link
rate control circuit. The display interface link rate control
circuit controls the clock signal adjuster circuit to scale the
common display link clock signal based on display identification
information associated with a display. In one example, each
respective display link clock signal drives a respective
display.
In one example, the virtual pixel clock circuit includes a
plurality of discrete time oscillator circuits. Each of the
discrete time oscillator circuits provide a respective one of the
plurality of virtual pixel clock signals in response to the common
pixel clock signal. In one example, each of the plurality of
discrete time oscillator circuits selectively adjusts a respective
one of the virtual pixel clock signals to one of a higher and lower
clock speed based on display configuration information.
In one example, the virtual pixel circuit includes a discrete time
oscillator control circuit. The discrete time oscillator control
circuit selectively adjusts a scaling factor each of the plurality
of discrete time oscillator circuits in response to display
configuration information.
In one example, the apparatus includes a plurality of display
control circuits. Each of the video display controllers are
responsive to a respective one of the virtual pixel clock signals.
In one example, each of the virtual pixel clock signals drive a
respective display. As such, a plurality of displays each present
an image in response to a respective one of the plurality of pixel
clock signals.
In one example, computer readable medium includes information that
when executed by a processor causes the to layout an integrated
circuit that comprises the apparatus. In one example, the
information comprises hardware description language.
The following description of the embodiments is merely exemplary in
nature and is in no way intended to limit the invention, its
application, or uses. For purposes of clarity, the same reference
numbers will be used in the drawings to identify similar
elements.
As used herein, the term "apparatus," "circuit," and/or "device"
can include an electronic circuit, one or more processors (e.g.,
shared, dedicated, or group of processors such as but not limited
to microprocessors, DSPs, or central processing units) and memory
that execute one or more software or firmware programs,
combinational logic circuits, an ASIC, and/or other suitable
components that provide the described functionality. Additionally,
the term "signal" may refer to one or more currents, one or more
voltages, or a data signal. Furthermore, as will be appreciated by
those of ordinary skill in the art, the layout of a "apparatus,"
"circuit," and/or "device" can be described and laid out in a
hardware description language such as Verilog.TM., VHDL, and/or
other suitable hardware description languages.
Referring now to FIG. 1, an exemplary functional block diagram of a
device 100 such as a wireless phone, a mobile and/or stationary
computer, a printer, a LAN interface (wireless and/or wired), a
media player, a video decoder and/or encoder, and/or any other
suitable device is depicted. The device 100 includes a processor
circuit 102, a bridge circuit 104, a memory circuit 106, a graphics
processor circuit 108, and a plurality of displays 110. Although
referred to as a graphics processor circuit in this example,
skilled artisans will appreciate that the graphics processor
circuit 108 can process video information in addition to graphics
information. In addition, in some embodiments, the displays 110 may
be external to the device 100 if desired.
Although not depicted, in some embodiments, there may be six
displays 110 aligned in a rectangular arrangement having three
columns and two rows. As such, in this example, each of the
displays 110 can present 1/6 of a frame so that the combination of
all the displays 110 present the entire frame. Although six
displays 110 are discussed in this example, it is contemplated that
any number of displays 110 can be included and arranged as
desired.
The processor circuit 102 is operatively coupled to the bridge
circuit 104 and processes requests passed to/from the bridge
circuit 104. The memory circuit 106 stores information communicated
from the bridge circuit 104. The bridge circuit 104 communicates
image information 112 from processor circuit 102 or memory to the
graphics processor circuit 108, which processes the information for
presentation on the displays 110 as known in the art.
The graphics processor circuit 108 can include an image processor
circuit 114, a plurality of display control circuits 116 (e.g.,
CRTC or other suitable display controller), a plurality of display
interface circuits 118 (e.g., PHY), a display link clock circuit
120 such as a phase lock loop or other suitable clock circuit, a
display interface link rate control circuit 122, a virtual pixel
clock circuit 124, and a pixel clock circuit 126 such as a phase
lock loop or other suitable clock circuit configured substantially
as shown. As known in the art, phase lock loops and other clock
circuits synthesize a reference clock to produce an output
clock.
The image processor circuit 114 provides processed image
information 129 to the display controller circuits 116 in response
to the image information 112. In response to the processed image
information 129, the display controller circuits 116 control the
displays 110 to present an image based on the image information 112
by communicating image information 119 to the display information
circuit. As noted above, in some embodiments, each display 110 can
present a portion of a frame so that the entire frame is presented
by a combination of all of the displays 110.
The display link clock circuit 120 provides a common display link
clock signal 130 in order to provide a respective link clock signal
132 to each of the displays 110. In one example, the common display
clock speed can be 540 MHz, however other clock speeds are
contemplated. The link clock signal 132 provides clocking for the
communication link between the display interface circuit 118 and
the display 110.
Each of the display interface circuits 118 include a respective
clock adjuster circuit 134. In one example, the clock adjuster
circuit 134 can be a clock multiplier circuit that converts the
common display link clock signal 130 into the link clock signals
132 having a speed of 1.62, 2.7, 5.4 Gbps and/or other suitable
clock speed.
Each of the clock adjuster circuits 134 selectively scales the
common display link clock signal 130 to provide a respective one of
the link clock signals 132. In one embodiment, one or more of the
link clock signals 132 can be at a different clock speed than the
others. For example, if one of the displays 110 operates using a
first link clock speed while another of the displays 110 operates
using a second link clock speed that is different than the first
link clock speed, the clock adjustor circuit 134 of the display
interface circuit 132 associated with display 110 at the first link
clock speed can scale the common display link clock signal 130 so
that the respective link clock signal 132 is at the first link
clock speed. Likewise, the clock adjustor circuit 134 of the
display interface circuit 132 associated with display 110 at the
second link clock speed can scale the common display link clock
signal 130 so that the respective link clock signal 132 is at the
second link clock speed. As such, it is possible to provide a
different link clock speed for one or more of the displays 110 that
is based on the common display link clock signal 130.
The display interface link rate control circuit 122 controls each
of the clock adjuster circuits 134 via a respective link rate
control signal 136. More specifically, the display interface
circuits 118 each receive display configuration information 138
from a respective display 110. The display configuration
information 138 can include information regarding the configuration
of the respective display 110. Exemplary information that can be
included in the display configuration information 138 includes
display link rate information, pixel clock rate information,
monitor type and/or make information, and/or other suitable
information used to described operating characteristics of the
displays 110. In one example, the display configuration information
138 can include information as described in the Display Data
Channel (DDC) standard, which is incorporated herein by reference
in its entirety; Extended Display Identification Data (EDID)
standard, which is incorporated herein by reference in its
entirety; and/or other suitable standard.
The display configuration information 138 is provided to the
display interface link rate control circuit 122 from the display
interface circuit 118. In response to the display configuration
information 138, the display interface link rate control circuit
122 selectively controls the respective displays 110 via the link
rate control signals 136 based on the display configuration
information 138. For example, if one of the displays 110 operates
using a first link clock speed while another of the displays 110
operates using a second link clock speed that is different than the
first link clock speed, the display interface link rate control
circuit 122 controls the clock adjustor circuit 134 of the display
interface circuit 132 associated with display 110 at the first link
clock speed to scale the common display link clock signal 130 so
that the respective link clock signal 132 is at the first link
clock speed. Likewise, display interface link rate control circuit
122 controls the clock adjustor circuit 134 of the display
interface circuit 132 associated with display 110 at the second
link clock speed to scale the common display link clock signal 130
so that the respective link clock signal 132 is at the second link
clock speed. As such, each link clock signal 132 can drive a
respective one of the displays 110 using a respective link clock
speed.
The pixel clock circuit 126 provides a common pixel clock signal
140. In response to the common pixel clock signal 140, the virtual
pixel clock circuit 124 provides a plurality of virtual pixel clock
signals 142 to a respective one of the display control circuits
116. In response thereto, each of the display control circuits 116
divides lines of respective processed image information 129 into
pixels. The higher the frequency of each of the virtual pixel clock
signals 142, the more pixels appear on a respective display 110.
Additionally, the virtual pixel clock signals 142 are rather stable
and exhibit a negligible amount of jitter.
One or more of the virtual pixel clock signals 142 can be at a
different clock speed in order to drive different models or types
of displays. For example, if one of the displays 110 operates using
a first pixel clock speed while another of the displays 110
operates using a second pixel clock speed that is different than
the first link clock speed, the virtual pixel clock circuit 124 can
provide the virtual pixel clock signal 142 at the first pixel clock
speed to the display control circuit 116 associated with display
110 that operates at the first pixel clock speed. Likewise, the
virtual pixel clock circuit 124 can provide the virtual pixel clock
signal 142 at the second pixel clock speed to the display control
circuit 116 associated with the display 110 that operates at the
second pixel clock speed. As such, virtual pixel clock circuit 124
can provide a different pixel clock speed for one or more of the
displays 110 that is based on the common pixel clock signal
140.
More specifically, the virtual pixel clock circuit 124 selectively
provides each of the virtual pixel clock signals 142 at various
clock speeds based on the display configuration information 138. As
noted above, the display configuration information 138 can include
information regarding the configuration of the respective display
110. Exemplary information that can be included in the display
configuration information 138 can include display link rate
information, pixel clock rate information, monitor type, and/or
other suitable information used to described operating
characteristics of the displays 110. Accordingly, each virtual
pixel clock signal 142 can drive a respective one of the displays
110 using a different pixel clock speed.
Referring now also to FIG. 2, an exemplary functional block diagram
of the virtual pixel clock circuit 124 is depicted. The virtual
pixel clock circuit 124 includes a plurality of discrete time
oscillator circuits 200 and a discrete time oscillator control
circuit 202. The discrete time oscillator circuits 200 can be any
suitable circuit that uses a programmable numerator and denominator
(or ratio) and is responsive to an input clock such as the common
pixel clock signal 140. The numerator and denominator (or ratio)
are set to produce a desired clock rate for the virtual pixel clock
signal 142 based on the common pixel clock signal 140. For example,
if the common pixel clock signal 140 is at 27 MHz and pixel clock
rate of 48 kHz is desired, then the ratio can be set to
48,000/27,000,000=2/1125. As such, in this example, the discrete
time oscillator circuits 200 produce a pulse 2 times for every 1125
cycles of the common pixel clock signal 140. Accordingly, each of
the discrete time oscillator circuits 200 provide a respective one
of the virtual pixel clock signals 142 based on the common pixel
clock signal 140.
The discrete time oscillator control circuit 202 selectively
adjusts the ratio (or scaling factor) of each of the discrete time
oscillator circuits 200 via respective discrete time oscillator
control signals 204 in response to respective display configuration
information 138. For example, if one of the displays 110 operates
using a first pixel clock speed while another of the displays 110
operates using a second pixel clock speed that is different than
the first link clock speed, the discrete time oscillator control
circuit 202 controls a respective one of the discrete time
oscillator circuits 200 to provide the virtual pixel clock signal
142 at the first pixel clock speed to the display control circuit
116 associated with display 110 that operates at the first pixel
clock speed. Likewise, the discrete time oscillator control circuit
202 controls a respective one of the discrete time oscillator
circuits 200 to provide the virtual pixel clock signal 142 at the
second pixel clock speed to the display control circuit 116
associated with the display 110 that operates at the second pixel
clock speed. As such, each of the discrete time oscillator circuits
200 selectively adjusts a respective one of the virtual pixel clock
signals 142 based on the display configuration information 138 in
order to provide a different pixel clock speed for one or more of
the displays 110.
Referring now to FIG. 3, exemplary operations that can be performed
to provide the link clock signals 132 having different clock speeds
are generally identified at 300. The process starts at 302. At 304,
the display link clock circuit 120 provides the common display link
clock signal 130. At 306, the clock adjuster circuits 134 provide
the link clock signals 132 in response to the common display link
clock signal 130. More specifically, each of the clock adjuster
circuits 134 provide a respective one of the link clock signal 132
in response to the common display link clock signal 130 such that
at least one of the respective link clock signals 132 is at a
different clock speed than another of the respective link clock
signals 132. As such, one or more of the display interface circuits
118 can drive a respective display 110 using a different link clock
speed than another of the display interface circuits 118.
Therefore, displays requiring different display link clock speeds
can be driven simultaneously using a single display link clock
circuit. The process ends at 308.
Referring now to FIG. 4, exemplary operations that can be performed
to provide the virtual pixel clock signals 142 having different
clock speeds are generally identified at 400. The process starts at
402. At 404, the pixel clock circuit 126 provides the common pixel
clock signal 140. At 406, the virtual pixel clock circuit 124
provides the virtual pixel clock signals 142 in response to the
common pixel clock signal 140. More specifically, the virtual pixel
clock circuit 124 provides each of the virtual pixel clock signals
142 such that at least one of the virtual pixel clock signals 142
is at a different clock speed than another of the virtual pixel
clock signals 142. As such, one or more of the display control
circuits 116 can drive a respective display 110 using a different
pixel clock speed than another of the display control circuits 116.
Therefore, displays requiring different pixel clock speeds can be
driven simultaneously using a single pixel clock circuit. The
process end at 408.
As noted above, among other advantages, the method and apparatus
provide a reduced number of clock circuits required to drive
multiple displays having various timing characteristics. Reducing
the number of required clock circuits in the apparatus
advantageously reduces the size and cost of the apparatus. In
addition, power consumption is also reduced due to the reduced
number of clock circuits. Other advantages will be recognized by
those of ordinary skill in the art.
Although the disclosure is described herein with reference to
specific embodiments, various modifications and changes can be made
without departing from the scope of the present disclosure as set
forth in the claims below. Accordingly, the specification and
figures are to be regarded in an illustrative rather than a
restrictive sense, and all such modifications are intended to be
included within the scope of the present disclosure. Any benefits,
advantages, or solutions to problems that are described herein with
regard to specific embodiments are not intended to be construed as
a critical, required, or essential feature or element of any or all
the claims. In addition, unless stated otherwise, terms such as
"first" and "second" are used to arbitrarily distinguish between
the elements such terms describe. Thus, these terms are not
necessarily intended to indicate temporal or other prioritization
of such elements. The term coupled, as used herein, is defined as
connected, although not necessarily directly, and not necessarily
mechanically. As used herein, the terms "comprises," "comprising,"
or any other variation thereof, are intended to cover a
non-exclusive inclusion, such that a process, method, article, or
apparatus that comprises a list of elements does not include only
those elements but may include other elements not expressly listed
or inherent to such process, method, article, or apparatus. The
terms a or an, as used herein, are defined as one or more than
one.
* * * * *