U.S. patent number 8,907,833 [Application Number 13/859,008] was granted by the patent office on 2014-12-09 for low power high speed pipeline adc.
This patent grant is currently assigned to Marvell International Ltd.. The grantee listed for this patent is Marvell International Ltd.. Invention is credited to Song Chen, Jie Jiang, Tao Shui, Yonghua Song, Hao Zhou.
United States Patent |
8,907,833 |
Zhou , et al. |
December 9, 2014 |
Low power high speed pipeline ADC
Abstract
In accordance with the teachings described herein, systems and
methods are provided for a time-interleaved pipeline analog to
digital converter. An example pipeline analog to digital converter
may include passive sampling circuits and a multiplying digital to
analog converter circuit. A first passive sampling circuit includes
an input terminal coupled to an analog input signal, and outputs a
first sample voltage that is responsive to the analog input signal.
A second passive sampling circuit includes an input terminal
coupled to the analog input signal, and outputs a second sample
voltage that is responsive to the analog input signal. The first
and second passive sampling circuits are clocked such that the
first sample voltage and the second sample voltage are
time-interleaved. A multiplying analog to digital converter (MDAC)
circuit receives the time-interleaved first and second sample
voltages from the first and second passive sampling circuits and
processes the time-interleaved first and second sample voltages to
generate a residue output voltage.
Inventors: |
Zhou; Hao (Shanghai,
CN), Song; Yonghua (Cupertino, CA), Shui; Tao
(San Jose, CA), Jiang; Jie (Shanghai, CN), Chen;
Song (Shanghai, CN) |
Applicant: |
Name |
City |
State |
Country |
Type |
Marvell International Ltd. |
Hamilton |
N/A |
BM |
|
|
Assignee: |
Marvell International Ltd.
(Hamilton, BM)
|
Family
ID: |
48445337 |
Appl.
No.: |
13/859,008 |
Filed: |
April 9, 2013 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
Issue Date |
|
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13109320 |
May 17, 2011 |
8451160 |
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61345444 |
May 17, 2010 |
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Current U.S.
Class: |
341/161;
341/155 |
Current CPC
Class: |
H03M
1/124 (20130101); H03M 1/002 (20130101); H03M
1/1215 (20130101); H03M 1/167 (20130101) |
Current International
Class: |
H03M
1/38 (20060101) |
Field of
Search: |
;341/155,161,159 |
References Cited
[Referenced By]
U.S. Patent Documents
Primary Examiner: Young; Brian
Parent Case Text
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is a continuation of U.S. patent application Ser.
No. 13/109,320, filed on May 17, 2011, which claims priority from
U.S. Provisional Patent Application No. 61/345,444, filed on May
17, 2010, and entitled "New Low Power High Speed Pipeline ADC," the
entirety of which is incorporated herein by reference.
Claims
What is claimed is:
1. An electronic device comprising: a first sampling circuit
configured to, on a repeating basis, sample an input voltage from
an input terminal, generate, from the input voltage, a first output
signal, and output, on an output line, the first output signal as a
first pulse; and a second sampling circuit configured to, on a
repeating basis, sample an input voltage from the input terminal,
generate, from the input voltage, a second output signal, and
output, on the output line, the second output signal as a second
pulse; wherein the sampling by the first sampling circuit is
time-interleaved with the sampling by the second sampling circuit;
wherein the first pulses are time-interleaved with the second
pulses; and wherein the first output signal is latched by the first
sampling circuit when output, and wherein the second output signal
is latched by the second sampling circuit when output.
2. An electronic device comprising: a first sampling circuit
configured to, on a repeating basis, sample an input voltage from
an input terminal, generate, from the input voltage, a first output
signal, and output, on an output line, the first output signal as a
first pulse; and a second sampling circuit configured to, on a
repeating basis, sample an input voltage from the input terminal,
generate, from the input voltage, a second output signal, and
output, on the output line, the second output signal as a second
pulse; wherein the sampling by the first sampling circuit is
time-interleaved with the sampling by the second sampling circuit;
and wherein the first pulses are time-interleaved with the second
pulses; wherein the first sampling circuit and the second sampling
circuit are timed to yield a repeating time sequence of (i)
sampling by the first sampling circuit, (ii) outputting by the
second sampling circuit, (iii) sampling by the second sampling
circuit, and (iv) outputting by the first sampling circuit.
3. The electronic device of claim 1 wherein the first pulses do not
overlap the second pulses.
4. The electronic device of claim 1 wherein the first sampling
circuit generates the first output signal from the input voltage in
substantially the same manner as the second sampling circuit
generates the second output signal from the input voltage.
5. An electronic device comprising: a first sampling circuit
configured to, on a repeating basis, sample an input voltage from
an input terminal, generate, from the input voltage, a first output
signal, and output, on an output line, the first output signal as a
first pulse; and a second sampling circuit configured to, on a
repeating basis, sample an input voltage from the input terminal,
generate, from the input voltage, a second output signal, and
output, on the output line, the second output signal as a second
pulse; a third sampling circuit configured to, on a repeating
basis, sample an input voltage from the input terminal, generate,
from the input voltage, a third output signal, and output, on the
output line, the third output signal as a third pulse; wherein the
sampling by the first sampling circuit, the sampling by the second
sampling circuit and the sampling by the third sampling circuit are
time-interleaved; and wherein the first pulses, the second pulses
and the third pulses are time-interleaved.
6. An electronic device comprising: a first sampling circuit
configured to, on a repeating basis, sample an input voltage from
an input terminal, generate, from the input voltage, a first output
signal, and output, on an output line, the first output signal as a
first pulse; and a second sampling circuit configured to, on a
repeating basis, sample an input voltage from the input terminal,
generate, from the input voltage, a second output signal, and
output, on the output line, the second output signal as a second
pulse; wherein the sampling by the first sampling circuit is
time-interleaved with the sampling by the second sampling circuit;
wherein the first pulses are time-interleaved with the second
pulses; and wherein the sampling circuits are flash
analog-to-digital converters, and wherein the first output signal
and the second output signal are digital output signals indicative
of the input voltage.
7. The electronic device of claim 6 further comprising a
digital-to-analog converter configured to convert each of the
digital output signals into an output analog voltage.
8. The electronic device of claim 1 further comprising: a
sample-timing clock configured to output a series of first
sample-timing pulses interleaved with a series of second
sample-timing pulses; wherein each first sample-timing pulse
activates the sampling by the first sampling circuit; and wherein
each second sample-timing pulse activates the sampling by the
second sampling circuit.
9. The electronic device of claim 8 further comprising: an
output-timing clock configured to output a series of first
output-timing pulses interleaved with a series of second
output-timing pulses; wherein the output-timing pulses are
interleaved with the sample-timing pulses; wherein the outputting
by the first sampling circuit occurs during each first
output-timing pulse; and wherein the outputting by the second
sampling circuit occurs during each second output-timing pulse.
10. A method comprising: performing repeatedly, by a first sampling
circuit, sampling an input voltage from the input terminal,
generating, from the input voltage, a first output signal, and
outputting, on an output line, the first output signal as a first
pulse; and performing repeatedly, by a second sampling circuit,
sampling an input voltage from the input terminal, generating, from
the input voltage, a second output signal, and outputting, on the
output line, the second output signal as a second pulse; wherein
the sampling by the first sampling circuit is time-interleaved with
the sampling by the second sampling circuit; wherein the first
pulses are time-interleaved with the second pulses on the output
line; and wherein the first output signal is latched by the first
sampling circuit when output, and wherein the second output signal
is latched by the second sampling circuit when output.
11. A method comprising: performing repeatedly, by a first sampling
circuit, sampling an input voltage from the input terminal,
generating, from the input voltage, a first output signal, and
outputting, on an output line, the first output signal as a first
pulse; and performing repeatedly, by a second sampling circuit,
sampling an input voltage from the input terminal, generating, from
the input voltage, a second output signal, and outputting, on the
output line, the second output signal as a second pulse; wherein
the sampling by the first sampling circuit is time-interleaved with
the sampling by the second sampling circuit; wherein the first
pulses are time-interleaved with the second pulses on the output
line; and wherein the first sampling circuit and the second
sampling circuit are timed to yield a repeating time sequence of
(i) sampling by the first sampling circuit, (ii) outputting by the
second sampling circuit, (iii) sampling by the second sampling
circuit, and (iv) outputting by the first sampling circuit.
12. The method of claim 10 wherein the first pulses do not overlap
the second pulses.
13. The method of claim 10 wherein the first sampling circuit
generates the first output signal from the input voltage in
substantially the same manner as the second sampling circuit
generates the second output signal from the input voltage.
14. The method of claim 10 comprising: performing repeatedly, by a
third sampling circuit, sample an input voltage from the input
terminal, generate, from the input voltage, a third output signal,
and output, on the output line, the third output signal as a third
pulse; wherein the sampling by the first sampling circuit, the
sampling by the second sampling circuit and the sampling by the
third sampling circuit are time-interleaved; and wherein the first
pulses, the second pulses and the third pulses are
time-interleaved.
15. The method of claim 10 wherein the first output signal and the
second output signal are digital output signals indicative of the
input voltage.
16. A method comprising: performing repeatedly, by a first sampling
circuit, sampling an input voltage from the input terminal,
generating, from the input voltage, a first output signal, and
outputting, on an output line, the first output signal as a first
pulse; and performing repeatedly, by a second sampling circuit,
sampling an input voltage from the input terminal, generating, from
the input voltage, a second output signal, and outputting, on the
output line, the second output signal as a second pulse; wherein
the sampling by the first sampling circuit is time-interleaved with
the sampling by the second sampling circuit; wherein the first
pulses are time-interleaved with the second pulses on the output
line; wherein the first output signal and the second output signal
are digital output signals indicative of the input voltage; and the
method further comprising: converting each of the digital output
signals into an output analog voltage.
17. The method of claim 10 further comprising: outputting a series
of first sample-timing pulses interleaved with a series of second
sample-timing pulses; wherein each first sample-timing pulse
activates the sampling by the first sampling circuit; and wherein
each second sample-timing pulse activates the sampling by the
second sampling circuit.
18. A method comprising: performing repeatedly, by a first sampling
circuit, sampling an input voltage from the input terminal,
generating, from the input voltage, a first output signal, and
outputting, on an output line, the first output signal as a first
pulse; and performing repeatedly, by a second sampling circuit,
sampling an input voltage from the input terminal, generating, from
the input voltage, a second output signal, and outputting, on the
output line, the second output signal as a second pulse; wherein
the sampling by the first sampling circuit is time-interleaved with
the sampling by the second sampling circuit; and wherein the first
pulses are time-interleaved with the second pulses on the output
line; and the method further comprising: outputting a series of
first sample-timing pulses interleaved with a series of second
sample-timing pulses, wherein each first sample-timing pulse
activates the sampling by the first sampling circuit, and wherein
each second sample-timing pulse activates the sampling by the
second sampling circuit; outputting a series of first output-timing
pulses interleaved with a series of second output-timing pulses;
wherein the output-timing pulses are interleaved with the
sample-timing pulses; wherein the outputting by the first sampling
circuit occurs during each first output-timing pulse; and wherein
the outputting by the second sampling circuit occurs during each
second output-timing pulse.
Description
FIELD
The technology described in this patent application relates
generally to pipelined analog to digital converters. More
particularly, systems and methods are disclosed for a low power
high speed pipeline analog to digital converter.
BACKGROUND
High speed analog to digital converters (ADC) are typically used in
electronics such as wireless receivers, cameras, modems, HDTV, and
ultrasound systems. These electronics utilize sampling rates
ranging between 40 MHz and 100 MHz for analog to digital
conversion. At these frequencies, pipelined ADCs may provide low
power consumption, low noise, and high speed. Pipeline ADCs are
often used in applications where dynamic performance is of
importance.
An active sample and hold amplifier is used in many configurations
because it provides the ADC with a settled input voltage, allowing
the subsequent circuit stages to capture the high frequency input
signals. In order to achieve low power consumption and low noise
while keeping performance high, some configurations remove the
active sample and hold amplifier. The active sample and hold
amplifier is not a necessity in ADCs and may also add noise and
distortion to the analog input signal. In addition, an active
sample and hold amplifier may consume large amounts of power and
area on the die.
Aperture error in a typical ADC is the error caused by variation in
the time at which the ADC transitions from sample mode to hold
mode, usually resulting from noise on the clock or input signal. In
a pipeline ADC architecture, sampling a continuous time signal,
rather than a held signal in an active sample and hold device, may
present additional aperture error. With reference to the pipeline
ADC system 100 in FIG. 1A, this error results from a bandwidth
mismatch of the sub-ADC 102 and the multiplying digital to analog
converter (MDAC) 104. The aperture error in a pipeline ADC without
active sample and hold can be demonstrated by the following
equations.
Assuming a full-scale sine wave at the input:
V.sub.in=V.sub.REF.times.sin(2.pi.f.sub.int)
The maximum slope of the signal is represented by:
dd.times..times..times..times..times..pi..times..times.
##EQU00001##
If the time constant mismatch between the sub-ADC 102 and the MDAC
104 is .DELTA..tau.=.epsilon..times..tau., then the maximum
aperture error may be represented by:
V.sub.error|.sub.Max=V.sub.REF.times.2.pi.f.sub.in.times..epsilon..times.-
.tau.
For the 2.5 bit first stage, the error should be smaller than the
correction range, that is V.sub.error|.sub.Max<1/8V.sub.REF. In
addition, the maximum input frequency f.sub.in of the input
sampling networks of sub-ADC 102 and MDAC 104 should be less than
or equal to
.tau. ##EQU00002## The time constant error may then be represented
by:
.times..times.<.times..times..pi..times..times. ##EQU00003##
Because the aperture error grows rapidly with respect to the input
frequency, FIG. 1A utilizes a sampling switch 106. The sampling
switch 106 is shared by both the sub-ADC 102 and the MDAC 104.
Because the switch is shared, the aperture error can be reduced by
matching the time constant of the sampling networks with the
following equations:
.times..times..times..times..times..times..times..times.
##EQU00004##
.times..times..times. ##EQU00005##
.times..times..times..times. ##EQU00006##
In the above equations, g.sub.m is the transconductance of the
preamplifier 108, R.sub.Sm is the on-resistance of the MDAC switch
110, and C.sub.p1 and C.sub.p2 are the total parasitic capacitance
at nodes T1 112 and T2 114. To optimize the time constant mismatch,
the ratio of 1/g.sub.m to R.sub.Sm should be set to 1. This
approach, however, provides for increased power consumption by the
preamplifiers 108.
As shown in FIG. 1B, the time window for T.sub.LATCH reduces the
net amplification duration of MDAC 116. This scenario requires the
operational transconductance amplifier of the MDAC 116 to consume
twice the amount of power as compared to a traditional structure.
Because the sampling duration is made shorter than the normal 50%
duty cycle, the preamplifiers 108 must also be faster to complete
their operations during T.sub.LATCH. The faster operation causes
the preamplifiers to consume more power.
A typical approach to reducing the power consumption of the
pipeline ADC circuit of FIG. 1A is shown in FIG. 2A. Compared with
the system 100 in FIG. 1A, the pipeline ADC system 200 of FIG. 2A
provides each flash comparator 202 and the MDAC 204 with their own
input sampling switches 206a and 206b, respectively. Using separate
sampling switches provides for no kickback from the latches 208 to
the MDAC 204. Accordingly, each flash comparator 202 does not
require a preamplifier and can only include a latch 208. Because
there are no preamplifiers in the flash comparators 202, the
sampling duration is shortened as compared to the typical 50% duty
cycle, as shown in FIG. 2B. In contrast to FIG. 1A, however, there
are no preamplifiers to consume power, so there is no power
tradeoff at the MDAC 204.
Even though there is reduced power consumption in the system 200 of
FIG. 2A as compared to the system 100 in FIG. 1A, the lack of
preamplifiers in the flash comparators 202 creates a larger than
normal input-inferred offset in each of the flash comparators 202.
The large offset may occupy a significant portion of the digital
correction range and leave only a small window for the aperture
error correction.
SUMMARY
In accordance with the teachings described herein, systems and
methods are provided for a time-interleaved pipeline analog to
digital converter. An example of a pipeline analog to digital
converter may include passive sampling circuits and a multiplying
digital to analog converter circuit. A first passive sampling
circuit includes an input terminal coupled to an analog input
signal, and outputs a first sample voltage that is responsive to
the analog input signal. A second passive sampling circuit includes
an input terminal coupled to the analog input signal, and outputs a
second sample voltage that is responsive to the analog input
signal. The first and second passive sampling circuits are clocked
such that the first sample voltage and the second sample voltage
are time-interleaved. A multiplying analog to digital converter
(MDAC) circuit receives the time-interleaved first and second
sample voltages from the first and second passive sampling circuits
and processes the time-interleaved first and second sample voltages
to generate a residue output voltage.
The first and second passive sampling circuits may each further
include a flash analog to digital converter (ADC) circuit coupled
to a first decoder. The MDAC may further comprise a first hold
capacitor coupled to the output of the first passive sampling
circuit and a second hold capacitor coupled to the output of the
second passive sampling circuit. The MDAC input is coupled to the
output terminal of the first and second hold capacitors.
The first passive sampling circuit receives the analog input
voltage when a first sample clock signal is in a logic high state
and the second passive sampling circuit receives the analog input
voltage when a second sample clock signal is in a logic high state.
The MDAC receives the first sample voltage when a first hold clock
signal is in a logic high state and the MDAC receives the second
sample voltage when a second hold clock signal is in a logic high
state.
The first sample clock signal is in a logic high state at every
other logic high state of the first input clock signal and the
second sample clock signal is in a logic high state at every other
logic high state of the first input clock signal, such that at each
logic high state of the first input clock signal, only one of the
first or second sample clock signals is in a logic high state.
The first hold clock signal is in a logic high state at every other
logic high state of the second input clock signal and the second
hold clock signal is in a logic high state at every other logic
high state of the second input clock signal, such that at each
logic high state of the second input clock signal, only one of the
first or second hold clock signals is in a logic high state.
An example of a method for processing an analog input signal in a
pipelined converter includes receiving the analog input signal at a
first passive sampling circuit and outputting a first sample
voltage that is responsive to the analog input signal; receiving
the analog input signal at a second passive sampling circuit and
outputting a second sample voltage that is responsive to the analog
input signal; time-interleaving the first and second sample
voltages; and receiving, at a multiplying analog to digital
converter (MDAC), the time-interleaved first and second sample
voltage from the first and second passive sampling circuits and
processing the time-interleaved first and second sample voltages to
generate a residue output voltage.
A second example of a method for processing an analog signal input
in a pipelined converter, includes receiving, at a first passive
sampling circuit, an input voltage when a first sample clock signal
is in a logic high state, the first sample clock signal being in a
logic high state at every other logic high state of a first input
clock signal; receiving, at a second passive sampling circuit, an
input voltage when a second sample clock signal is in a logic high
state, the second sample clock signal being in a logic high state
at every other logic high state of the first input clock signal,
such that at each high logic state of the first input clock signal,
only one of the first or second sample clock signals is in a logic
high state; outputting a sampled voltage, by the first passive
sampling circuit, to a multiplying digital to analog converter
(MDAC) when a first hold clock signal is in a logic high state, the
first hold clock signal being in a logic high state at every other
logic high state of a second input clock signal; and outputting a
sampled voltage, by the second passive sampling circuit, to the
MDAC when a second hold clock signal is in a logic high state, the
second hold clock signal being in a logic high state at every other
logic high state of the second input clock signal, such that at
each high logic state of the second input clock signal, only one of
the first or second hold clock signals is in a logic high
state.
BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. 1A and 2A illustrate a typical configuration for a pipeline
ADC system.
FIGS. 1B and 2B are timing diagrams corresponding to FIGS. 1A and
2A, respectively.
FIG. 3 is an example of a time-interleaved pipeline ADC system with
high speed capabilities and low power consumption.
FIGS. 4A and 4B are a circuit diagram for a time-interleaved
pipeline ADC system.
FIG. 5 illustrates clock signals for a time-interleaved pipeline
ADC system.
FIG. 6 is a flow diagram illustrating a method of time-interleaving
sub-analog-to-digital converters in a pipeline ADC system.
FIG. 7 is a flow diagram illustrating operation of
time-interleaving sub-analog-to-digital converters in a pipeline
ADC system.
FIG. 8 is an example of a system that may utilize a
time-interleaved pipeline ADC.
DETAILED DESCRIPTION
FIG. 3 is a block diagram of an example of a time-interleaved
pipeline ADC system 300 with high speed capabilities and low power
consumption. The pipeline ADC system 300 includes Sub-ADC1 302,
Sub-ADC2 304, a time-interleaved module 306, and a MDAC 308. In
operation, the pipeline ADC system receives an analog input signal
V.sub.IN at both Sub-ADC1 302 and Sub-ADC2 304. The Sub-ADCs 302
and 304 perform sampling operations on the analog input signal
V.sub.IN and generate a processed signal. The time-interleaved
module 306 controls the timing of the Sub-ADCs so that they operate
in a time-interleaved manner. The time-interleaved module may be
implemented, for example, in a microprocessor or a clocking
circuit. The Sub-ADCs 302 and 304 operate in a time-interleaved
manner so that the MDAC 308 receives the processed signals output
from each Sub-ADC in an alternating fashion.
The alternating, time-interleaved, pipeline ADC system 300 allows
the Sub-ADCs 302 and 304 extra time to complete the sampling
operations. Because of this extra time, the sub-ADCs 302 and 304
run with reduced current, and thus, consume less power. The extra
time also allows the sub-ADCS 302 and 304 to more accurately
capture and process the entire signal and negates the effects of
any delay caused by the preamplifiers to the signal processing
operation.
The sub-ADCs 302 and 304 and the MDAC 308 each utilize a separate
sampling switch and capacitors. This allows for the aperture to be
greatly reduced because the time constants of each circuit may be
matched with the following formula:
.times..times..times..times..times..times..times..times.
##EQU00007##
Because the time constants may be matched and the time for the
flash comparators to sample the input voltage is lengthened, the
time-interleaved pipeline ADC system 300 can operate with low power
consumption and nominal offset.
FIGS. 4A and 4B provide a more detailed example of the
time-interleaved pipeline ADC system of FIG. 3. The pipeline ADC
system 400 of FIGS. 4A-B includes Sub-ADC1 402, Sub-ADC2 404, flash
comparators 406 and 408, decoders 410, and a MDAC 412. In
operation, the pipeline ADC system 400 processes an input analog
voltage V.sub.IN based on the clock signals illustrated in FIG. 5.
Therefore, the operation of the pipeline ADC system 400 will be
described with reference to FIGS. 4A, 4B, and 5.
The input analog voltage V.sub.IN is received at both Sub-ADC1 402
and Sub-ADC2 404. When clock signal CKS1 goes high 502 (FIG. 5),
switches SW0-SW4 close, allowing the input analog voltage V.sub.IN
to be received at the flash comparators 406 in Sub-ADC1 402. As
shown in FIGS. 4A-B, Sub-ADCs 402 and 404 may comprise a plurality
of flash comparators 406 and 408, depending on the bit size being
sampled. The input analog voltage V.sub.IN is subsequently sampled
across capacitors C3 before entering the preamplifier 414 and latch
416 for digitization. The digitized output voltage from the latch
in Sub-ADC1 402 is not received by the MDAC 412, however, until
clock signal CKH1 goes high 504.
As shown in FIG. 5, clock signal CKH1 does not go high until a time
period T.sub.S had elapsed. The time period T.sub.S represents the
time interval for the preamplifier 414 and latch 416 to process the
analog input voltage V.sub.IN. Therefore, the digitized output
voltage is output from the latch prior to clock signal CKH1
transitioning to a high state. This digitized output voltage may be
output to another stage of the pipeline ADC, such as a digital
error correction stage, so that the digital output may be utilized
in an electronic device.
When clock signal CKH1 goes high 504, switches SW5 and SW7 close
and switch SW6 opens, allowing the digitized output voltage to also
be received at the MDAC 412 after passing through hold capacitor
C1.
Because the pipeline ADC system 400 operates the Sub-ADCs 402 and
404 in a time-interleaved manner, Sub-ADC1 402 and Sub-ADC2 404
output a digitized voltage at alternating intervals. As illustrated
in FIG. 5, each Sub-ADC 402 and 404 outputs a digitized voltage
during a T.sub.S time period. Following the time period TS, the
Sub-ADCs 402 and 404 process the digitized signal in the MDAC
412.
Sub-ADC2 404 operates in a similar manner as Sub-ADC1 402. As shown
in FIG. 5, when Sub-ADC1 402 is performing its digitization of the
input analog signal V.sub.IN during the time period T.sub.S, clock
signal CKH2 506 goes high. At this moment, any output from the
Sub-ADC2 404 may be input to the MDAC 412 and clock signal CKS2 508
is low so that the input analog voltage V.sub.IN is not input to
the flash comparators 408. Following the high state of CKH2 506,
clock signal CKS2 508 goes high. At this moment, switches SW8-12
close, allowing the input analog voltage V.sub.IN to be received at
the flash comparators 408 in Sub-ADC2 404. The input analog voltage
V.sub.IN is subsequently sampled across capacitors C4 before
entering the preamplifier 414b and latch 416b for digitization. The
digitized output voltage from the latch in Sub-ADC2 404 is not
received by the MDAC 412, however, until clock signal CKH2 goes
high 510.
As shown in FIG. 5, clock signal CKH2 does not go high at 510 until
a second time period (2*T.sub.S) has elapsed. Just as in Sub-ADC1
402, a digitized output voltage in Sub-ADC2 404 is output from the
latch 410b prior to clock signal CKH2 transitioning to a high state
510. When clock signal CKH2 goes high 510, switches SW13 and SW15
close and switch SW14 opens, allowing the digitized output voltage
to be received at the MDAC 412 after passing through hold capacitor
C2.
The MDAC 412 processes the digitized output voltage during each
hold interval of the system--when clock signal CKH1 or CKH2 are in
a high state. The MDAC 112 then outputs analog output voltage
V.sub.OUT, as illustrated in FIG. 5. The output analog voltage, or
residue, V.sub.OUT may subsequently be received by a next stage
configured to process the residue voltage. This time-interleaved
process may repeat as long as necessary to process each subsequent
sample.
Moving the preamp and latch time from T.sub.LATCH in FIG. 2B to
T.sub.S in FIG. 5 is an advantage of passive time-interleaved
sampling. T.sub.S may be much longer than T.sub.LATCH, allowing for
much less power to be consumed by the preamp and latch. In
addition, because the preamp and latch time is moved, no
T.sub.LATCH is needed and the net amplification duration of the
MDAC may be extended to near half of T.sub.S, allowing for less
power consumption by the MDAC.
FIG. 6 is a flow diagram illustrating an example of a method of
time-interleaving sub-analog-to-digital converters in a pipeline
ADC system. At 602 a first sub-ADC receives an input analog voltage
signal and converts the input analog voltage signal to an output
digital voltage signal. Similarly, at 604, a second sub-ADC
receives the input analog voltage signal and converts the input
analog voltage signal to a second output digital voltage signal. At
606, the sub-ADCs are operated in a time-interleaved, or ping-pong,
fashion. The time-interleaved operation of the sub-ADCs produces
the output digital voltage signals at alternating time intervals.
Therefore, at step 608, the output digital voltage signals are
received, for example by a MDAC, in a time-interleaved fashion.
FIG. 7 is a flow diagram illustrating the operation of clock
signals for a method of time-interleaving sub-analog-to-digital
converters in a pipeline ADC system, such as the method shown in
FIG. 6. At 702, clock signal CK1 is high and clock signal CK2 is
low (see, e.g., CK1 and CK2 in FIGS. 4 and 5). For this condition,
at 704, clock signal CKS1 goes high and an input analog voltage is
sampled in sub-ADC1. After 704, the time period T.sub.S begins.
During this time period, the input analog voltage signal is
digitized. Also during this time period, at 706, clock signal CK1
goes low and clock signal CK2 goes high. During this condition,
clock signal CKH2 also goes high and an output digitized voltage
from sub-ADC2 is held at 708. At 710, clock signal CK1 returns to a
high state and clock signal CK2 returns to a low state. At 712,
clock signal CKS2 goes high and the input analog voltage is sampled
at sub-ADC2. Following 712 is also the end of the T.sub.S time
period. At 714, clock signal CK1 enters the low state and clock
signal CK2 enters the high state. Subsequently, at 716, clock
signal CKH2 goes high and the digitized output voltage produced
during the time period T.sub.S is held for sub-ADC1. The process
then returns at 702 and processes the next sample bits for the
system.
FIG. 8 illustrates an example of a system that may utilize a
time-interleaved pipeline ADC. As shown in FIG. 8, a system
utilizing a time-interleaved pipeline ADC may include a signal
processing and/or control circuit 852, such as a microprocessor or
DSP, a plurality of input/output devices 856, 858, 860, 862, a
memory 866, a mass data storage 864, and/or wireless communication
circuitry 851, 868. In different embodiments, the system
illustrated in FIG. 8 may be included (in whole or in part) in a
cellular telephone, a computer, a DVD player, a television, a
set-top box, a vehicle, a digital media player and/or other
suitable systems or devices.
This written description uses examples to disclose the invention,
include the best mode, and also to enable a person skilled in the
art to make and use the invention. The patentable scope of the
invention may include other examples that occur to those skilled in
the art. For instance, although the example time-interleaved
pipeline ADC systems described herein include two Sub-ADCs, other
examples may include more than two Sub-ADCs.
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