U.S. patent number 7,724,831 [Application Number 11/477,129] was granted by the patent office on 2010-05-25 for method and apparatus for detection of load impedance modulation in a transformer circuit.
This patent grant is currently assigned to Teridian Semiconductor, Corp.. Invention is credited to Kiyoshi Fukahori, Russell Hershbarger.
United States Patent |
7,724,831 |
Fukahori , et al. |
May 25, 2010 |
Method and apparatus for detection of load impedance modulation in
a transformer circuit
Abstract
A method and apparatus for detection of load impedance
modulation as a result of communication of data from the secondary
to the primary side of a transformer are presented. The load
impedance on the secondary of the transformer barrier is modulated
differentially using data to be communicated across the barrier. A
detection circuit on the primary side isolates the load current
from the magnetizing current in the primary. The load current is
subsequently integrated over two consecutive Manchester periods and
the integrated value from the first Manchester period is compared
against that of the second period thereby recovering the receive
data.
Inventors: |
Fukahori; Kiyoshi (Irvine,
CA), Hershbarger; Russell (Nevada City, CA) |
Assignee: |
Teridian Semiconductor, Corp.
(Irvine, CA)
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Family
ID: |
37596042 |
Appl.
No.: |
11/477,129 |
Filed: |
June 27, 2006 |
Prior Publication Data
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Document
Identifier |
Publication Date |
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US 20070014371 A1 |
Jan 18, 2007 |
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Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
Issue Date |
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10857469 |
May 28, 2004 |
7158573 |
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60695243 |
Jun 28, 2005 |
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60695249 |
Jun 28, 2005 |
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60695242 |
Jun 28, 2005 |
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60474009 |
May 29, 2003 |
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Current U.S.
Class: |
375/258;
340/310.17; 340/538.11; 340/538.16 |
Current CPC
Class: |
H04L
25/4908 (20130101); H04L 25/0282 (20130101); H04L
25/4904 (20130101); H04L 5/1423 (20130101); H04L
25/0266 (20130101); H01F 27/42 (20130101); H01F
2019/085 (20130101) |
Current International
Class: |
H04B
3/00 (20060101) |
Field of
Search: |
;375/258,219,319,257
;340/310.07 |
References Cited
[Referenced By]
U.S. Patent Documents
Primary Examiner: Ghebretinsae; Temesghen
Attorney, Agent or Firm: The Hecker Law Group, PLC
Parent Case Text
CROSS REFERENCE TO RELATED APPLICATIONS
This application claims the benefit of priority from U.S.
Provisional Application No. 60/695,243 filed on Jun. 28, 2005,
entitled "Method And Apparatus For Cancellation Of Magnetizing
Inductance Current In A Transformer Circuit"; U.S. Provisional
Application No. 60/695,249 filed on Jun. 28, 2005, entitled "Method
and Apparatus for Sampling Load Current in a Transformer Circuit";
and U.S. Provisional Application No. 60/695,242 filed on Jun. 28,
2005, entitled "Method and Apparatus for Generating a Decision
Threshold Signal from Balanced Samples"; and is a
continuation-in-part of U.S. patent application Ser. No.
10/857,469, filed on May 28, 2004, entitled "A Method and Apparatus
for Full Duplex Signaling Across a Transformer Circuit", which
claims the benefit of priority from U.S. Provisional Application
No. 60/474,009 filed on May 29, 2003, the specifications of all of
which are herein incorporated by reference in their entirety.
Claims
The invention claimed is:
1. An apparatus for detecting load impedance in a transformer
comprising: a transformer having a primary side and a secondary
side, said transformer having a total current being sourced on said
primary side, wherein said total current comprises a magnetizing
inductance current component and a load current component; a first
circuit component coupled to said secondary side of said
transformer, said first circuit component differentially modulating
load impedance on said secondary side of said transformer, wherein
said differentially modulating said load impedance comprises:
obtaining a data stream for communication from said secondary side
to said primary side of said transformer; using a Manchester
encoder to convert said data stream to a differential receive
bitstream; and modulating said load impedance on said secondary
side using said differential receive bitstream; and a second
circuit coupled to said primary side of said transformer for
detection of said modulated load impedance by differentially
integrating said load current on said primary side of said
transformer.
2. The apparatus of claim 1, wherein said load current is isolated
from said total current by canceling said magnetizing current.
3. The apparatus of claim 1, wherein said differentially
integrating said load current comprises: a circuit measuring an
output of a voltage driver on said primary side, wherein said
output is a voltage equivalent of absolute value of said load
current; a circuit generating an error signal between said load
current and an average of said load current; a circuit generating
an integrated output voltage by integrating said error signal; and
a circuit comparing said integrated output signal to a fixed value
at specific time intervals to generate discrete values
corresponding to said load impedance modulation.
4. The apparatus of claim 3, wherein said generating an error
signal comprises: a first voltage to current convener converting
said voltage equivalent to said load current; a filter circuit
generating an average of said equivalent voltage; a second voltage
to current converter converting said average equivalent voltage to
said average load current; and a summer circuit generating said
error signal by subtracting said average of said load current from
said load current.
5. A method for detecting load impedance in a transformer
comprising: sourcing a total current on a primary side of a
transformer, said transformer additionally having a secondary side,
wherein said total current comprises a magnetizing inductance
current component and a load current component; modulating load
impedance on said secondary side of said transformer using
differential coding of data through a first circuit component
coupled to said secondary side of said transformer, wherein said
modulating said load impedance using said differential coding of
data comprises: obtaining a data stream for communication from said
secondary side to said primary side of said transformer; using a
Manchester encoder to convert said data stream to a differential
receive bitstream; and modulating said load impedance on said
secondary side using said differential receive bitstream; and
detecting said load impedance by differentially integrating said
load current on said primary side of said transformer using a
second circuit coupled to said primary side of said
transformer.
6. The method of claim 5, wherein said load current is isolated
from said total current by canceling said magnetizing current.
7. The method of claim 5, wherein said differentially integrating
said load current comprises: measuring an output of a voltage
driver on said primary side, wherein said output is a voltage
equivalent of absolute value of said load current; generating an
error signal between said load current and an average of said load
current; generating an integrated output voltage by integrating
said error signal; and comparing said integrated output signal to a
fixed value at specific time intervals to generate discrete values
corresponding to said load impedance modulation.
8. The method of claim 7, wherein said generating an error signal
comprises: converting said voltage equivalent to said load current;
generating an average of said equivalent voltage; converting said
average equivalent voltage to said average load current; and
generating said error signal by subtracting said average of said
load current from said load current.
9. An apparatus for detecting load impedance in a transformer
comprising: a transformer having a primary side and a secondary
side; a first circuit component coupled to said secondary side of
said transformer, said first circuit component differentially
modulating load impedance on said secondary side of said
transformer, wherein said differentially modulating said load
impedance comprises: obtaining a data stream for communication from
said secondary side to said primary side of said transformer; using
a Manchester encoder to convert said data stream to a differential
receive bitstream; and modulating said load impedance on said
secondary side using said differential receive bitstream; and a
second circuit coupled to said primary side of said transformer for
detection of said load impedance, wherein said second circuit
differentially integrates load current on said primary side of said
transformer for determination of said load impedance.
10. The apparatus of claim 9, wherein said load current is isolated
by canceling a magnetizing current component from total current on
said primary side.
11. The apparatus of claim 9, wherein said differentially
integrating said load current comprises: a circuit measuring an
output of a voltage driver on said primary side, wherein said
output is a voltage equivalent of absolute value of said load
current; a circuit generating an error signal between said load
current and an average of said load current; a circuit generating
an integrated output voltage by integrating said error signal; and
a circuit comparing said integrated output signal to a fixed value
at specific time intervals to generate discrete values
corresponding to said load impedance modulation.
12. The apparatus of claim 11, wherein said generating an error
signal comprises: a first voltage to current converter converting
said voltage equivalent to said load current; a filter circuit
generating an average of said equivalent voltage; a second voltage
to current converter converting said average equivalent voltage to
said average load current; and a summer circuit generating said
error signal by subtracting said average of said load current from
said load current.
13. An apparatus for detecting impedance modulation comprising: a
current sense circuit coupled to a voltage driver that supplies a
load current to a variable impedance, said current sense circuit
providing a detection input signal proportional to the magnitude of
said load current; a threshold circuit sampling said detection
input signal at a first sample point to obtain a first sample value
associated with a first magnitude value of said load current and at
a second sample point to obtain a second sample value associated
with a second magnitude value of said load current, said threshold
circuit comprising an averaging circuit that receives said first
sample value and said second sample value and provides a threshold
value; and a decision circuit receiving said detection input signal
and said threshold value and providing an output data signal,
wherein said decision circuit comprises: a subtraction circuit
receiving said threshold value and said detection input signal and
providing a difference output; and an integrator integrating said
difference output, said integrator being reset at the beginning of
each bit period.
14. The apparatus of claim 13, wherein said decision circuit is
configured to sample said detection input signal adjacent to an
endpoint of a Manchester period associated with an output data
stream of said voltage driver.
15. The apparatus of claim 13, wherein an impedance modulated data
stream in said load current is Manchester encoded, and wherein said
first sample point and said second sample point lie within the same
bit period.
16. The apparatus of claim 13, wherein said integrator is
configured to switch a polarity of integration at a midpoint of
said bit period.
17. A method for detecting impedance modulation in a communication
circuit having a voltage driver that drives a voltage signal onto a
variable load impedance, wherein said voltage signal embodies a
transmit data stream and said variable load impedance is modulated
with a receive data stream that is Manchester encoded, said method
comprising: sensing a load current in said voltage driver to
provide a detection signal proportional to a magnitude of said load
current; integrating said detection signal over a bit period of
said receive data stream to provide an integration result;
switching a polarity of said integration at a midpoint of said bit
period; and determining a binary result based on a polarity of said
integration result at the end of said bit period.
18. The method of claim 17, further comprising: sampling said
detection signal during a first half of said bit period and a
second half of said bit period to provide a first value and a
second value; averaging said first value and said second value to
provide an average signal; and subtracting said average signal from
said detection signal prior to said integration.
Description
BACKGROUND OF INVENTION
1. Field of the Invention
This invention relates to the field of electronic communications.
More specifically the invention relates to detecting modulation of
a load impedance in the secondary of a transformer circuit.
2. Background
An isolation barrier is generally used in applications in which it
is desired to keep voltage potentials in one portion of a circuit
isolated from voltages in another portion, e.g., to prevent
relatively excessive and/or harmful voltages from entering a
relatively low voltage or voltage sensitive circuit. Such
applications may include, for example, telephony, medical,
industrial, and other similar applications.
For example, in a telephony application, it may be necessary to
protect communication circuitry from high voltages on the telephone
line by placing an isolation barrier between the communication
circuitry and the telephone line. However, while it is desirable to
prevent harmful voltages from crossing from one side of an
isolation barrier to the other, it is also desirable to facilitate
signal communication between circuits on both sides of the barrier.
In telephony applications, the isolation requirement is generally
imposed by some governmental requirement (e.g., FCC part 68 in the
US).
The transformer is one of several types of electrical devices that
may be used as an element of an isolation barrier. However, in the
prior art, digital communication across a transformer generally
requires either a pulse transformer for each direction of
communication, or time domain multiplexing of a pulse transformer
(i.e., half-duplex communication). Prior art systems are incapable
of full-duplex digital communication across a single
transformer.
Half-duplex communication reduces communication bandwidth as each
direction of communication must wait its turn to use the one-way
signal channel. However, the use of multiple transformers to
achieve two-way communication is expensive in terms of cost and
space. A full duplex, single-transformer solution is therefore
desired.
Unfortunately, the electrical characteristics of a transformer make
it difficult to simultaneously drive a transmit signal onto, and
detect a receive signal from, the same port of a transformer. For
example, a transmit voltage signal driven across one port of a
transformer gives rise to a load current component and a
magnetizing inductance current component. The load current is
proportional to the transmit voltage signal divided by the load
impedance across the second port of the transformer. The
magnetizing current on the other hand is generated by the
inductance of the transformer coil being driven, and is
proportional to the integral of the transmit voltage signal that
appears across the first port of transformer. The value of the
magnetizing current is thus dependent upon the history of the
transmit signal.
For full-duplex signaling, it would be desirable and advantageous
to have a system that can detect a receive signal across the same
port of the transformer that is being used simultaneously to drive
the transmit signal, in the presence of the load current and
magnetizing current associated with the transmit signal.
SUMMARY OF INVENTION
The present invention provides a method and apparatus for detection
of load impedance modulation in a transformer circuit. In one or
more embodiments of the invention, the separation of transformer
current on the primary side into two components--load and
magnetizing--allows the detection of data communicated from the
secondary to the primary via load impedance modulation of the
secondary port between distinct values. The load current, once
captured, can be compared to a threshold for a data detection
decision.
In one embodiment of the invention, the transmit data communicated
from the primary to the secondary of the transformer is double
DC-balance encoded. With such encoding, the current sourced by the
transmit driver consists primarily of the load current (i.e., from
the load across the secondary of the transformer) and negligible
magnetizing current, if the current sourced from the transmit
driver is sampled at prescribed points in time (e.g., at the end of
a Manchester period), or at any point in time if the magnetizing
current is canceled from the transmit drive current (e.g., by
providing the induced magnetizing current from a separate
source).
Load impedance may be detected by comparing the sourced current to
a threshold value. The threshold value may be adaptively generated
by averaging the two load current values corresponding to two
distinct load impedances. For instance, the data to be transferred
from the secondary to the primary (or a portion thereof) may be
Manchester encoded such that the received data bit at the primary
comprises both the high and low values of load current. The high
and low values can be provided to an averaging circuit to generate
a continuously updated value to be used as a threshold.
One or more embodiments of the present invention take full
advantage of the fact that load current is made separately
available at all times by active cancellation of the magnetizing
current. Instead of discretely sampling the load current at the end
of each Manchester period, the magnitude of the load current
integrated over the first Manchester period may be compared with
the magnitude of the load current integrated over the second
Manchester period to render a data decision. This comparison may be
implemented by continuously integrating the load current magnitude
over both Manchester periods with a polarity reversal in the
integration at the midpoint between the Manchester periods. To
reduce the dynamic range requirements of the integrator, the
average magnitude of the load current may be subtracted from the
instantaneous load current magnitude prior to integration.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is block diagram of a modem Codec DAA (data access
arrangement) connecting a host/DSP to a public switched telephone
network in accordance with an embodiment of the present
invention.
FIG. 2 is a block diagram of a host interface component in
accordance with an embodiment of the present invention.
FIG. 3A is a circuit diagram of a transformer drive scheme in
accordance with an embodiment of the present invention.
FIG. 3B is a signal diagram of the circuit of FIG. 3A, in
accordance with an embodiment of the present invention.
FIG. 4 is a signal diagram illustrating the effect of a
single-balanced data signal (e.g., by a 1-bit to 2-bit Manchester
encoder) on magnetizing current.
FIG. 5A is a signal diagram illustrating the behavior of the
magnetizing current after transmit data is first processed through
a 3-bit to 4-bit encoder followed by a Manchester encoder in
accordance with an embodiment of the present invention.
FIG. 5B is a signal diagram illustrating the behavior of the
magnetizing current after transmit data is first processed through
a first Manchester encoder (1b/2b) followed by a second Manchester
encoder in accordance with an embodiment of the present
invention.
FIG. 6 is block diagram of a host side barrier interface in
accordance with an embodiment of the present invention.
FIG. 7A is a signal diagram illustrating encoding of control and
data in accordance with an embodiment of the present invention.
FIG. 7B is a signal diagram illustrating encoding of control and
data in accordance with another embodiment of the present
invention.
FIG. 8 is a signal diagram illustrating an example of transformer
current waveforms associated with transmit and receive data
signals, in accordance with an embodiment of the present
invention.
FIG. 9 is a block diagram of a line interface component in
accordance with an embodiment of the present invention.
FIG. 10 is a block diagram of a line side barrier interface in
accordance with an embodiment of the present invention.
FIG. 11A is a block diagram of an encoder/decoder in accordance
with an embodiment of the present invention.
FIG. 11B is a block diagram of an encoder/decoder in accordance
with another embodiment of the present invention.
FIG. 12A is a signal diagram illustrating encoding of receive data
in accordance with an embodiment of the present invention.
FIG. 12B is a signal diagram illustrating encoding of receive data
in accordance with another embodiment of the present invention.
FIG. 13 is a block diagram of a clock recovery circuit in
accordance with an embodiment of the present invention.
FIG. 14 is a block diagram of a phase-locked loop in accordance
with an embodiment of the present invention.
FIG. 15 is a signal diagram illustrating representative preamble
pulses for clock recovery lock in accordance with an embodiment of
the present invention.
FIG. 16 is a signal diagram illustrating results of inversion of
the preamble pulses for clock recovery in accordance with an
embodiment of the present invention.
FIG. 17A is an illustration of the makeup of the transmit word in
one embodiment of the present invention.
FIG. 17B is an illustration of the makeup of the receive word in
one embodiment of the present invention.
FIG. 18A is a circuit block diagram of the receive data detection
apparatus of an embodiment of the present invention.
FIG. 18B illustrates the waveforms associated with FIG. 18A.
DETAILED DESCRIPTION
A method and apparatus for detecting data transferred from the
secondary to the primary side of a transformer via load impedance
modulation are described. In the following description, numerous
specific details are set forth to provide a more thorough
description of embodiments of the invention. It will be apparent,
however, to one skilled in the art that the invention may be
practiced without these specific details. In other instances, well
known features have not been described in detail so as not to
obscure the invention.
Embodiments of the present invention may be used in electronic
circuits to support simultaneous, bi-directional communication
across a transformer, for example, in connection with an isolation
barrier of a DAA circuit. Thus, for purposes of illustration, the
method and apparatus of the present invention will be described
below within the context of a DAA isolation barrier implementation.
Although the discussions herein are concentrated on the disclosed
DAA environment, it should be apparent to those of skill in the art
that the principles expounded herein are applicable to other
applications wherein detection of impedance modulation is
desired.
IMPLEMENTATION EXAMPLE
DAA Embodiment
Signal communication across an isolation barrier is generally
useful for telephony, medical, industrial, and other applications
wherein it is desired to separate voltage potentials. In telephony
applications, communication devices (e.g., computers, fax machines,
etc.) typically connect to the PSTN (public switched telephone
network) through modem devices to send and receive signals over the
telephone lines.
A DAA circuit (data access arrangement) provides the interface
between the modem device and the telephone lines, including the
isolation barrier. The DAA may be described in terms of a "line
side" (i.e., that portion of the circuitry that couples to the
telephone line), a "host side" (i.e., that portion of the circuitry
more closely associated with the host device; also referred to as
the "modem side" or "DSP side"), and an isolation barrier that
separates the line side and the host side. The isolation barrier
may include one or more isolation elements, as well as one or more
isolation element types (e.g., transformers, capacitors, optical
couplers, etc.).
FIG. 1 is a block diagram of one embodiment of a modem DAA
connecting a host/DSP to a PSTN. In this illustration, DAA 100
connects host computer 150 to PSTN 160 via the "tip" and "ring"
lines of the telephone network. DAA 100 comprises Host Interface
Component (HIC) 104; Isolation Barrier 106; Line Interface
Component (LIC) 108; and external circuitry 110. HIC 104 interfaces
the DAA functions with Host 150. Host 150 may include, for example,
a DSP, personal computer, or similar device.
External Circuitry 110 provides circuitry for connection of the DAA
to PSTN 160. Typically, the PSTN signal is analog in nature. The
analog information from the PSTN may be converted to digital
information in LIC 108 before transmission across Isolation Barrier
106 to HIC 104. In one embodiment, Isolation Barrier 106 comprises
a pulse transformer.
In telephony applications, analog voice band signals (e.g., 300
Hz-3.6 KHz) on the phone line may be converted to digital data in
LIC 108 using a modulation/demodulation techniques (e.g., at the
rate of 1.536 Mbps for an 8 kHz sampling rate). The generated
digital data may be further processed and/or directly time-division
multiplexed with status and other information to form an effective
transfer rate that may be higher than the bit rate of the digital
data being sent across the transformer of Isolation Barrier 106.
HIC 104 may subsequently demultiplex the received bit stream into
the various components, e.g., voice band signal, status, and other
information. HIC 104 may digitally filter the voice band signal,
decimate and demodulate the voice band signal to extract the
original voice band information, and then send the extracted
digital voice band data (e.g., in 16-bit samples) to Host 150.
In the other direction (i.e., transmission from Host 150 to PSTN
160), HIC 104 may receive digital information from Host 150 for
transmission to PSTN 160. HIC 104 may receive the digital
information in the form of a digital data stream or other form
(e.g., 16-bit data at 16 kHz) from Host 150 and may serialize it
via a parallel-to-serial converter (or an appropriate modulation
technique) to a bit stream of appropriate rate (such as, but not
limited to, 256 kbps or 1.536 Mbps). In accordance with one or more
embodiments of the invention, an encoding scheme may be used to
maintain DC-balanced current and voltage characteristics within the
signal driven across the transformer of Barrier 106, thus raising
the actual data transfer rate across the barrier to the full
transfer speed (such as, but not limited to, 512 kbps or 2.048
Mbps). The digital bit stream is then received by LIC 108.
Communication across Isolation Barrier 106 may be performed in
full-duplex. In addition to the data communicated across the
barrier, control and clocking information, as well as power may be
sent across the barrier. For instance, clocking information used to
reconstruct the HIC clock in LIC 108 may be embedded in the bit
stream sent across the barrier from HIC 104.
In one embodiment of the DAA circuit, HIC 104 may provide power
needed by LIC 108 while the phone line connection is "on-hook."
However, after the phone line connection goes "off-hook," LIC 108
may be entirely line powered, if power is available from the
telephone line.
A serial data port may be provided for transferring "receive" data
and status information from HIC 104 to Host 150 and "transmit" data
and control information from Host 150 to HIC 104. As used herein,
"receive" data is data sent from the line side to the host side and
"transmit" data is data sent from the host side to the line
side.
In the descriptions that follow, the primary side of transformer
106 is connected to HIC 104 and the secondary side of transformer
106 is connected to the LIC 108 for consistency in description. It
should be apparent to those of skill in the art that other
arrangements are also possible. In addition, "forward direction"
refers to data and control bits driven onto the primary by the HIC
drivers. Clocking and power may also be provided in the forward
direction. The "reverse direction" is data received by HIC 104 from
across Barrier 106.
Pulse transformer 106 may have, for example, a 1:1 (PRI:SEC)
winding ratio. However, it should be apparent to those of skill in
the art that the transformer ratio is in no way constrained to
those discussed herein.
The pulse transformer has advantages over other types of isolation
elements. For instance, advantages of a pulse transformer over a
capacitor as the isolation element include lower cost Bill of
Materials (BOM); lower component count; and better common mode
noise immunity. In addition, it may be easier to send power across
a transformer with minimum loss (e.g., HIC 104 sending power across
to LIC 108) while the phone line connection is "on-hook."
FIG. 2 is a block diagram of an embodiment of Host Interface
Component 104. In the illustrated embodiment, HIC 104 may include,
for example, Modem Interface (MI) 210; Transmit and Receive Signal
Processors (TSP 221 and RSP 222); Modem Side Barrier Interface
circuit (MSBI) 230; Modem Side Barrier Interface Finite State
Machine (MSFSM) 250; and Clock Generation Circuit (CLKGEN) 240.
MI 210 may provide a bi-directional data port that can be
configured to support most DSP's or similar processing units with
which it may interface. MI 210 provides an interface between Host
150 and DAA 100. In the present illustration, only representative
interface signals are shown.
Signals Tx_D 203 and Rx_D 204 may be configured as internal signals
of a predetermined width (e.g., 16 bits wide). In this
illustration, Tx_D 203 is input to Transmit Signal Processor (TSP)
module 221 and Rx_D 204 is output from Receive Signal Processor
(RSP) 222. In addition, clock signals TRSPCLK 205 provides clocking
for module TSP 221 and module RSP 222. In addition, clocks to MSFSM
250 and MSBI 230 may be derived within CLKGEN 240 from the system
clock (SysCLK 206).
TSP 221 receives digital data, Tx_D 203, from MI 210, processes the
digital data, and may serialize it via a simple parallel to serial
converter or through an over-sampling quantizer (e.g., digital
sigma-delta modulator) to generate transmit bit stream TxdBS 225,
which is coupled to MSBI 230 for transmission over the barrier. The
present invention is in no way limited in the mechanism by which
the one-bit data stream TxdBS originates.
In one or more embodiments, TSP 221 may consist of a transmit
interpolation filter (TIF) that takes in 16-bit data, for example,
from MI 210 at a certain rate (e.g., 8 kHz), and a parallel to
serial converter or a digital sigma-delta modulator. The TIF may
up-sample (i.e., interpolate) the data to a desired rate (e.g., 16
kHz), and output a 16-bit (or other multi-bit) data stream. This
16-bit data stream may be immediately serialized and sent to MSBI
230 for transmission or, alternately fed to a digital sigma-delta
modulator and thus converted to a serialized bit stream for
transmission. The former has the advantage of reduced data rate
across the barrier; however, any serialization method may be
employed without departing from the spirit of the invention.
The serialized output TxdBS 225 from either the parallel to serial
converter or a digital sigma-delta modulator (DSDM) is fed into
MSBI 230 for time-division multiplexing with control data to form a
transmit bit stream (TBS), which, in one or more embodiments, is
double-balanced encoded (e.g., DC-balanced with respect to current
and voltage drive to the transformer) prior to transmission across
the barrier to LIC 108.
In the receive direction, information that is transferred over the
barrier (e.g., using impedance modulation) from the LIC 108 to MSBI
230 is decoded and separated into data and status in MSBI 230. The
data portion (RxdBS 226) may be fed to one or more digital filters
in RSP 222. The digital filters may be synchronized so that there
is one sample available at the desired output rate (e.g., 16
kHz).
The output of RSP 222, Rx_D 204, may be decimated output data (e.g.
16-bit wide) at the desired rate (e.g., 8 kHz). Rx_D 204 may then
be transmitted to MI 210 for subsequent processing and transmission
to Host 150.
MSBI 230 provides the interface functionality of the HIC with the
isolation barrier for communication with LIC 108. In one or more
embodiments, in addition to other functions, the MSBI 230 may
manage all of the required signaling across the barrier by, for
example: encoding the transmit bit stream (TxdBS 225) and control
information (CTL) and transferring the encoded signal across the
barrier; decoding the receive bit stream (RxdBS 226) and status
information (STA) from LIC 108; and generating proper amplitude
pulses to transfer power to LIC 108 when necessary. The MSFSM 250
is a state machine that controls the functions of MSBI 230 and
generates the control signal, CTL, that is transferred across the
barrier to LIC 108.
Referring back to FIG. 1, the telephone line side of the DAA
embodiment comprises LIC 108 and external circuitry 110. The
functionality of LIC 108 and external circuitry 110 of one possible
embodiment are further illustrated in FIG. 9. As illustrated, LIC
108 comprises circuitry enclosed in block 900. Other circuitry (not
shown) may also be part of the external circuitry 110.
LIC 108 comprises Line Side Barrier Interface (LSBI) 902; clock
recovery circuit (CLK REC) 904; line side finite state machine
(LSFSM) 906; analog-to-digital converter block (ADC) 908;
digital-to-analog converter block (DAC) 910; active termination
circuit 912; AC transmit driver (ACGM) 914; voltage regulator 916;
anti-aliasing filter (AAF) 918; transmit echo generator 920; DC
termination circuit (DCGM) 922; auxiliary analog-to-digital
converter (Aux A/D) 924; multiplexer 926; and ring amplifier (RG
Amp) 928.
In one embodiment, the analog signal from the telephone line (Tip
and Ring) is conditioned through Rectifier 930 to eliminate any
polarity issues.
The positive terminal of Rectifier 930 is AC coupled through the
Rxp input of block 900 to the positive terminal of AAF 918. As
illustrated, AAF 918 may comprise one or more active and/or passive
filters and amplifiers. The negative terminal, Rxn, of AAF 918 is
AC coupled to output TXN of transmit echo generator 920 for
transmit echo cancellation.
AAF 918 sums the receive signal, Rxp, with a portion of transmit
signal, TXN, to reduce the transmit signal component in the receive
path.
The analog output, Rx, of AAF 918 is coupled to ADC 908 for
conversion to the receive data bit stream, RxdBS. The resulting
high frequency one-bit receive data stream (RxdBS) may be sent to
LSBI 902 for encoding and eventual transmission across the barrier
to HIC 104, or alternately be further filtered by an additional
digital filter such as Sinc^3 filter, then serialized and sent to
LSBI 902 for transmission across the barrier.
DCGM 922 provides for appropriate DC termination characteristics by
monitoring the input voltage from the telephone line (DCI), and the
DC loop current sense (DCE).
In the transmit direction, the transmit bit stream (TBS) received
from across the barrier by LSBI 902 is first separated into
transmit data bit stream (TxdBS) and control data (CTL). The
transmit bit stream TxdBS may be converted to the analog transmit
signal Tx using devices such as: a serial to parallel converter and
digital filter (e.g., digital sigma-delta modulation); or a Digital
to Analog Converter block (e.g. DAC 910). The received signal from
AAF 918 (e.g., Rx) is summed with the transmit signal in active
termination block 912. AC termination is provided by sensing the
receive signal at terminal Rxp and feeding back an appropriate AC
current generated within active termination circuit 912 via AC
transmit driver 914 to the collector of transistor Q5.
In one or more embodiments, an auxiliary analog to digital
converter, Aux A/D 924, may be used to convey status information
associated with the line condition. The tip and ring inputs may be
coupled as differential inputs to amplifier 928, and then
multiplexed with the line sensing signals, DCI and DCE, for
conversion in Aux A/D 924. The output of the Aux A/D 924 may then
be coupled to line side finite state machine (LSFSM) 906 for
transmission to HIC 104 as status (STA) component of the receive
signal.
The host (i.e., Host 150) in communication with HIC 104 receives
and interprets the status data to decide the appropriate action in
controlling the DAA device.
Full-Duplex Signaling over the Transformer
To understand the functions of MSBI 230 and LSBI 902, it is useful
to discuss the general concept of transferring data
bi-directionally and simultaneously (i.e., full duplex) across the
isolation barrier in accordance with one or more embodiments of the
present invention.
FIGS. 3A and 3B provide illustration of the basic concept involved
in the bi-directional transfer of data across a pulse transformer.
FIG. 3A is an illustration of a transformer drive scheme in
accordance with an embodiment of the present invention. FIG. 3B
shows the transformer voltage and current values Vin, Vout, and Iin
when the input data TxdBS="0" is doubly DC balanced via Manchester
coding to yield "0110" TBS (first stage Manchester encoding: "0"
becomes "01"; second stage Manchester encoding: "01" becomes
"0110") and the receive data RBS transitions from "0" to "1" at the
midpoint of the data period. In this illustration, PRP and PRM are
the positive and negative terminals on the primary side of the
pulse transformer, respectively. Similarly, SCP and SCM are the
positive and negative terminals on the secondary side of the pulse
transformer, respectively.
In operation, transmit data, in the form of input voltage Vin, is
driven across the primary side of the transformer. Assuming a 1:1
winding ratio (though other winding ratios may be used as well),
mutual inductance causes the input voltage to be induced across the
output terminals of the secondary as Vout. As a consequence, output
current Iout flows through the loading resistor R1 (e.g., 1
k.quadrature.), assuming the switch on R2 is open (i.e. off). Since
magnetic flux in a transformer cannot change immediately, input
current Iin will flow into the primary side simultaneously.
By turning on the switch controlled by RBS 302 (see portion of
waveforms in FIG. 3B labeled 320), and hence placing resistor R2 in
parallel with resistor R1, the load impedance changes to the
equivalent impedance of two resistors in parallel. For example, if
R1 and R2 are each 1 k, then the equivalent impedance is 0.5
k.quadrature.. Load dependent components of Iout and Iin also
change as the impedance changes. For instance, if the load current,
I.sub.L, is 0.5 milliamps when driven by +0.5 v across the primary
ports with only R1 as the load impedance, then the load current
will double to 1.0 milliamps when R2 is switched on (given R1=R2=1
k.quadrature.). Thus, if the load-dependent portion of Iin could be
separated out from the total current Iin, it would form a basis for
detecting the impedance changes on the primary side of the barrier
and extracting the receive data (RBS 302) responsible for those
changes (i.e., by controlling the switch).
In operation, Iin is composed of a magnetizing inductance component
and a load current component. For the detection of impedance
modulation, it is possible to isolate the component of Iin due to
load impedance, I.sub.L, from the component of Iin due to the
magnetizing inductance, I.sub.M. One or more embodiments of the
invention facilitate isolation of the loading current from the
magnetizing current by using a transmit data encoding scheme that
is double DC balanced, i.e., DC balanced in both current and
voltage. Double DC-balancing of the transmission signal induces
predictable behavior in the magnetizing inductance current, such
that the magnetizing inductance current is near zero at specific
times. For example, in FIG. 3B, I.sub.M approaches zero value at
points 341, 342 and 343 (e.g., at the end of each double-balanced
data period).
FIG. 4 provides an example of a transmit data stream that is not
double-balanced, with the corresponding magnetizing current. In
this example, transmit data TxdBS 410 is Manchester encoded (single
balanced) to generate coded data Txd 420, which is driven across a
transformer. In this illustration, the magnetizing current 430 at
the end of each of the Manchester periods is affected by the change
in data pattern and may vary from one Manchester period to the next
as shown. For example, at the transition from data sequence 413 to
data sequence 414, the magnetizing current, because of its
integrating behavior, rises well above the DC balance point for
current. The perturbation in DC current value decays toward zero
over time until perturbed again by another non-double-balanced data
sequence. This makes the process of isolating the load current from
magnetizing current more difficult because the value of the
magnetizing current is unpredictable.
To make magnetizing current predictable, the transmit signal may be
doubly DC balanced prior to transmission across the transformer.
Balancing the transmit data signal in both current and voltage may
be established, for example, by applying multiple single-balanced
encoding processes to the transmit data (in sequence or otherwise).
For example, Manchester encoding (i.e., 1b/2b) applied twice to the
transmit signal will result in a double-balanced data stream. In
other embodiments, a single encoding process may be implemented
that provides DC balancing of both current and voltage
characteristics. The benefit of this encoding is that the
magnetizing current, I.sub.M, returns to zero at the end of every
Manchester period.
In accordance with one embodiment of the invention, this
facilitates detection of the load current, I.sub.L, by sampling Iin
at specific points in time when I.sub.M is near zero (e.g., near
the transition between each Manchester period).
In accordance with another embodiment of the invention, the
predictable nature of magnetizing current I.sub.M allows for
generation of a corresponding cancellation current at the primary
of the transformer, such that the load-dependent current I.sub.L
may be sampled substantially free of the influence of the
magnetizing inductance current.
The impact of specific balancing block codes on transmission
bandwidth, circuit complexity, and decay time of the encoded signal
may be considered in selecting a particular encoding scheme. For
instance, using two Manchester encoders (1-bit to 2-bit encoding)
in series would result in the use of four times the original
transmission bandwidth. In contrast, using a 7b/8b (i.e., 7-bit to
8-bit) encoder would be more bandwidth efficient, but may result in
an unnecessarily complex circuit. In one or more embodiments of the
present invention, a DC balanced 3b/4b encoder or a Manchester
encoder is applied in series with another Manchester encoder to
provide predictable magnetizing current with relatively moderate
increases in bandwidth.
FIG. 5A is an illustration of the behavior of the magnetizing
current after TxdBS 410 is processed through a 3-bit to 4-bit
encoder in accordance with an embodiment of the present invention.
In this illustration, a DC-balanced 3-bit to 4-bit encoding scheme
is used in the first stage (i.e., waveform 510), followed by a
Manchester encoding second stage (i.e., waveform 520). This
combination of encoding schemes results in the magnetizing current
shown in waveform 530, which returns to zero at the end of each
Manchester period.
A 4-bit data scheme has only six code words available that are DC
balanced as follows: "0011"; "0101"; "0110"; "1001"; "1010"; and
"1100". Thus, in the 3-bit to 4-bit encoding scheme of an
embodiment of the present invention, these six balanced code words
are assigned the values from one ("001") through six ("110") of the
three input bit combinations. The remaining two input words, zero
("000") and seven ("111") are encoded to alternate between two
unbalanced 4-bit words that average to DC-balanced words, e.g.,
"000" may be encoded to alternate between "0010" and "1101", while
"111" may be encoded to alternate between "0100" and "1011".
FIG. 5B is an illustration of the behavior of the magnetizing
current in another embodiment after TxdBS 410 is processed through
two layers of Manchester encoding. In this illustration, a
DC-balanced 1-bit to 2-bit encoding scheme is used in the first
stage (see waveform 540), followed by a Manchester second stage
(see waveform 550). As in the 3b/4b case, the magnetizing current
is predictably zero at the end of each Manchester period
independent of the raw transmit data values, as shown in waveform
560.
As the waveforms illustrate, the double Manchester encoding of
transmit data to a double DC balanced signal 550 results in a
balanced and predictable magnetizing current 560--i.e., zero at the
end of each Manchester period. Thus the transformer input current
Iin sampled at the end of every Manchester period will ideally be
equal to I.sub.L, the load current. Because load current can be
detected by sampling the primary side current, Iin, at prescribed
times, it is possible, in one or more embodiments of the invention,
to communicate receive data using modulation of load impedance on
the secondary of the transformer.
Modem Side Barrier Interface
Now referring back to MSBI 230 of the DAA circuit example, FIG. 6
illustrates one embodiment of a Modem Side Barrier Interface. As
shown, MSBI 230 may comprise Control Encoder block 602; DC Balance
Encoder block (e.g., 3b/4b, 1b/2b Manchester, etc.) 604;
Multiplexer (Mux) 608; Demultiplexer (Demux) 614; Manchester
Encoder 616; Receive Detector 618; Error Integrator 620; Ramp
Generator 622; Current Driver 624; and Voltage Driver 626.
In this example, transmit data, TxdBS, is first DC-balance encoded
(e.g. by either 3b/4b encoding and then serializing, or directly
serializing via Manchester encoder) at block 604. Encoding
increases the rate of the transmit data. For example, assuming the
data rate of the transmit bit stream, TxdBS, is at 256 kbps, the
actual data rate across the barrier, after two layers of Manchester
encoding, is 256.times.4=1.024 Mbps, or after 3-bit to 4-bit
conversion in series with Manchester encoding,
256.times.4/3.times.2=683 kbps.
In one embodiment, an AC power signal may be transmitted over the
isolation barrier to LIC 108 from HIC 104 in special power frames
that are time division multiplexed with data frames carrying the
TxdBS data stream. The power frame may consist of, for example,
enhanced magnitude voltage pulses that may be rectified and
converted to a DC power source on the line side of the barrier. The
power signal is doubly DC balanced at the point it is driven across
the transformer, and, in one or more embodiments, may be utilized
as a channel for control information.
In the embodiment of FIG. 6, composite signal CTL is the power
signal modulated by control data. For example, when transfer of
control data is necessary, the control data bit (i.e., CTL) may be
encoded as follows: "0" may be encoded as "xx0101xx" and "1" may be
encoded as "xx1010xx" in block 602 (where "xx" represents "don't
care" bit values that are allowed to vary as long as double DC
balancing is maintained). The resulting encoded CTL data and TxdBS
data are time-division multiplexed in Mux 608 to generate TxdCTL,
which is subsequently Manchester encoded in block 616 to generate
the transmit bit stream, TBS. Transmit bit stream TBS is driven
across the barrier by Voltage Driver 626.
FIG. 7A is an illustration of encoding control and transmit data as
seen across the primary side of the barrier in accordance with an
embodiment of the present invention. It consists of power frames
(702A and 704A) and data frames (701A and 703A). In the illustrated
embodiment, each frame consists of eight Manchester periods. Each
frame is thus capable of transferring four bits of raw data or
eight bits of DC-balanced data (as a result of 1b/2b Manchester
encoder or a 3b/4b encoder), prior to Manchester Encoder 616.
Control signal, CTL, may be time-division-multiplexed with the
transmit bit stream (TxdBS) for transmission across the barrier to
LIC 108 from the HIC 104. In a preferred embodiment, each power
frame is assigned one value of CTL bit as shown in FIG. 7A. In
block 602, CTL="0" may be encoded as "xx0101xx" and CTL="1" may be
encoded as "xx1010xx". It should be clear to those skilled in the
art that more than a single bit of CTL information may be
transferred across in one power frame. The resulting encoded CTL
data and TxdBS data are time-division multiplexed in Mux 608 to
form the composite bit stream, TxdCTL, which is subsequently
Manchester encoded in block 616 before being driven across the
barrier by Voltage Driver 626. As illustrated, Data 701A represents
data to be transmitted; Data 702A represents a control value of
"0"; Data 703A represents data to be transmitted; and Data 704A
represents a control value of "1".
As illustrated in FIG. 7A, for an embodiment using a 3b/4b encoder,
one bit of control data and six raw (uncoded) transmit bits
(equivalent to eight coded bits) are alternately transferred across
the barrier, the effective control data transfer rate is one-sixth
the rate of the transmit bit rate. In another embodiment wherein
the first stage encoder is a 1b/2b encoder, one bit of control data
and four raw (uncoded) transmit bits (equivalent to eight coded
bits) are alternately transferred across the barrier, the effective
control data transfer rate is one-fourth the rate of the transmit
bit rate.
Alternately, FIG. 7B shows that CTL information can be embedded in
the Data frame itself instead of the power frames if excess
bandwidth exists within the data frames. In this embodiment, 1b/2b
encoder as the first layer of encoding is used in which one bit of
control data and three (uncoded) bits are alternately transferred
across the barrier. The effective control data transfer rate is one
third the rate of the transmit bit rate.
In one embodiment of the present invention, the transmit signal is
doubly DC balanced using two layers of Manchester encoding prior to
transmission. FIG. 17A is an illustration of the makeup of the
transmit word in one embodiment of the present invention. In this
illustration, the TSP 221 (see FIG. 2) serializes the 16 bit wide
data (i.e. Tx_D) over six data frames (1701, 1703, . . . 1711) to
generate TxdBS. The first data frame (i.e. 1701) comprises bits 15
(LSB) and 14; the second data frame (i.e. 1703) comprises bits 13,
12, and 11; the third data frame (not shown) comprises bits 10, 9,
and 8; the fourth data frame (not shown) comprises bits 7, 6, and
5; the fifth data frame (not shown) comprises bits 4, 3, and 2; the
last data frame (i.e. 1711) comprises bits 1 and 0.
Each data frame carries three data bits and each power frame (e.g.
1702 and 1712) carries one CTL bit. Since each data frame has four
bit-slots available for data, the first bit is arbitrarily set to
zero. However, other embodiments may choose to embed the CTL bit or
other information in the first bit slot of the data frames. (See
the illustration in FIG. 7B for the receive data). In addition, it
may be necessary to delineate each word boundary by some means, for
example, one header bit may be attached to each word, as
illustrated in FIG. 17A. The resulting transmit serial word may
then undergo the first stage of Manchester encoding to generate the
signal TxdCTL.
In the reverse direction, the data to be sent across the barrier,
RxdBS, may be formed by serializing a 17 bit wide data at 16 kHz
(from ADC 908) over six data frames just as transmit data was
formatted. FIG. 17B is an illustration of the makeup of the receive
word in one embodiment of the present invention. As illustrated,
one header bit is attached to the beginning of the 17 bit word and
the resulting 18 bits are divided over the six data frames, i.e.,
three data bits per frame leaving one bit for STA in each of the
data frames.
In this illustration, the ENDEC 1006 (see FIG. 10) serializes the
17 bit wide data (i.e. RxdBS) and a header bit over six data frames
(1721, 1723, . . . 1731) as follows: the first data frame (i.e.
1721) comprises header bit, and data bits 16 (LSB) and 15; the
second data frame (i.e. 1723) comprises bits 14, 13, and 12; the
third data frame (not shown) comprises bits 11, 10, and 9; the
fourth data frame (not shown) comprises bits 8, 7, and 6; the fifth
data frame (not shown) comprises bits 5, 4, and 3; the last data
frame (i.e. 1731) comprises bits 2, 1, and 0.
Thus both transmit and receive formats are very similar,
simplifying the design of the barrier interface significantly.
In an example embodiment, each Manchester period is 1/1.536 MHz or
roughly 650 nsec, and both data and power frames consist of eight
Manchester periods each, or roughly 5.2 usec. Accounting for an
equal number of frames for power and CTL transfer, it takes a total
of twelve frames or 62.5 usec to transfer an entire word in
transmit direction (six data frames to transfer a word in either
direction). Since no receive data can be sent across the barrier
during power frames, the transfer rate of the entire receive word
is the same as that of the transmit word. Thus, so long as the
transmit and receive words are generated at the same rate (e.g., at
16 kHz=1/62.5 usec.), seamless full duplex communication can be
established without any need for buffering data in either
direction.
Impedance Modulation Detection
Referring back to FIG. 6, the receive data, RBS, is a decoded bit
stream obtained by isolating the transformer current, Itotal, into
two components: I.sub.M, the magnetizing current; and I.sub.L, the
load current (i.e., due to the transformer load impedance of R1 and
R2). In accordance with an embodiment of the invention, a current
feedback path comprising elements 618, 620, 622 and 624 may be
implemented to generate a compensating current Ixid, which acts to
cancel the magnetizing inductance current, I.sub.M. The feedback
loop forces Ixid to track I.sub.M so that the receive data may be
detected and extracted from the load current I.sub.L, which in this
embodiment is sourced from (or sunk by) the voltage driver as input
current Ixvd (i.e., if Ixid is substantially equivalent to I.sub.M,
then Ixvd will consist substantially of I.sub.L).
The digital input voltage signal comprises short spans of
relatively constant voltage values, balanced around zero. Due to
the integral relationship between input voltage and current in an
inductor, the magnetizing inductance current, as illustrated in
FIG. 8, may be characterized as a fixed-rate ramp toggling between
upward and downward slopes as the input voltage signal toggles
between digital (e.g., binary) voltage states. A compensating
current equivalent to the magnetizing current may therefore be
generated by a controllable current ramp generator.
In one embodiment, a ramp current is generated in block 622, and
scaled and converted to Ixid in current driver block 624. The
generated current, Ixid, feeds into the primary terminal of the
transformer to cancel the magnetizing inductance current drawn by
the transformer. Due to the operation of the feedback loop, current
Ixid is adapted to be substantially equivalent to the magnetizing
current, I.sub.M, so that the current (Ixvd) sourced (or sunk) by
voltage generator 626 is substantially equivalent to the isolated
load current, I.sub.L.
As illustrated, Receive Detector 618 decodes the receive data and
generates the loop error discriminant from signal VMR, which is a
function of the magnitude of the load current I.sub.L. Signal VMR,
in one embodiment, is a voltage signal that is generated by forcing
the rectified value of current Ixvd (i.e., |Ixvd|) of the voltage
driver thru a diode connected PMOS device. For the purpose of
canceling the magnetizing current, VMR can be conveniently used in
a current mirror configuration to regenerate error current within
Error Integrator 620 for further processing.
Example input voltage waveforms for transmit data (Manchester
encoded), and corresponding waveforms for currents I.sub.M, I.sub.L
and Itotal are shown in FIG. 8. VMR can be sampled at two different
times to form an error discriminant. Since I.sub.M is known to be
ideally zero at the end of the Manchester period (V2--802, 804 in
FIG. 8) and at its maximum in the middle of the Manchester period
(V1--801, 803 in FIG. 8), VMR (that represents |Ixvd|) is sampled
at those two instances, in one embodiment. Any difference that
exists between the two samples represents a portion of magnetizing
current I.sub.M that is not cancelled by the Ixid of the current
driver 624, resulting in an error signal around which the servo
loop may be closed to achieve Ixvd=I.sub.L.
When the error signal into integrator 620 averages to zero, the
integrator output is constant. This constant output may form the
basis for ramp generator 622. For instance, a constant current
source, when integrated, results in a ramped current output. The
generated current ramp from ramp generator 622 may subsequently
feed into current driver 624 (e.g., a high impedance driver), which
drives the current, Ixid, into the primary of the transformer.
Thus, a feedback loop comprising an error (receive) detector 618,
error integrator 620, ramp generator 622, and current driver 624 is
used, in one embodiment, for cancellation of the magnetizing
inductance current, I.sub.M. The voltage driver sources (or sinks)
the isolated load current equivalent.
For data recovery purposes, the receive detector may comprise a
load current processing circuit and a threshold detector, for
example. Thus, an embodiment may use a simple logic of setting the
receive data to zero ("0") when the load current is below the known
threshold, otherwise the receive data is set to one ("1").
Referring to FIG. 8, the receive signal Rxd may be decoded by
sampling the current Ixvd (via sensing voltage VMR) at any time in
the bit period, and comparing the magnitude of the sensed value
against a threshold. The threshold may be derived, for example,
from the average of the two sensed levels corresponding to the two
known impedance values.
Alternately, the receive data may be differentially encoded (as
shown in FIG. 12B) such that the receive data may be recovered by
detecting the load currents differentially. More specifically,
since each raw data bit is encoded into "01" or "10", the magnitude
of the load current |IL| may be integrated over the first half of
the raw data period and compared with the result of similar
integration performed over the second half of the raw data period
to recover the raw receive data. The comparison is done by virtue
of polarity reversal in integration at the end of the first
Manchester period. If the integrated value at the end of the second
Manchester period is positive, the raw data is decoded as "1",
otherwise "0". (Note: references to the Manchester period relate to
the Manchester period of the transmit signal; the raw data period
of the receive data is equivalent to two Manchester periods of the
transmit data.)
FIG. 18A is a circuit block diagram of a detection apparatus for
data recovery in accordance with an embodiment of the present
invention. FIG. 18B illustrates the waveforms associated with FIG.
18A. In each of the data periods of the illustrations of FIG. 18B,
transmit raw data is shown doubly encoded by two layers of
Manchester coding and the receive data by a single layer of
Manchester coding. The current, I.sub.L, and the magnetizing
current, I.sub.M, are separately shown. In this example, when the
termination impedance is either 1 k.quadrature. (i.e. R1) or 0.5
k.quadrature. (i.e. R1+R2), the load current, I.sub.L, is
approximately 0.5 mA or 1.0 mA.
Signal VMR, which is an output of voltage driver 626, is a voltage
representing the absolute value of the load current, I.sub.L (or a
proportional representation thereof). For detection of the receive
data, four clocks (designated as P1, P2, P3, and P4 in FIG. 18B)
are generated for clocking the various switches represented in FIG.
18A. P1 is used to reset the integrator at the beginning of each
data period; P2 is used to reverse the polarity of integration; P3
is used to sample the integrator at the end of each data period;
and P4 is used to sample the load current when the magnetizing
current, I.sub.M, is known to be zero.
As illustrated, voltage VMR is converted by Voltage to current
converter V2I 1802 to the absolute value of the load current,
|I.sub.L|, or a proportional metric thereof. This absolute value of
the load current is then provided to summer 1816 where the average
magnitude of the load current, Isub, is subtracted from it to
generate an error signal. This error signal is assigned a polarity
based on the P2 clock signal at switch 1806. For instance, a
positive sign is assigned to the error signal when P2 is true, and
a negative sign is assigned when P2 is false (i.e., P2B). The
signed error signal output of switch 1806 is subsequently sent to
integrator 1808.
The error signal generated in summer 1816 is integrated by
integrator 1808 to generate a decision voltage Vint. Integrator
1808 is reset at the beginning of each of the raw data bit periods
(i.e., each Manchester period) using clock P1 at switch 1812. As
illustrated in FIG. 18B, the absolute value of I.sub.L goes between
0.5 milliamps and 1.0 milliamp, thus the average current Isub is
0.75 milliamps. (Since Rxd is Manchester coded, sampling will
generate the average of the two load currents representing two
different terminations). Thus, as the waveforms illustrate, the
error signal, which is integrated by integrator 1808 to generate
Vint, will be negative through data period 1821; negative during
data period 1822; positive during data period 1823; and positive
during data period 1824. The resulting integrator output Vint is
sampled with signal P3 at D-flip/flop 1810 to generate the receive
data signal, RBS (see FIG. 6). The integrator is reset at the end
of every data period using P1.
The average magnitude of the load current, Isub, (e.g., 0.75 mA in
this example) is constantly subtracted from the integration to
minimize the dynamic range requirements of the integrator. The
average load current magnitude is generated by using signal P4 to
sample the voltage VMR via switch 1814. The sampled VMR voltage at
switch 1814 is subsequently filtered through an RC network (e.g.,
low pass filter) that is in series with switch 1814, and converted
in voltage-to-current converter V2I 1804 to generate the average
magnitude of the load current, Isub. In other embodiments wherein
the dynamic range of the integrator is not an issue, the average
load current magnitude need not be generated, and the load current
magnitude |I.sub.L| may be provided directly to polarity switch
1806.
After decoding, the receive signal RBS is separated (e.g.
demultiplexed) into data and status information in Demux 614. The
data portion may comprise six bits, for example, which may
subsequently be serialized into the receive bit stream, RxdBS. In
addition, the status bit STA may be used to form an 8-bit wide
status word.
Line Side Barrier Interface
FIG. 10 is a functional illustration of an embodiment of a Line
Side Barrier Interface (LSBI) 902. As illustrated, LSBI 902
comprises Rectifier 1002; Barrier Detection 1004; Encoder/Decoder
(ENDEC) 1006; Mode Detection 1008; and amplifier/comparator 1010.
Comparator 1010 generates and sends the transmitted Manchester
Encoded Data (MED) to the clock recovery loop. MED may be raw data
from the barrier or processed data generated in accordance with the
illustration of FIG. 15B to ease the task of clock recovery,
depending on the state of the clock recovery loop.
In one embodiment, the barrier transformer 106 and the
rectification scheme in Rectifier 1002 are such that 3V pulses from
the HIC 104 will become 6V pulses to the LIC 108. The 6V pulses are
rectified by the Rectifier 1002, which could be a diode bridge or
any other rectification scheme (e.g. active or passive), on pins
SCP and SCM of the transformer 106 to generate a positive supply
voltage, VPX, for the LIC 108.
Barrier Detection 1004 performs raw data detection from the signal
at the terminals, SCP and SCM, of the transformer.
In one embodiment, LSBI 902 identifies the state of operation by
monitoring the transmit data stream, TBS, coming across the barrier
from HIC 104 by checking the number of power pulses and the data
pulses or by checking voltage levels of the transmit data stream
(e.g., power pulses may be transmitted with a higher voltage than
data pulses). For instance, the modes of operation may comprise a
mixed mode and a data mode.
In Mixed mode, power transmission and full-duplex data transfer may
be time division multiplexed. From reset until the assertion of an
Off Hook command, HIC 104 may operate in a "Mixed Mode". During the
Mixed mode, the HIC 104 may supply power to LIC 108 across the
pulse transformer barrier. In some embodiments, HIC 104 may
continue to deliver power to LIC 108 even after the off hook
command is asserted.
In Data mode, transmit and receive data may be simultaneously and
continuously exchanged between the LIC 108 and HIC 104 at twice the
rate of Mixed mode as the power frames can now be used as data
frames.
Encoder/Decoder (ENDEC) 1006 performs decoding of the transmit bit
stream (TBS) into CTL and TxdBS and performs the reverse of DC
Balance Coding performed in 604. That is, the ENDEC 1006 recovers
TxdBS (see FIG. 6) on the line side. FIGS. 11A and 11B are
functional illustrations of Encoder/Decoder 1006 in accordance with
embodiments of the present invention.
As illustrated in both FIGS. 11A and 11B, transmit bit stream, TBS,
is Manchester decoded in block 1102 and then demultiplexed in block
1104 into a data portion and a control portion. The data portion is
processed through a DC Balance Decoder (reverse of DC Balance
Encoder discussed with respect to FIG. 5) in block 1106. The
resulting data may be serialized in block 1108 into the recovered
transmit bit stream, TxdBS. In addition, the control portion is
decoded in block 1110 to generate the control bit, CTL.
Encoder/Decoder 1006 also encodes the receive data, RxdBS, which
originates from Analog to Digital Converter (ADC) 908, and the
status bit, STA, to generate the composite signal RBS (=RxdBS+STA).
In blocks 1122 and 1124, the receive data, RxdBS, and the Status
bit, STA, may be encoded for transmission across the barrier.
Referring to the embodiment of FIG. 11A, the status bit, STA, may
be Manchester encoded in block 1124A and then combined with the
uncoded receive bit stream, RxdBS, in block 1122A to form RBS,
which is illustrated in FIG. 12A as "Encoded Rxdata". In this
embodiment, the encoding scheme first does Manchester encoding of
the Status bit into two bits in block 1124A and places one of the
bits at the beginning of three of six bits of data and the other at
the beginning of the remaining three of the same six data bits in
block 1122A. The resulting bit pattern is further illustrated
graphically in FIG. 12A. In this embodiment, special encoding of
the RxdBS bits is not required and thus not shown. Also, note that
a status bit of "0" is encoded in both the illustrations of FIGS.
12A and 12B. In contrast, if the status bit is "1" (i.e. STA=1),
the encoded data would have its bit pattern reversed. That is, a
"1" in the first position of the status bit and a value of "0" in
the second position of the status bit.
In another embodiment illustrated in FIG. 11B, both the status bit
(STA) and the receive data bit stream (RxdBS) are multiplexed in
block 1122B and then Manchester encoded within block 1124B to
generate the receive bit stream, RBS. The resulting bit pattern is
illustrated in FIG. 12B.
The formed received bit stream (i.e. RBS) is then transmitted to
the HIC. When HIC 104 detects the RBS, it frames the bits and
decodes the data accordingly. Thus, for instance into seven bits of
data--six bits of receive data, RxdBS, and one bit of STA, if the
RBS was formed in the LIC using the embodiment illustrated in FIG.
11A. Also, the data may be decoded into three bits of RxdBS and one
bit of STA if RBS was formed in the LIC using the embodiment
illustrated in FIG. 11B.
Clock Recovery
One factor facilitating bi-directional communication across the
barrier is having both the HIC and the LIC locked in time
(synchronized). For example, switch Rxd 302 in FIG. 3A is
preferably opened and closed at the beginning or the end of the
Manchester period. In other words Manchester edges in HIC should
line up closely with those of the LIC.
FIG. 13 is an illustration of a clock recovery circuit in
accordance with an embodiment of the present invention. As
illustrated, clock recovery in the LIC 108 may be performed by a
Phase Lock Loop (PLL) comprising a timing extraction block 1302 and
a clock multiply block 1304. Upon enablement, timing extraction
block 1302 determines the frequency range of the input MED (i.e.
Manchester Encoded Data) and properly sets up the Phase Lock Loop.
When the PLL locks onto the MED frequency, the signal LKD is
asserted and sent to LSBI 902.
The range of frequency associated with the input, MED, may vary
significantly. Thus, the clock recovery circuit is preferably
configured to deal with a wide frequency range.
To set up the clock recovery circuit, the HIC 104 may send a
preamble containing only clock and power pulses as shown in FIG.
15A. There can be an irregularity in the waveform at the boundaries
between power and data frames. The transformer driver for power and
data frames may be configured such that the Manchester codes
saddling the boundaries between power and data frames are matched.
This may be achieved, for example, using a dual mode super source
follower circuit.
In one embodiment, LSBI 902 first inverts the power pulses to make
them a true alternating preamble as shown in FIG. 15B. After
inversion, the pulse train becomes a seamless preamble pattern at
half the frequency of the Manchester clock, i.e. transitions only
occur at the rising edge of the Manchester clock. This makes the
initial locking process relatively easy. The Timing Extraction
circuit 1302 detects the approximate frequency range of the
inverted preamble. This information is then used by the PLL to
properly set the PLL parameters.
FIG. 14 is a detailed illustration of a PLL in accordance with an
embodiment of the present invention. The clock recovery PLL
comprises an edge trigger block 1402 (that generates a one-shot at
every edge of MED); Timing Recovery Manchester Encoder block (TRMC)
1404; switch 1406; phase detector (PFD) 1410; voltage controlled
oscillator gain determination block (Kvco Set) 1408; lock
determination block (LKD) 1412; voltage controlled oscillator (VCO)
1418; clock divider block (Div6) 1416; and Charge Pump (CP)
1414.
In one embodiment of the clock recovery circuit, there are three
steps involved in acquiring a clock (CLK) that is locked to
Manchester Encoded Data. The first step is to estimate the required
Kvco settings (Kvco 1408) for the PLL for a given input clock
(preamble) represented by the input MED. This may be accomplished
by enabling Kvco counters in the clock extraction block to start
counting MED edges for a specific period.
After counting is complete, the entire PLL is powered up and the
final result of the counter is used to set the Kvco control bits.
While counting both edges of the preamble, the generated double
input frequency signal at block 1402 may be used as the reference
frequency (FREF) to the PLL.
After setting the PLL Kvco control bits and powering up the entire
PLL, the PLL begins the process of locking to MED (still preamble).
When the PLL has successfully acquired lock, LKD signal goes high,
as determined in block 1412.
Once the LKD signal goes high, FREF to the PLL may switch from the
bi-directional one-shot 1402 to the output of Timing Recovery
Manchester Encoder block (TRMC) 1404, which selects only the valid
Manchester transition edges that are present at the constant rate
(of Manchester clock). Assertion of the signal LKD may also be used
to signal the LSBI 902 that it can start sending data instead of
preamble clock to the MED.
Finally, CLK is conveniently multiplied up from the Manchester
clock rate, e.g., six times. The rising edge of the recovered
Manchester clock is aligned with the valid data transition. The
recovered clock signal may then be used in all circuitry on the
line side requiring timing information (e.g., an ADC block 908 and
ENDEC block 1006).
Thus, a method and apparatus for detecting impedance modulation
have been described. Particular embodiments described herein are
illustrative only and should not limit the present invention
thereby. The invention is defined by the claims and their full
scope of equivalents.
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