U.S. patent number 5,319,258 [Application Number 07/956,943] was granted by the patent office on 1994-06-07 for programmable output drive circuit.
This patent grant is currently assigned to Samsung Semiconductor, Inc.. Invention is credited to J. Eric Ruetz.
United States Patent |
5,319,258 |
Ruetz |
June 7, 1994 |
**Please see images for:
( Certificate of Correction ) ** |
Programmable output drive circuit
Abstract
A programmable output driver circuit is provided having multiple
drive capabilities for optimising noise margins at different
frequencies. Several signal paths are designed in parallel, each
comprising a driver unit made up of a pull-down and a pull-up
transistor. Some of the paths can be disabled by NAND gates slowing
down the driver circuit to reduce the attendant noise at lower
frequencies. Different types of parallel structures can be
designed, allowing for variable rise and fall times of the output
signal, as well as skewed duty cycles.
Inventors: |
Ruetz; J. Eric (San Bruno,
CA) |
Assignee: |
Samsung Semiconductor, Inc.
(San Jose, CA)
|
Family
ID: |
24935058 |
Appl.
No.: |
07/956,943 |
Filed: |
October 5, 1992 |
Related U.S. Patent Documents
|
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
Issue Date |
|
|
730370 |
Jul 16, 1991 |
5153450 |
|
|
|
Current U.S.
Class: |
326/21; 326/82;
327/108; 327/379 |
Current CPC
Class: |
H03K
19/00361 (20130101) |
Current International
Class: |
H03K
19/003 (20060101); H03K 017/16 (); H03K
019/092 () |
Field of
Search: |
;307/475,443,270,542 |
References Cited
[Referenced By]
U.S. Patent Documents
Foreign Patent Documents
|
|
|
|
|
|
|
0253914 |
|
Jul 1986 |
|
EP |
|
1264470 |
|
Oct 1986 |
|
EP |
|
0315473 |
|
Nov 1988 |
|
EP |
|
59-158623 |
|
Jan 1985 |
|
JP |
|
1-284107 |
|
Feb 1990 |
|
JP |
|
2-58925 |
|
May 1990 |
|
JP |
|
3117020 |
|
May 1991 |
|
JP |
|
Other References
Emsworth, GB, Research Disclosure No. 313, "Programmable Impedance
Off-Chip Driver", May (1990) p. 370..
|
Primary Examiner: Westin; Edward P.
Assistant Examiner: Roseen; Richard
Attorney, Agent or Firm: Townsend and Townsend Khourie and
Crew
Parent Case Text
This is a continuation of application Ser. No. 07/730,370 filed
Jul. 16, 1991, now U.S. Pat. No. 5,153,450.
Claims
What is claimed is:
1. A programmable output driver circuit, comprising:
a first driver unit, coupled between an input and an output, having
a first drive capability;
a second driver unit, coupled to said input and said output in
parallel to said first driver unit, having a second drive
capability different from said first drive capability; and
a selector coupled to said second driver unit for selectively
enabling and disabling said second driver unit to add or not add
said second capability to said first capability, wherein said
selector has an associated delay time in adding said second drive
capability to said first drive capability, and said driver circuit
further comprises a delay circuit coupled between said input and
said first driver unit, for delaying an input signal to said first
driver circuit by said associated delay time so that application of
said first and said second drive capabilities is synchronized.
2. The driver circuit of claim 1 further comprising a memory for
storing selectable operating conditions, said memory activating
said selector for predetermined input conditions requiring a
combined drive capability.
Description
BACKGROUND OF THE INVENTION
The present invention relates to a high frequency output driver
circuit having a programmable drive capability that does not
compromise noise performance of the driver circuit at lower
frequencies.
Output drivers integrated as part of a larger circuit often act as
a source of noise through power supply coupling. The magnitude of
this noise is directly related to a frequency of operation of the
driver circuit. To be able to drive capacitive loads at high
frequencies, output driver circuit design includes providing an
output signal having fast rise and fall times. Achieving fast rise
and fall times requires devices with very large channel width to
length (W/L) ratios capable of sinking and sourcing large amounts
of current. As the rise and fall times of the output waveforms of
the output driver become faster, the output driver circuit
introduces increasingly higher level harmonics into the circuit
through the power supply pins, bond wire and lead frame inductance.
For operation at lower frequencies, the output waveform has more
time to reach a final value, allowing use of smaller and slower
devices handling lower amounts of current. This in turn results in
reduced noise levels for the output driver circuit and reduced
noise coupling for the larger circuit.
Therefore in applications with wide frequency ranges and high
frequency requirements, designers have either compromised the noise
performance at lower frequencies to obtain high frequency
operation, or compromised the frequency performance at higher
frequencies to obtain lower noise levels during the low frequency
operation.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an output
driver capable of driving various loads at a wide range of output
frequencies without sacrificing either noise margins or rise and
fall times of an output waveform.
According to the present invention, there are provided various
paths designed in parallel to route the output signal. Each path
consists of a driver unit with a specific drive capability.
Depending on the frequency of operation, a control signal can
selectively disable some of these paths. For high frequency
operation, enabling more paths provides additional drive capability
and speed. At lower frequencies, where rise and fall times may be
longer, disabling all parallel paths reduces the drive capability
and speed, thereby reducing the attendant noise coupled to the
entire system.
The number and size of these selectable parallel paths can vary
depending on the application. Read Only Memories (ROMs), in one
preferred embodiment, provide selection control signals to select
particular ones of the parallel paths to provide necessary current
levels without excessive noise levels. The combination of variable
number of paths and ROM programmability allows for a fully
customized design.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a circuit diagram of a programmable output driver with
two levels of operation: a default mode, and a high frequency
mode;
FIG. 2 is a block diagram of a ROM programmable output driver with
multiple levels of operation;
FIG. 3 is a circuit diagram of a two level programmable output
driver capable of skewing duty cycle of an output signal to above
50%; and
FIG. 4 is a timing diagram illustrating generation of a control
pulse for a pull-up transistor required in the skewing circuit.
DESCRIPTION OF THE PREFERRED EMBODIMENT
FIG. 1 is a basic circuit diagram of a programmable output driver
10 in accordance with the subject invention. An input signal is
coupled to an input of the driver 10, and is routed to an output
through two paths, one of which can be disabled by AND gates 16 and
18. Therefore the output driver 10 provides two levels of drive
capability: a default path consisting of driver unit 12, constantly
connected for lower frequencies, and a second path consisting of a
selectable driver unit 14 placed in parallel with driver unit 12,
only upon asserting the SEL input for higher frequency
operation.
During default operation the SEL input is low, resulting in a low
signal at outputs of both AND gates 16 and 18. This effectively
removes N-channel transistors MNS1 and MNS2, the pull-up and
pull-down transistors that form the selectable driver unit 14 from
the signal path. The remaining pull-up and pull-down N-channel
transistors MN1 and MN2 form the default driver unit 12 and are
always active. These devices are designed for desired performance
at frequencies up to a first particular frequency.
For higher frequency operations, the output signal requires a
faster rise and fall time. This faster transition speed is achieved
by setting the SEL input to a high level allowing the signal to
pass through the AND gates 16 and 18 driving the select transistors
MNS1 and MNS2. These select transistors are placed in parallel to
the default driver unit 12 transistors resulting in an increased
effective size equal to the sum of the two devices. In this case as
the sizes of the two devices are equal, the drive capability is
doubled. This enables the circuit to drive the same capacitive load
at frequencies up to a second particular frequency beyond the first
particular frequency. For example, in a preferred embodiment having
an output range of about 10 MHz to about 140 MHz, the first
particular frequency is in the range of about 60 MHz to about 80
MHz. The second particular frequency of 140 MHz provides acceptable
rise and fall times.
To avoid differing delay times associated with each signal path,
delay blocks 20 and 22, comprised of two inverters connected in
series, are placed in the default signal path. The input signal is
coupled to the input of the driver unit 12 via the delay blocks 20
and 22. The two inverters in each delay block are designed to match
the delay introduced in the selectable driver unit 14 path by the
AND gates 16 and 18.
FIG. 2 is a block diagram of a ROM programmable output driver with
multiple drive capabilities. The ROM stores a program controlling
the SEL signals based on the frequency of operation. The designer
will calculate desired threshold frequencies at which additional
drive is required and enter the values into the program. The user
then selects a particular frequency of operation Fo, and informs
the ROM through an address input. The program is basically in the
form of a look-up table and depending on which range of frequencies
Fo falls in, the proper SEL bit(s) will turn on.
In some applications, skewing of the duty cycle of the output
signal may be desirable. FIG. 3 is a circuit diagram of a
programmable output driver capable of skewing duty cycle of an
output signal to above 50%. A P-channel transistor MPS1 connecting
the output of the driver 10 to a supply voltage is turned on by a
narrow control pulse generated at each rising edge of the input
signal. Thus, only rise times, and not fall times, are affected.
Skewing of fall times only could be accomplished by similar
modification to the sinking transistor drivers.
FIG. 4 is a timing chart illustrating how the control pulse is
generated. An output of a 3-input NAND gate 24 is coupled to an
input of a delay block 28. The output of delay block 28 drives the
gate of MPS1. A first input of NAND 24 is coupled to an enable
signal ENBL such that the output of NAND 24 remains high, and
therefore MPS1 off, as long as ENBL is held low. A second input of
NAND 24 is coupled to the input signal. The output of AND 16 is
delayed by a fixed delay block 30 and coupled to a third input of
NAND 24. This fixed delay block 30 consists of three inverters
connected in series and therefore inverts the signal as well as
delaying it by a fixed time delay. Thus, the three inputs to NAND
24 consist of ENBL, the input signal, and the inverted and delayed
version of the input signal.
The output of NAND 24 connected as described above, is therefore a
negative pulse at each rising edge of the input signal when both
SEL and ENBL signals are on. This negative pulse turns on MPS1 for
a length of time equal to the fixed delay of block 30 plus the
delay introduced by AND 16, at every rising edge of the input
signal. With MPS1 turned on, the output of the driver 10 rises
faster to supply voltage compared to the normal operation. Since
the rise time is decreased while the fall time is unaffected, the
resulting output signal would have a duty cycle greater than
50%.
This design offers great flexibility as additional selectable
driver units can be added in parallel to further customize the
noise-frequency performance. Also, different size pull-up or
pull-down transistors can be utilized as described above to skew
the duty cycle of the output signal in either direction.
In conclusion, the present invention offers an output driver
circuit operating over a wide range of frequencies without
adversely affecting noise margins. While the above is a complete
description of the preferred embodiments of the present invention,
it is possible to use various alternatives, modification and
equivalents. For example, instead of N-channel pull-up transistors,
P-channel devices can be used enabling the output waveform to swing
closer to the supply voltage if desired. Faster fall time during a
short period corresponding to the falling edge can be achieved,
utilizing a control pulse and an N-channel pull-down device similar
to the P-channel version described above for the rising edge.
Therefore, the above description does not limit the scope of
invention. The appended claims define this scope.
* * * * *