U.S. patent number 4,541,067 [Application Number 06/376,895] was granted by the patent office on 1985-09-10 for combinational logic structure using pass transistors.
This patent grant is currently assigned to American Microsystems, Inc.. Invention is credited to Sterling R. Whitaker.
United States Patent |
4,541,067 |
Whitaker |
September 10, 1985 |
Combinational logic structure using PASS transistors
Abstract
PASS transistors are used to reduce the layout complexity of
logic circuits by using PASS transistors connected to pass a first
and second input function to an output node in response to selected
CONTROL signals, thereby to generate a selected output function on
the output node. The PASS transistor comprises a transistor capable
of passing an input function in response to a CONTROL signal
applied to the transistor thereby to generate an output function
related to the input function. In general, the input function
comprises less than all of a set of input variables and the CONTROL
function comprises one or more of the remainder of the set of input
variables.
Inventors: |
Whitaker; Sterling R.
(Chubbuck, ID) |
Assignee: |
American Microsystems, Inc.
(Santa Clara, CA)
|
Family
ID: |
23486945 |
Appl.
No.: |
06/376,895 |
Filed: |
May 10, 1982 |
Current U.S.
Class: |
326/113; 326/52;
326/53; 708/230 |
Current CPC
Class: |
G06F
7/50 (20130101); H03K 19/09441 (20130101); H03M
11/02 (20130101); H03K 23/00 (20130101); H03K
19/215 (20130101) |
Current International
Class: |
G06F
7/50 (20060101); G06F 7/48 (20060101); H03K
19/0944 (20060101); H03K 19/20 (20060101); H03K
23/00 (20060101); H03M 11/02 (20060101); H03K
19/21 (20060101); G06F 007/52 (); G03K
019/20 () |
Field of
Search: |
;364/784,489,490,491,716
;340/146.2 ;307/455,471,472 |
References Cited
[Referenced By]
U.S. Patent Documents
Primary Examiner: Malzahn; David H.
Attorney, Agent or Firm: Madden, Jr.; Walter J. MacPherson;
Alan H. Caserza; Steven F.
Claims
What is claimed is:
1. A logic circuit including as its basic element PASS transistors,
wherein each PASS transistor comprises an input lead, an output
lead and a control lead for controlling the passing of signals from
said input lead to said output lead, said logic circuit
comprising:
an output node connected to said output leads;
at least two PASS transistors;
means for supplying a first input function to said input lead of
one of said transistors;
means for supplying a second input function to said input lead of
another of said transistors; and
means for supplying selected control signals to said control leads
of said transistors, to generate on said output node a selected
output function related to said first and/or second input
functions;
wherein said first input function is the reference voltage
V.sub.SS, said second input function is B, one of said selected
control signals is A, another of said selected control signals is
A, and said structure thereby represents an AND function.
2. A logic circuit including as its basic element PASS transistors,
wherein each PASS transistor comprises an input lead, an output
lead and a control lead for controlling the passing of signals from
said input lead to said output lead, said logic circuit
comprising:
an output node connected to said output leads;
at least two PASS transistors;
means for supplying a first input function to said input lead of
one of said transistors;
means for supplying a second input function to said input lead of
another of said transistors; and
means for supplying selected control signals to said control leads
of said transistors, to generate on said output node a selected
output function related to said first and/or second input
functions;
wherein said first input function is the supply voltage VDD, said
second input function is B, one of said selected control signals is
A, another of said selected control signals is A, and said
structure thereby represents a NAND function.
3. A logic circuit including as its basic element PASS transistors,
wherein each PASS transistor comprises an input lead, an output
lead and a control lead for controlling the passing of signals from
said input lead to said output lead, said logic circuit
comprising:
an output node connected to said output leads;
at least two PASS transistors;
means for supplying a first input function to said input lead of
one of said transistors;
means for supplying a second input function to said input lead of
another of said transistors; and
means for supplying selected control signals to said control leads
of said transistors, to generate on said output node a selected
output function related to said first and/or second input
functions;
wherein said first input function is B, said second input function
is the supply voltage VDD, one of said selected control signals is
A, another of said selected control signals is A and said structure
represents an OR function.
4. A logic circuit including as its basic element PASS transistors,
wherein each PASS transistor comprises an input lead, an output
lead and a control lead for controlling the passing of signals from
said input lead to said output lead, said logic circuit
comprising:
an output node connected to said output leads;
at least two PASS transistors;
means for supplying a first input function to said input lead of
one of said transistors;
means for supplying a second input function to said input lead of
another of said transistors; and
means for supplying selected control signals to said control leads
of said transistors, to generate on said output node a selected
output function related to said first and/or second input
functions;
wherein said first input function is B, said second input function
is the reference voltage VSS, one of said selected control signals
is A, another of said selected control signals is A and said
structure represents a NOR function.
5. The method of constructing a logic circuit to represent a given
logical function, said circuit using as its basic element the PASS
transistor, said PASS transistor having an input lead, an output
lead and a control lead controlled by a control function, said
method comprising:
establishing a truth table of the desired logic function, said
truth table depicting the state of the output variable or variables
for each state of the input variables including;
the step of establishing said truth table including entering into
said truth table for each input state the input variables which,
when passed to the output lead of a PASS transistor, yield the
desired output variable or variables, said input variables
comprising the PASS function for that state;
entering the PASS function for each state of the input variables
into a modified Karnaugh map wherein each state of the modified
Karnaugh map contains the particular input variables which yield
the desired output variable, and particular variables being called
the PASS function for that state of input variables;
identifying the identical PASS variables in each PASS function for
each state of input variables such that every state has at least
one PASS variable identified;
identifying a control function among the input variables which is
previously identified, for controlling said PASS transistor;
and
constructing a logic circuit using said PASS transistors in
accordance with said identified PASS variables and said control
function.
6. The method of claim 5 wherein said step of identifying a control
function comprises:
using the identity that
a PASS transistor which has a control function identical to its
PASS function passes a high level signal when made conductive by
the control function; and
a PASS transistor which has a control function the inverse of its
PASS function passes a low level signal when made conductive by the
control function, to make the PASS function independent of the
control function among said input variables.
7. The method of constructing a logic circuit to represent a given
logical function, said circuit using as its basic element the PASS
transistor, said PASS transistor having an input lead, an output
lead and a control lead controlled by a control function, said
method comprising:
establishing a truth table of the desired logic function, said
truth table depicting the state of the output variable or variables
for each state of the input variables;
the step of establishing said truth table including entering into
said truth table for each input state the input variables which,
when passed to the output lead of a PASS transistor, yield the
desired output variable or variables, said input variables
comprising the PASS function for that state;
identifying the identical PASS variables in each PASS function for
each state of input variables such that every state has at least
one PASS variable identified;
identifying a control function among the input variables which is
independent of the identical PASS variables previously identified,
for controlling said PASS transistor; and
constructing a logic circuit using said PASS transistors in
accordance with said identified PASS variables and said control
function.
8. The method of claim 7 wherein said step of identifying a control
function comprises:
using the identities that
a PASS transistor which has a control function identical to its
PASS function passes a high level signal when made conductive by
the control function and
a PASS transistor which has a control function the inverse of its
PASS function passes a low level signal when made conductive by the
control function, to make the PASS function independent of the
control variables.
9. A logic circuit including as its basic element PASS transistors
wherein each PASS transistor comprises an input lead, an output
lead and a control lead for controlling the passing of signals from
said input lead to said output lead, said logic circuit comprising
an output node connected to said output lead;
at least two PASS transistors;
means for supplying a first input function to said input lead of
one of said transistors, said first input function being J;
means for supplying a second input function to said input lead of
another of said transistors, said input function being K; and
means for supplying selected control signals to said control leads
of said transistors, said control signals being Q and Q, said input
functions and said selected control signals being selectively
combined in said PASS transistors to generate on said output node
an output function representing a J/K flip flop.
Description
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to logic circuits and in particular to a
logical element known as a PASS transistor and to logic circuits
formed using PASS transistors so as to substantially reduce the
number of active devices required to implement logic functions.
2. Prior Art
Boolean logic expressions may be realized through classical logic
design methods with networks of combinational logic. Logic networks
using MOS technology are often formed with NAND, NOR and Inversion
gates since these structures are easily implemented. The PASS
transistor is another common MOS structure. Classical logic design
methods, however, do not result in networks of PASS
transistors.
FIG. 1a shows the PASS transistor with its logical function. When
the gate or control electrode 13 to PASS transistor 10 is asserted
(and by "asserted" is meant driven to a voltage so as to form a
conductive path between input lead 11 and output lead 12),
transistor 10 passes the logic state at input lead 11 to output
lead 12. The input and output leads of an MOS transistor may be
arbitrarily chosen because an MOS transistor is bidirectional. For
convenience, the input lead shall hereafter be defined as the
terminal driven by the source of a logic state. The output lead 12
of PASS transistor 10 typically applies the passed logic state to
the input lead of another series connected logic structure. Output
leads of a number of PASS transistors may be joined to drive the
same input of a logic structure provided that all PASS transistors
whose controls are asserted are passing the same logic state. The
use of PASS transistors as bidirectional transmission gates is
described in an article entitled "VLSI: A New Frontier for Systems
Designers" published in the Jan. 1982 Computer Journal of the IEEE
by Douglas G. Fairbairn, which, is hereby incorporated by
reference.
SUMMARY
In accordance with this invention, logic networks are fabricated
using PASS transistors so as to maximize the regularity of the
resulting logic circuitry. The resulting logical networks give
significant topological, power and speed advantages over prior art
logic circuits when used to form combinational logic.
The use of the PASS transistor as a logic element yields several
advantages over the NAND, NOR and inverter structures used in prior
art logic circuits such as MOS-integrated logic circuits. First,
the PASS transistor dissipates no significant steady state power.
Second, arrays of PASS transistors form structures of regular
topology often consuming less area for a given logical function
than consumed by NAND, NOR and inverter arrays. Third,
combinational logic formed with PASS transistors often reduces the
signal propagation delay through a network.
While the major disadvantage of the PASS transistor is that the
voltage level of the logic high signal on its output lead is
degraded due to the characteristics of the field effect transistor
used as the PASS transistor, this can be overcome by careful
circuit design. However, after passing a logic high level through
one PASS transistor, no significant further degradation of voltage
level occurs when the signal is passed through N additional PASS
transistors assuming no PASS transistor control input is driven by
the output of another PASS transistor.
BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. 1a and 1b illustrate a PASS transistor and the truth table
for that transistor;
FIGS. 2a through 2d illustrate the logical function Z=AB+AB
implemented using AND gates, a NOR gate and an inverter, and the
truth table, Karnaugh plot and Boolean equation associated with
that structure;
FIGS. 3a through 3d illustrate the truth table, the Karnaugh map,
the looping of the PASS functions for an equivalence gate and the
resulting PASS transistor network, respectively, for the same
logical function shown in FIG. 2c;
FIGS. 4a and 4b illustrate two functional identities which are
employed to make logic networks using PASS transistors;
FIG. 5 illustrates in schematic block diagram form a magnitude
comparator structure of well known design;
FIG. 6 illustrates the truth table for the magnitude comparator
shown in FIG. 5;
FIG. 7 illustrates the Karnaugh map and the looping of the PASS
functions necessary to produce the logical functions required by
the truth table of FIG. 6;
FIGS. 8a and 8b illustrate the PASS transistor implementation of
the logic circuit necessary to implement the truth table of FIG. 6
and the silicon layout (in accordance with the conventions shown in
FIGS. 16d and 16f) of the transistors shown in FIG. 8a,
respectively;
FIGS. 9a, 9b and 9c illustrate, respectively, the truth table,
Karnaugh map with PASS variables looped and circuit diagram of the
resulting logical network for an AND gate;
FIGS. 10a, 1Ob and 10c illustrate, respectively, the truth table,
Karnaugh map with PASS functions looped and the logic circuit
implemented using PASS transistors for a NAND gate;
FIGS. 11a, 11b and 11c illustrate, respectively, the truth table,
Karnaugh map with PASS functions looped and the logic circuit
implemented using PASS transistors for an OR gate;
FIGS. 12a, 12b and 12c illustrate, respectively, the truth table,
Karnaugh map with PASS functions looped and the logic circuit
implemented using PASS transistors for a NOR gate;
FIGS. 13a, 13b and 13c illustrate, respectively, the truth table,
Karnaugh map with PASS functions looped and the logic circuit
implemented using PASS transistors for an Exclusive OR gate;
FIGS. 14a, 14b and 14c illustrate, respectively, the truth table,
Karnaugh map with PASS functions looped and the logic circuit
implemented using PASS transistors for an Exclusive NOR gate;
FIGS. 15a, 15b, 15c and 15d illustrate, respectively, the block
diagram, the truth table, the Karnaugh map with PASS functions
looped and the logic circuit implementation using PASS transistors,
respectively, for the carry generator of a full adder;
FIGS. 16a, 16b and 16c illustrate, respectively, the truth table,
Karnaugh map with PASS functions looped and the logic circuit
implemented using PASS transistors for a summing network of a full
adder;
FIG. 16d illustrates the layout of the circuit shown in FIG. 16c
for the full adder structure;
FIG. 16e illustrates the relationship of the structure of FIG. 16d
to a complete adding circuit;
FIG. 16f illustrates the way in which an MOS transistor is
illustrated in FIG. 16d;
FIGS. 17a, 17b, 17c and 17d (wherein the components of FIG. 17d are
labelled in accordance with the conventions of FIGS. 16d and 16f)
illustrate the truth table, the Karnaugh map with the PASS
functions circled, the logic circuit implementation using PASS
transistors, and the schematic top view of the semiconductor N
channel MOS transistor implementation of the circuit of FIG. 17c,
respectively;
FIGS. 17e and 17f illustrate the PASS variable to CONTROL variable
transformations used in implementing the structure of FIG. 17c;
FIGS. 17g and 17h (wherein the components of FIG. 17h are labelled
in accordance with the conventions of FIGS. 16d and 16f) illustrate
the logic circuitry and the layout of this logic circuitry in N
channel MOS technology after the transformations illustrated in
FIGS. 17e and 17f have been applied to the circuit of FIG. 17c;
FIG. 18a, illustrates a block diagram for a binary up/down
counter;
FIGS. 18b, 18c, 18d and 18e illustrate, respectively, the truth
table, the Karnaugh map with the input PASS functions looped and
the circuit implementation of the Karnaugh map;
FIG. 19a illustrates in schematic block form a binary up
counter;
FIGS. 19b, 19c, 19d, 19e and 19f illustrate, respectively, the
truth table, the Karnaugh map with PASS functions looped, the
circuit implementation and the N channel MOS transistor
implementation for the binary up counter of FIG. 19a;
FIGS. 20a, 20b, 20c and 20d illustrate, respectively, the truth
table, the Karnaugh map with PASS functions looped, the circuit
implementation and the N channel MOS transistor implementation for
a JK flip-flop;
FIG. 21a illustrates in schematic block diagram form a shift
left/hold circuit;
FIGS. 21b, 21c, 21d and 21e illustrate, respectively, the truth
table, the Karnaugh map with PASS functions circled, the circuit
implementation and the N channel MOS transistor implementation of
the shift left/hold structure.
DETAILED DESCRIPTION
The classical design of combinational digital logic circuits may be
illustrated by the following example. First a truth table for the
desired logical function is formed. FIG. 2a shows the truth table
for an Exclusive NOR or equivalence gate. When input A is equal in
value to input B, the output assumes a logic one state. When input
A is not equal in value to input B, the output assumes a logic zero
state. The truth table information is then entered into a Karnaugh
map. The output function is reduced and read from the Karnaugh map
using looping techniques. A Karnaugh map reduction of the Exclusive
NOR truth table is shown in FIG. 2b, with the Boolean expression
shown in FIG. 2c. The function is then implemented using logic AND
function and OR function gates. The implementation of this function
with prior art logic structures requires two AND functions and one
OR function. A possible MOS configuration has two nodes which
dissipate power, two gate delays and consists of 7 transistors.
The technique for designing combinational logic which results in
networks of PASS transistors will now be illustrated. The truth
table in FIG. 3a shows that the output function Z=AB+AB may be
obtained by passing the input variables and/or their inversions.
For example, in the first state of the truth table, input variables
A and B are both low and the output variable Z is high. Thus Z may
be formed by passing the inversion of A or the inversion of B (i.e.
A or B). In the second state A is low and B is high. Since Z is
low, Z may be formed by passing A or the inverse of B (i.e. A or
B). The PASS functions of the other two states are similarly
obtained and shown in the truth table in FIG. 3a. These PASS
functions are then entered into the appropriate states of a
Karnaugh map as illustrated in FIG. 3b. Note that the PASS
formations replace the output signals in a normal Karnaugh map.
Identical passed variables are identified in adjacent states on the
Karnaugh map and then looped together as shown in FIG. 3c to reduce
the CONTROL functions. These loopings may use normal Karnaugh map
reduction techniques with the following rules. First, a variable
must be passed in every "care" state of the map, since the output
signal from a PASS transistor is undefined when its control input
is low. (A "care" state is an input state for which the output
state must be defined and is often referred to simply as a
"state".) Second, more than one variable may be passed in each
state, since the PASS function guarantees that the passed variables
are the same logic level in a given state. Third, once a don't care
state has been included in a loop, the pass function is established
for that state.
A possible mapping for the equivalence gate using PASS transistors
is to pass the inverse of B when A is low and to pass B when A is
high. This mapping is shown in FIG. 3c. A is the CONTROL function
that passes the PASS function B and A is the CONTROL function that
passes the PASS function B. The PASS transistor network obtained is
shown in FIG. 3d.
The PASS transistor Exclusive NOR shown in FIG. 3d dissipates no
significant steady state power, has one PASS transistor delay and
consists of only two transistors. Thus a substantial power, speed
and area savings over the classical logic design methods is
realized.
The area advantage of one circuit configuration over another is not
always obvious from the logic or schematic diagrams. Also a lower
transistor count does not guarantee that less silicon area will be
used to lay out a circuit since electrical interconnect area
requirements are not represented by transistor count. Both
transistor count and regularity must be considered when comparing
two circuit configurations for area advantages. Network regularity
is a concept described, for example, in Chapter 3.1 of
"Introduction to VLSI Systems" by Carver Mead and Lynn Conway
published by Addison Wesley Publishers, 1980.
Maximum topological regularity for an array of PASS transistors is
established if the intersection of the set of control variables
with the set of passed variables is the null set. This allows
passed variables to flow in one direction while the control
variables flow at right angles. (A "CONTROL" variable is the input
variable which drives the control terminal of a PASS transistor. A
"PASS" variable is the input variable which drives the input
terminal of a PASS transistors and which is passed to the output
terminal when the PASS transistor is turned on.) Regularity may be
maximized in the CONTROL function if the CONTROL functions can be
looped such that they are functions of only the control variables.
Regularity in the PASS function may be maximized by making the PASS
function independent of the control variables. This independence
may be established through the use of the following identities. A
PASS transistor whose input is variable X and whose control is also
X always passes a one. This is equivalent to a PASS transistor
whose input is high and whose control is X as shown in FIG. 4a.
Similarly, a PASS transistor whose input is X and whose control is
X always passes a zero. This is equivalent to a PASS transistor
whose input is low and which is controlled by X. FIGS. 4a and 4b
summarize these equivalences.
The iterative combinational array is a class of combinational logic
for which the area of one circuit configuration versus another may
easily be compared. Area may be compared by drawing the layout of
one element of the array.
A useful circuit illustrative of iterative combinational arrays is
the digital magnitude comparator. The magnitude comparison of two
digital words A=A.sub.n-1, A.sub.n-2 . . . A.sub.i . . . A.sub.o
and B=B.sub.n-1, B.sub.n-2 . . . B.sub.1 . . . B.sub.o is
accomplished by comparing the i.sub.th bits and the results of all
more significant bit comparisons. A comparison must produce three
pieces of information to be complete: A>B, A=B and A<B, but
any one may be derived from the other two. It may be shown that
A>B and A<B are good choices to implement. FIG. 5 shows the
configuration of the comparison where C.sub.i is high indicating
A>B if either (A.sub.i >B.sub.i and D.sub.i+1 =0), or
(C.sub.i+1 =1) and D.sub.i is high indicating A>B if either
(D.sub.i+1 =1) or (A.sub.i >B.sub.i and C.sub.i +1 =0).
The first step in designing the magnitude comparator is to
establish a truth table as illustrated in FIG. 6. The possible
passed variables are then added to the truth table to define the
PASS functions for each state and these passed variables are
entered into a modified Karnaugh map. (In simple cases, where the
identical pass variables associated with different states can be
identified from the truth table, the modified Karnaugh map can be
omitted). Groups of passed variables are then ready to be looped
(i.e. identified and circled for ease of reference). Since
C.sub.i+1 and D.sub.i+1 influence directly C.sub.i and D.sub.i,
respectively, these are good choices for passed variables. If the
Karnaugh map is looped as shown in FIG. 7, the CONTROL functions
are functions of only variables A.sub.i and B.sub.i and the PASS
functions C.sub.i+1 and D.sub.i+1 are independent of A.sub.i and
B.sub.i. The circuit schematic of the PASS transistor array is
shown in FIG. 8a and the integrated circuit layout in N channel MOS
technology is shown in FIG. 8 b. In FIG. 8b, an MOS transistor is
depicted by the crossing of two perpendicular lines and a
conductive crossunder is depicted by a dark rectangle. The gate
electrodes are the vertical lines labeled A.sub.i, A.sub.i, B.sub.i
and B.sub.i and the horizontal lines labeled C.sub.i+1 and
D.sub.i+1 comprise diffused conductive lines and source and drain
regions.
The basic design method for constructing a logic circuit using the
PASS transistor as the basic element is as follows:
1. Establish a truth table of the desired function.
2. Enter the PASS function into the truth table (the PASS function
is an input variable or its inverse which is passed to the output
lead of the PASS transistor to yield the desired output
signal).
3. Enter the PASS function into a modified Karnaugh map wherein
each state of the modified Karnaugh map contains the particular
input variables (called the PASS function) which yield the desired
output variable.
4. Loop (i.e. identify or group) the identical PASS variables in
each PASS FUNCTION such that every care state (a care state is one
combination of input variables where the output variable must be
defined) has at least one PASS variable looped and such that the
CONTROL function (i.e., the function that controls the gate of the
PASS transistor) is independent of the PASS variables.
5. Use the identities shown in FIGS. 4a and 4b to make the PASS
function independent of CONTROL variables.
6. Draw the PASS transistor network.
FIGS. 3a through 3d, discussed above, illustrate this procedure. As
explained above, in some cases, step 3 can be omitted.
FIGS. 9a, 9b and 9c illustrate, respectively, this method for
specifying the PASS transistor logic circuit representing an AND
gate. As shown in FIG. 9c, a PASS transistor logic circuit is
implemented using only two PASS transistors as compared to three to
five transistors using the prior art implementation.
Note that in the logic circuit of FIG. 9c, the PASS function A is
replaced with V.sub.SS (the circuit ground or reference voltage) in
accordance with the identity of FIG. 4b.
FIGS. 10a, 10b and 10c illustrate, respectively, the truth table,
Karnaugh plot and logic circuit implemented using PASS transistors
for a NAND gate. Again, the inherent simplicity of the logic
circuit utilizing PASS transistors in accordance with this
invention is apparent.
Note that in the logic circuit of FIG. 10c, the PASS function A is
replaced with V.sub.DD (the supply voltage) in accordance with the
identity of FIG. 4a.
FIGS. 11a, 11b and 11c illustrate, respectively, the truth table,
Karnaugh plot and logic network constructed using PASS transistors
of an OR gate. In the logic circuit of FIG. 11c, the PASS function
A has been replaced with the supply voltage V.sub.DD in accordance
with the identity of FIG. 4a.
FIGS. 12a, 12b and 12c illustrate, respectively, the truth table,
Karnaugh plot and logic circuitry of a NOR gate constructed using
PASS transistors. In the logic circuit of FIG. 12c, the PASS
function A has been replaced with the reference voltage V.sub.SS in
accordance with the identity of FIG. 4b.
FIGS. 13a, 13b and 13c illustrate, respectively, the truth table,
Karnaugh plot and logic circuit constructed using PASS transistors
of an exclusive OR gate.
FIGS. 14a, 14b and 14c illustrate, respectively, the truth table,
Karnaugh plot and logic circuit constructed using PASS transistors
of an exclusive NOR gate.
Each of the structures shown in FIGS. 9c, 10c, 11c, 12c, 13c and
14c uses only two PASS transistors. Each PASS transistor is
controlled either by the A or A signal. Each of the logic circuits
is capable of producing an appropriate output state in response to
any one of the four different possible input states of the two
input variables A, B. In FIGS. 9c, 10c, 11c and 12c, none of the
PASS variables are related to the CONTROL variables as a result of
use of the identities of FIGS. 4a and 4b. The result is an inherent
simplicity in each of the circuits.
FIGS. 15a, 15b, 15c and 15d illustrate the implementation of a full
adder using the methodology and rules of this invention. The carry
associated with the full adder (FIG. 15d) can be implemented using
eight (8) PASS transistors as opposed to a much more complex
implementation using standard prior art logic components as
illustrated, for example, in FIG. 7-3 on page 123 of "Introduction
to the Basic Computer" by Donald Eadie, published in 1968 by
Prentice-Hall, Inc., Inglewood Cliffs, N.J., which is hereby
incorporated by reference. The sum circuit is formed using another
eight (8) PASS transistors and is shown in FIGS. 16a, 16b and 16c
which illustrate the truth table, Karnaugh plot, and PASS
transistor implementation, respectively, of a summing network.
FIG. 16d illustrates the layout of the implementation of the
circuitry shown in FIG. 16c in terms of PASS transistors. The
regularity and orthogonality of the CONTROL functions and PASS
functions is readily apparent from this description. The structure
is implemented using N channel MOS transistors and the different
component layers are indicated as shown by the key associated with
the Figure. The polysilicon (denoted as "poly") comprises the gate
electrodes of the N channel MOS transistors and the diffusion
comprises the source and drain regions of these transistors as well
as the conductive interconnects between the source and drain
regions of adjacent transistors.
Thus, in FIG. 16d, which shows the carry portion of a full adder
15d, the sum network 16c and a complementary carry portion of a
full adder derived from the full adder of 15d, the structure 16d is
laid out using N+ diffusions (denoted by the line with an X)
polycrystalline silicon (denoted by the straight line) and metal
(denoted by the straight line with a cross mark). Deep depletion
buried cross unders are denoted as dark rectangles. The buried
cross unders serve as conductive paths for current. The MOS
transistor is denoted schematically as shown in FIG. 16f wherein
the polysilicon gate line is orthogonal to an N+ diffusion line.
Underneath the polycrystalline silicon gate in an N+ transistor is
a channel region, the conductivity of which is controlled by the
signal level on the polycrystalline silicon line. The orthogonality
of the layout is apparent from FIG. 16d. FIG. 16d represents one
portion of an 8-bit adding circuitry and is designed to mate
topologically with adjacent portions of the circuitry as shown in
FIG. 16f.
The conventions described above as applicable to FIG. 16d apply
equally to FIGS. 8b, 17d, 17h and 19f.
FIGS. 17a and 17b illustrate the truth table and the modified
Karnaugh map for a priority encoder. The modified Karnaugh map in
FIG. 17b is in two parts. One part illustrates the particular PASS
functions which can be used to obtain the output D. However, the
mapping illustrates that for the input variables AB having the
values 00 or 01 and the input variable C equal to 0, the PASS
function is B to yield the output function D. For the value of C
equal to 1 and the values of AB equal to either 00 or 01, the PASS
function necessary to yield the value of D can be either C as shown
looped, or A. For the values of AB=11 and 10, and either value of
C, the PASS function to yield the value of D is A.
A similar analysis for the output variable E is shown in the second
part of the modified Karnaugh map of FIG. 17b. The particular logic
shown is implemented in circuit form as shown in FIG. 17c and has a
layout as shown in FIG. 17d. The layout of FIG. 17d is keyed
identically to that of FIG. 16d. The key to the layout in FIG. 16d
applies equally to that in FIG. 17d and to the other drawings such
as shown in FIGS. 8b, 17h and 19f in this specification.
The PASS variables can then be transformed as shown in FIG. 17e and
17f to simplify the structure shown in FIG. 17d to form the circuit
shown in FIG. 17g. The circuit in FIG. 17g is substantially simpler
in terms of topological layout although it contains 16 transistors
to the 10 shown in FIG. 17c. The 16 transistors shown in FIG. 17g,
however, allow a more rational arrangement of the voltage power
lines VDD, VSS and the signal input lines A, A, B, B, and C, C.
FIG. 17h illustrates schematically the actual layout of the PASS
transistors shown in FIG. 17g. The comparison between FIG. 17c
illustrates the type of trade-offs available using the logic system
described herein.
FIG. 18a illustrates the schematic block diagram of a binary
up/down counter. The truth table for this counter is illustrated in
FIG. 18b. Input variables D, T.sub.i-1 and Q.sub.i control the
state of the output variables D.sub.i and T.sub.i. The modified
Karnaugh map for output variable D.sub.i is shown in FIG. 18c and
for output variable T.sub.i is shown in FIG. 18d. The particular
variables looped to provide the PASS function for generating the
output variable D.sub.i are shown to be the variable T for Q.sub.i
=0 and all values of the variables D and T.sub.i-1, and the
variable T for Q.sub.i =1 and all values of D and T.sub.i-1. The
output variable T.sub.i is generated by the looped PASS functions
as illustrated in FIG. 18d. The structure to implement the truth
table is as shown in FIG. 18e. Note that for all values of the
variables D and T.sub.i-1 and for Q.sub.i =0, the output function
D.sub.i is generated by passing the T input signal with the Q
control signal. The output variable D.sub.i for Q=1 and all values
of D and T.sub.i-1 is generated by passing the input signal T with
the Q gate control signal. This structure is shown as implemented
in the top two lines of the circuit of FIG. 18e. The T.sub.i output
variable is generated by four paths of functions reflecting the
four different possible sets of CONTROL functions and PASS
functions necessary to generate all possible combinations of
T.sub.i output signals. For values of DT.sub.i-1 equals 11 or 10
and Q.sub.i equal 0, the T.sub.i-1 input signal is passed by the
transistors 184 and 185 controlled by the Q.sub.i CONTROL signal
and the D CONTROL signal, respectively, and for DT.sub.i-1 equals
00 or 01 and Q.sub.i equals 1, by transistors 182 and 183
controlled by the Q.sub.i input signal and the D input signal,
respectively. The Q.sub.i input signal is also passed by
transistors 186 and 187 controlled by the Q and the D signals,
respectively, when Q=0 or VSS, and the Q input signal (which is
equivalent to V.sub.SS by the transformation of FIG. 4b) is passed
by transistors 188 and 189 controlled by the gates driven by
Q.sub.i and D when Q.sub.i =1 or Q.sub.i =VSS.
FIG. 19a illustrates in schematic block diagram form the input and
output signals to and from a binary up counter.
FIG. 19b gives the truth table for the input variables T.sub.i-1
and Q.sub.i and their relationship to the output variables D.sub.i
and T.sub.i. FIGS. 19c and 19d give the modified Karnaugh plots for
the output variables D.sub.i and T.sub.i, respectively, as a
function of the input variables T.sub.i-1 and Q.sub.i.
FIG. 19e illustrates the circuit implementation of the logic using
the PASS transistors of this invention derived using the input
variables T.sub.i-1 and Q.sub.i wherein Q.sub.i as shown in
Karnaugh plot 19d has only the value VSS per the equivalent circuit
of FIG. 4b.
FIG. 19f illustrates the layout schematically of the circuit shown
in FIG. 19e.
FIG. 20a gives the truth table for a JK flip-flop with inputs JK
and Q and output D.
FIG. 20b shows the modified Karnaugh map for the truth table of
FIG. 20a.
FIG. 20c shows the circuit implementation of the flip-flop using
the PASS functions of this invention. Note that the circuit
implementation requires only two PASS transistors reflecting only
two looped PASS functions in the modified Karnaugh plot of FIG.
20b.
FIG. 20d shows schematically the extremely simple implementation of
this structure using again the key shown in FIG. 16d.
FIG. 21a illustrates a schematic block diagram of a shift left/hold
circuit and the input and output variables to this circuit. The
input variable C, Q.sub.i-1 and Q.sub.i produce an output variable
D.sub.i. The modified Karnaugh plot for this circuit is illustrated
in FIG. 21c and is implemented as shown in FIG. 21d by a
two-transistor circuit. The schematic layout of this two-transistor
circuit is illustrated in FIG. 21e.
The structures of this invention are, as seen from the last two
implementations in particular, extremely simple compared to prior
art logic implementations. Thus, the topological advantages of this
invention are achieved together with significant reductions in the
complexity of components. Structures made in accordance with this
invention have increased packing density in terms of logic function
per unit area and thus possess either smaller size with
commensurate increased yield or a substantially larger number of
devices formed on a chip of silicon material. Naturally, the
devices described above are to be implemented in standard
semiconductor processing technology such as N channel MOS
technology. The invention, however, is capable of being implemented
in other semiconductor technologies including P channel MOS
technology and CMOS technologies.
While several embodiments of this invention have been described
above, other embodiments of this invention will be obvious in view
of the above description to those skilled in the logic design arts.
The above description is therefore intended to be illustrative only
and not limiting .
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