Game apparatus for trying coincidence between randomly selected characters

Abstract

A game apparatus having digital circuit arrangement such that some randomly selected characters are sequentially exhibited on a plurality of display sections when the player sets the apparatus in operation, as by the insertion of a chip into its slot. When the thus-exhibited characters conicide, the apparatus dispenses a prescribed number of prize chips. When all but one of the characters coincide, the player is allowed to play an "extra game" on the display section which has exhibited a character out of coincidence with those exhibited by the other display sections. According to another preferred embodiment of the invention such extra game can be played not only when all but one of the characters coincide but when they do not coincide at all.

Description

BACKGROUND OF THE INVENTION

This invention relates to a game apparatus composed predominantly of digital circuitry for causing a plurality of display sections to exhibit some randomly selected characters and for dispensing a prescribed number of prize chips when all the exhibited characters coincide.

There has been known a slot machine of this class, in which there are provided several motor-driven reels each having a series of characters or pictures represented thereon. To set this prior art machine in operation the player is required to insert a chip or the like into its slot and then to operate a lever, whereupon the aforesaid reels start revolving at high speed. The reels automatically stop one after the other, with the result that a randomly selected one of the characters or the like on each reel is exhibited through each of the windows formed on the machine. When there is any correspondence between the characters thus exhibited, there is awarded a prize in accordance with the nature of that correspondence.

However, since the prior art machine of the type described depends for its operation almost solely on mechanical means, it involves a variety of intrinsic deficiencies. For instance, considerable noise is produced during operation of the machine, and the inevitable wear of its moving parts gives rise to various troubles or malfunctions.

SUMMARY OF THE INVENTION

It is, therefore, an object of this invention to provide a game apparatus of the class referred to, which is composed predominantly of electronic circuitry whereby the listed disadvantages of the prior art are eliminated altogether.

Another object of the invention is to provide a game apparatus which is highly compact, lightweight, inexpensive of manufacture, and positive in operation.

A further object of the invention is to provide a game apparatus which permits the player to play an "extra game" under some specified conditions in event he has failed to obtain coincidence between the characters exhibited as a result of his first game.

A further object of the invention is to provide a game apparatus including a sound generating mechanism such that some mechanical sound is produced during operation of the apparatus to indicate its normal operating condition and to add to the thrills of the game.

A further object of the invention is to provide a game apparatus including an alarm mechanism which gives off a loud noise as when the apparatus is tilted and/or raised.

A still further object of the invention is to provide a game apparatus including a display device whereby various characters are exhibited in a clearly distinguishable manner, either singly or in combination.

With these objects in view and the other objects hereinafter set forth, this invention provides a game apparatus which, according to a preferred embodiment thereof, includes a plurality of timers for producing outputs for prescribed different lengths of time when the operation of the game apparatus is initiated by the player, as by the insertion of a chip or the like into its slot. Means such as an oscillator becomes operative simultaneously with the timers to produce pulses, and these pulses are permitted to pass through gates, such as NAND circuits, only while these gates are being supplied with the outputs from the corresponding timers. The pulses delivered from the gates are counted by counter circuits provided correspondingly thereto, and the outputs from these counter circuits are supplied to driver circuits respectively, such that upon lapse of the prescribed operating times of the aforesaid timers some randomly selected characters are exhibited on display sections.

Whether the characters thus exhibited on the respective display sections coincide or not is sensed by a coincidence circuit, which produces an output when the exhibited characters do coincide. A prize chip dispensing section is provided which dispenses prize chips only while being supplied with the output from the coincidence circuit. The prize chips being thus dispensed are counted by counter means, perhaps on a binary basis, which is capable of causing the coincidence circuit to discontinue its output production when a prescribed number of the prize chips are dispensed by the prize chip dispensing section.

The embodiment described hereinbefore can be further provided with a logical circuit comprising a pair of flip-flop circuits to permit the player to play an extra game as when all but one of the characters exhibited by the respective display sections as a result of his first game are in coincidence.

The features which are believed to be novel and characteristic of this invention are set forth in the appended claims. The invention itself, however, both as to its organization and mode of operation, together with the further objects and advantages thereof, will be better understood from the following description taken in conjunction with the accompanying drawings which illustrate some preferred embodiments of the invention purely by way of example.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic electrical diagram showing a game apparatus by way of a preferred embodiment of the invention;

FIG. 2 is a schematic diagram showing an example of the detailed configuration of a timer used in the game apparatus of FIG. 1;

FIG. 3 is a schematic diagram showing a part of a coincidence circuit shown in FIG. 1 and prior art means for counting prize chips being dispensed;

FIG. 4 is a waveform diagram explanatory of the operation of the counting means shown in FIG. 3;

FIG. 5 is a similar waveform diagram explanatory of the operation of the prize chip counting means used in the game apparatus of FIG. 1;

FIG. 6 is a schematic diagram showing means for changing the average percentage of prize chips dispensation in the game apparatus of FIG. 1;

FIG. 7 is a perspective view of a display device for use in the game apparatus of FIG. 1;

FIG. 8 is an exploded perspective view of the display device of FIG. 7;

FIG. 9 is a vertical sectional view of the display device of FIG. 7;

FIG. 10 is a schematic electrical diagram showing a game apparatus by way of another preferred embodiment of the invention;

FIGS. 11a and 11b are waveform diagrams plotted by way of explanation of a possible erroneous operation of the game apparatus of FIG. 10;

FIGS. 12a and 12b are also waveform diagrams plotted by way of explanation of another possible erroneous operation in the game apparatus of FIG. 10;

FIG. 13 is a schematic diagram showing the detailed configuration of a sound generator and alarm mechanism in the game apparatus of FIG. 10; and

FIGS. 14a and 14b are vertical sectional views of sensors for use with the mechanism of FIG. 13.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The game apparatus according to this invention will now be described with reference to FIG. 1 which illustrates the electrical circuitry of a first preferred embodiment of the invention. A microswitch provided at SW1 is to be temporarily closed each time a chip or the like is inserted into the slot of the game apparatus. This microswitch is associated with electronic timers T1, T2 and T3 as in the drawing, and each of the timers will produce a signal for a prescribed length of time upon closure of the microswitch SW1. For instance, the timer T1 may have a prescribed operating time of four seconds, the timer T2 that of five seconds, and the timer T3 that of six seconds.

As illustrated in more detail in FIG. 2, each of the timers T1 to T3 may comprise an integrating circuit consisting of capacitor C1 and resistance R1, and switching elements Q1, Q2 and Q3. Referring again to FIG. 1, the output terminal leading from the switching element Q3 of each timer is connected to one of the input terminals of each of NAND circuits U1, U2 and U3. The timer T3, which has the longest operating time, is further associated with an oscillator circuit OU in such a manner that the operating time of this oscillator circuit is exactly synchronized with that of the timer T3.

The output of the oscillator circuit OU is connected to another input of each of the aforesaid NAND circuits U1 to U3, while the outputs of these NAND circuits are connected to the inputs of counter circuits CU1, CU2 and CU3 respectively. The outputs of the counter circuits are connected to the inputs of driver circuits DU1, DU2 and DU3, respectively, that are adapted to operate respective display sections A, B and C which can be formed of indicator tubes, liquid crystals or the like.

Actuated by the pulses delivered from the driver circuits DU1 to DU3, each of the display sections A to C will exhibit, say, seven distinct characters or pictures. During operation of each display section the seven characters exhibited thereby will change from one to the next at such high speed that the player will be unable to decipher them. Each of the driver circuits has a plurality of 16, in this particular embodiment, output terminals which can be selectively switched over to change the rate at which the characters exhibited by the respective display sections coincide, as hereinafter described in more detail.

Connected to a still another input terminal of each of the NAND circuits U1 to U3 is a logical circuit LU adapted to permit the player to play an extra game hereinafter explained. This logical circuit is broadly composed of flip-flop circuits FF1 and FF2 each having four terminals J, K, Q and Q. The extra game can be explained as follows. Upon termination of the operation of the counter circuits CU1 to CU3 the display sections A to C exhibit some characters selected at random. If the characters thus exhibited by, say, the display sections A and B coincide with each other but not with that exhibited by the display section C, then the player is entitled to an extra game in which only the display section C is caused to change its characters.

The characters exhibited each time by the display sections A to C are, in a sense, recognized by a coincidence circuit EU which serves to cause the dispensation of prize chips, which may be made of metal, in case the characters exhibited by the display sections coincide. The number of the prize chips thus dispensed by the game apparatus of the invention is determined in accordance with the particular characters which have coincided, as will be referred to in further detail. The coincidence circuit EU comprises NOR circuits U4 to U17 and inverters I1 to I5 connected as in the drawing.

Six out of the seven outputs of the display section A which correspond to the respective characters to be exhibited thereby are connected to the inputs A1 to A6 of the NOR circuits U4 to U8 and U14 respectively, while the remaining one output is connected to none of the circuits. Thus, no prize chips will be dispensed when the character corresponding to that one output is exhibited. A similar output is provided to each of the other display sections B and C.

The six outputs of the display section B are similarly connected to the inputs B1 to B6 of the NOR circuits U4 to U8 and U14, whereas the six outputs of the display section C are connected to the inputs C1 to C6 of the NOR circuits U9 to U14. Connected to the other inputs of the NOR circuits U9 to U13 are the outputs of the inverters I1 to I5, respectively, the inputs of which inverters are connected to the outputs of the NOR circuits U4 to U8, respectively. The NOR circuits U9 to U13 have additional inputs 128, 64, 32, 16 and 8, and the other NOR circuits U14 to U16 also have additional inputs 8', 4 and 2. These eight additional inputs of the NOR circuits U9 to U16 are connected to the five inputs 2, 4, 8', 8 and 16 of a binary counter circuit CU4 and to the three inputs 32, 64 and 128 of another binary counter circuit CU5 as in the drawing.

The reference numerals attached to the outputs of the NOR circuits U9 to U16 and to the corresponding inputs of the counter circuits CU4 and CU5 represent the numbers of the prize chips to be dispensed by the action of a motor, not shown, under the control of a NOR circuit U18. The number of the prize chips dispensed each time is to be counted on the basis of pulses introduced through terminal 3. When the pulse number thus counted is, say, two, a signal is delivered from the output 2 to the input 2 of the NOR circuit U16.

It will redound to the full appreciation of the advantages of this invention to note that a decimal counter counter CU4' and a binary-to-decimal conversion matrix circuit M shown in FIG. 3 have been used conventionally in place of the binary counter circuits CU4 and CU5. According to this prior art arrangement the pulses delivered from the outputs a to h of the matrix circuit M have the duration, as diagrammatically represented in FIG. 4. Such pulses, when introduced into the coincidence circuit, are hardly distinguishable from those generated accidentally as by external noises. Contrastively, the pulses produced according to the invention have their own characteristic duration as shown in FIG. 5, so that any erroneous operation of the coincidence circuit is successfully prevented.

It will be apparent that the probability of coincidence of each set of characters exhibited by the display sections A, B and C should be determined on the basis of the average rate at which the prize chips are to be dispensed. The average percentage of prize chip dispensation may be set, for example, at 60, 70 and 80 per cent depending upon the estimated frequency at which games are played on the game apparatus, and there are 4,101 combinations of the characters to be exhibited by the three display sections. If now it is assumed that the player is permitted to play the aforesaid extra game only on the display section C, and that the average percentage of prize chip dispensation is present at 60 and 80 per cent, respectively, then the probability of coincidence of each set of characters and the corresponding number of prize chips to be dispensed can be determined as in the following tables:

I. Average Percentage of Prize Chip Dispensation: 60% (Total Number of Games Played: 4101) Number of Display Probability Prize Total Number Char- Section of Chips of Prize Chips acter A B C Coincidence Dispensed Dispensed ______________________________________ ! 1 1 1 2 128 256 * 1 1 1 2 64 128 # 3 1 1 6 32 192 x 7 1 1 14 16 224 y 1 8 1 16 8 128 64 8 512 z 2 4 8 64 4 256 384 2 768 ? 1 0 3 0 0 0 ______________________________________ Total 552 2264 ______________________________________

II. Average Percentage of Prize Chip Dispensation: 80% (Total Number of Games Played: 4101) Number of Display Probability Prize Total Number Char- Section of Chips of Prize Chips acter A B C Coincidence Dispensed Dispensed ______________________________________ ! 1 1 1 2 128 256 * 1 1 1 2 64 128 # 3 1 2 12 32 384 x 8 1 2 32 12 512 y 1 7 4 56 8 448 60 8 480 z 2 5 6 100 4 400 352 2 704 ? 0 0 0 0 0 0 ______________________________________ Total 616 3312 ______________________________________

For thus changing the average percentage of prize chip dispensation in accordance with the frequency at which games are played on this apparatus, the probability of coincidence of the respective sets of characters must be correspondingly modified as set forth by way of example in the foregoing tables. This objective can be accomplished according to the invention simply by operating selector switches SW2 to SW7, FIG. 6, which are interlocked to simultaneously change the operating combinations of the above mentioned 16 outputs provided to each of the driver circuits DU1 to DU3 associated with the display sections A to C respectively. In this particular embodiment of the invention, 80 per cent of prize chip dispensation results when the movable contact of each selector switch is connected to the fixed contact k, 70 per cent when to the fixed contact l, and 60 per cent when to the fixed contact m.

The circuitry shown in FIG. 1 further includes NOR circuits U19 and U20 and NAND circuits U21 and U22, and the logical circuit LU is provided with an "extra game" switch SW8 and a "cancel" switch SW9 which are both to be operated by the player for purposes hereinafter made apparent.

The first preferred embodiment of the invention being configured substantially as hereinbefore described with reference to FIG. 1 in particular, the microswitch SW1 is temporarily closed to initiate the operation of the timers T1 to T3 when a chip or the like is inserted into the slot of the game apparatus. The output signals from these timers are delivered to the NAND circuits U1 to U3 to cause conduction therethrough, so that the pulses generated by the oscillator circuit OU, which has started its operation simultaneously with the timers, are supplied via the NAND circuits to the counter circuits CU1 to CU3, where the pulses are counted.

The output signals from these counter circuits, representative of the counted numbers of pulses, are delivered to the driver circuits DU1 to DU3 respectively, whereupon these driver circuits actuate the respective display sections A to C. As previously mentioned, the seven characters are sequentially and repeatedly exhibited on each of the display sections during operation of the counter circuits, at such high speed that they are not visually recognizable. Upon lapse of a predetermined length of time (4 seconds in this embodiment) the timer T1 stops its operation, and the other timers T2 and T3 stop their operations in 5 and 6 seconds respectively. Each time one of these timers becomes inoperative, the corresponding one of the NAND circuits U1 to U3 is rendered nonconductive, and the operation of the oscillator circuits OU terminates at the same time when the NAND circuit U3 becomes nonconductive. The counting operations of the counter circuits CU1 to CU3 also terminate when the timers become inoperative. The display sections A to C now stationarily exhibit their respective characters which have been showing when the corresponding timers become inoperative.

Let it now be assumed that the movable contact of each of the selector switches SW 2 to SW7, provided between the driver circuits and the display sections as shown in FIG. 6, is connected to the fixed contact k to set the average percentage of prize chip dispensation at 80 per cent. The characters exhibited by the respective display sections in accordance with this percentage of prize chip dispensation are all recognized by the coincidence circuit EU. In case all the characters on the display sections have coincided, the coincidence circuit operates as follows.

If the coinciding characters are, say, "!", then 128 prize chips will be automatically dispensed (see Table II). The display section A delivers an output signal corresponding to the character "!" to the input A1 of the NOR circuit U4 of the coincidence circuit. Similarly, the display section B delivers an output signal corresponding to the character ! to the other input B1 of the NOR circuit U4. Thus, the NOR circuit U4 produces a signal which is delivered to the NOR circuit U9 via the inverter circuit I1. Since an output signal corresponding to the character ! is also delivered from the display section C to the input C1 of this NOR circuit U9, a signal is supplied from its output to one of the inputs of the NOR circuit U17.

The NOR circuit U17 produces an output signal whenever a signal is introduced to any of its inputs, so that upon delivery of the signal from the NOR circuit U9, the NOR circuit U17 supplies its output signal to the NOR circuit U18 which controls the operation of the aforesaid motor, not shown, of the prize chip dispensing section. The 128 prize chips are now successively dispensed, and the number of the prize chips being thus dispensed are counted by the binary counter circuits CU4 and CU5, to which the pulses corresponding to the dispensed chips are supplied as aforesaid through its terminal 3. In accordance with the sequentially increasing number of the pulses actually counted by the counter circuits CU4 and CU5, signals are successively produced from its terminals 2, 4 and so on, until at last a signal is produced from the terminal 128. The last mentioned signal is delivered through the terminal 128 to the NOR circuit U9 of the coincidence circuit EU thereby terminating the signal production of this NOR circuit U9. Thereupon the NOR circuit U18 causes the motor of the prize dispensing section to be set out of rotation so that prize chips are no longer dispensed. The same operation of the coincidence circuit EU and so forth takes place no matter what characters coincide on the respective display sections A to C.

In case the characters exhibited by the display sections A and B have coincided with each other but not with that exhibited by the display section C, another game can be played extra on the display section C through the procedure set forth hereinbelow.

Upon closure of the cancel switch SW9 provided to the logical circuit LU the output Q of the flip flop circuit FF2 is brought to a 0 level. If now a chip or the like is inserted into the slot of the game apparatus to play the game as described above, the timers T1 to T3 are set in operation to cause the output Q of the flip flop circuit FF1 to switch to a 1 level. In this state the display sections A to C exhibit the swiftly changing characters. Upon lapse of the prescribed lengths of time the timers successively stop their operations, with the result that the characters exhibited by the display sections A and B coincide with each other but not with that exhibited by the display section C as above assumed. The output Q of the flip flop circuit FF1 is now brought to a 0 level.

Since the characters exhibited by the display sections A and B are in coincidence, signals representative of these coinciding characters are delivered to either of the NOR circuits U4 to U8, so that an output signal from this particular NOR circuit is delivered to the NOR circuit U18 and thence to the NAND circuit U22 via the NOR circuit U19. Also delivered to the NAND circuit U22 is the 1 level signal from the output Q of the flip flop circuit FF2, so that upon closure of the "extra game" switch SW8, the NAND circuit U22 will deliver its output signal to the "clock" terminal of the flip flop circuit FF2.

Thus, the player is ready to play an extra game if he closes the extra game switch when the characters exhibited by the display sections A and B are in coincidence and when the timers are out of operation. Upon closure of the extra game switch the output Q of the flip flop circuit FF2 and the output J of the flip flop circuit FF1 are both brought to a 0 level, so that the NAND circuits U1 and U2 connected to these outputs of the flip flop circuits FF1 and FF2 are biased to cause the display sections A and B to maintain the coinciding characters which have been exhibited thereby as a result of the precedingly played game. This permits the player to play an extra game only on the display section C as above stated.

As the player again inserts a chip or the like into the slot of the game apparatus to play the extra game, the timers T1 to T3 are set in operation. Since, however, the output of only the timer T3 connected to the logical circuit LU, the output Q of the flip flop circuit FF1 is brought to a 1 level by the output signal of the timer T3 while the output Q of the flip flop circuit FF2 remains in the "0" level. As a consequence, the display sections A and B are caused to maintain their coinciding characters, whereas the display section C is caused to sequentially and repeatedly exhibit the seven characters as previously explained. This operation of the display section C continues for the prescribed operating time, six seconds in this embodiment, of the timer T3.

Upon termination of operation of the timer T3 the output Q of the flip flop circuit FF1 switches to a 0 level. As the output Q of the other flip flop FF2 resultantly switches to a 1 level, the NAND circuits U1 and U2 are both released from their inoperative condition. In case all the characters exhibited by the display sections A to C have coincided as a result of this extra game, a predetermined number of the prize chips will be dispensed through the procedure already set forth. Since the logical circuit LU is already in its normal condition, the NAND circuits U1 and U2 cannot be biased as above even if the extra game switch SW8 is closed again, so that the extra game cannot be played twice consecutively. This holds true even in case all the characters exhibited by the three display sections have coincided as a result of the extra game.

If a chip or the like is again inserted to initiate the operations of the timers T1 to T3, the output Q of the flip flop circuit FF1 assumes a 1 level. The initial condition is thus realized. The NOR circuit U20 shown in FIG. 1 is used to exhibit the fact that the player is free to insert a chip or the like into the slot of the game apparatus, while the NAND circuit U21 is used to exhibit the fact that an extra game is due.

The operation of the selector switches SW2 to SW7 shown in FIG. 6 will now be briefly described in relation only with the display section B. If, for instance, the movable contact of the selector switch SW3 is connected to the fixed contact k to realize 80 per cent of prize chip dispensation, then the terminal of the display section B corresponding to the character z is electrically connected to the terminal No. 15 of the driver circuit DU2 besides being connected to the terminals Nos. 4, 6, 10 and 12 of the driver circuit. The probability that the character z will be exhibited by the display section B is now higher than when the movable contact of the selector switch SW3 is connected to the fixed contact m. Similar results are obtainable with the other selector switches. However, it must be noted that in this embodiment of the invention the selector switches SW2 to SW7 are all interlocked for changing the average percentage of prize chip dispensation between 60, 70 and 80 per cent.

The detailed construction of the display sections A to C is hereinafter described with reference to FIGS. 7 to 9. A casing 30, which can be conveniently molded of a plastic, is recessed at 31 to accommodate a plurality of display panels 32 one on the back of another. It will be noted from FIGS. 8 and 9 that the display panels are removably received in grooves 33 formed correspondingly at the bottom and the top of the recess 31. The grooves formed on the top of the recess 31 are open to a plurality of compartments 34, respectively, each adapted to house a lamp 35.

Each of the display panels 32 is in the form of a sheet of transparent material, such for example as acrylic resin or glass, on one face of which an appropriate character or picture is engraved. A color filter 36, made for example of a colored plastic, is affixed to the upper edge of each display panel, while a shutter 37 of opaque material such for example as metal is affixed to the bottom edge of each display panel.

As will be seen from FIGS. 8 and 9, the aforesaid lamps 35 are supported at their upper ends by a rectangular plate 38 laid over the casing 30. This casing is further provided with a front covering 39 of substantially U-shaped cross section having a window 40 through which are exhibited the various characters or the like of the respective panels in a manner described hereinbelow.

When one of the lamps 35 is lit up, the corresponding one of the display panels 32 therebelow is irradiated through the color filter 36 so that the character or the like engraved on this particular panel only is distinctly made visible in the color of that color filter due to the so-called edge effect. Similarly, when another of the lamps 35 is lit up, the display panel corresponding thereto is irradiated through its own color filter so that the character on this second panel is also made visible in a color which preferably is differentiated from the color of the first mentioned color filter.

Thus, since the characters or the like engraved on the respective display panels are exhibited in their own distinctive colors, they are easily visually distinguishable from each other. The characters thus exhibited are especially aesthetically appealing when they are successively switched from one to the next as previously mentioned. It is an additional advantage that even when two or more of the display panels are irradiated simultaneously by their respective lamps, the resultantly exhibited characters are clearly distinguishable from each other.

The game apparatus according to the invention will now be described in terms of a second preferred embodiment thereof illustrated in FIG. 10, in which parts corresponding to those set forth in connection with the preceding embodiment are designated by like reference characters.

As in the preceding embodiment, the microswitch SW1 is to be temporarily closed each time a chip or the like is inserted into the slot of the game apparatus. Upon closure of the microswitch the timers T1 to T3 will generate pulses of a definite level for their respective prescribed lengths of time, the timer T1 having the shortest operating time and the timer T3 the longest operating time. The output of each of these timers is connected to one of the inputs of each of the NAND circuits U1 to U3, and each of the NAND circuits has another input for connection to the output of a pulse oscillator circuit OU and still another input 1H, 2H or 3H for use when the extra game is played, as hereinafter referred to in more detail.

The outputs of the NAND circuits U1 to U3 are connected to the inputs of decimal counter circuits C1 to C3 and thence to driver circuits D1 to D3 respectively. Each of the driver circuits has, say, sixteen outputs connected to each of matrix circuits N1 to N3 whereby the sixteen outputs of each driver circuit are rearranged into six outputs 1A to 1F, 2A to 2F, and 3A to 3F, respectively. The six outputs of each matrix circuit are connected to a display section, not shown, which exhibits signals or characters in accordance with the signals of different kinds supplied thereto. More specifically, the display sections associated with the respective matrix circuits N1 to N3 can be formed of lamps, indicator tubes, liquid crystals or the like to exhibit such signals or characters in a manner still to be described.

Each corresponding three of the outputs of the matrix circuits N1 to N3 are connected to each of four-input OR circuits S1 to S6. The OR circuit S1, for instance, has its three inputs connected to the outputs 1A, 2A and 3A of the matrix circuits and its fourth input connected to an output .sigma. of a pair of counter circuits C4 and C5 adapted to count the number of prize chips dispensed when the characters exhibited by the aforesaid display sections coincide. Pulse signals will be produced successively from the outputs .alpha. to .sigma. of the counter circuits when they count up to 2, 4, 8, 16, 32, 64 and 128 prize chips respectively. The output .alpha., for instance, corresponds to the number 2 and the output .sigma. to the number 128. For thus counting the number of prize chips there is provided a switch SW10 adapted to be closed by each prize chip being dispensed, and a pulse is introduced into the counter circuits each time the switch is closed.

The outputs of the OR circuits S1 to S8 are all connected to a NAND circuit G1 the output of which is connected, on the one hand, to a NAND circuit G2 and on the other hand to a NOR circuit G3. This NOR circuit G3 is adapted to light up a lamp, not shown, for indication that the apparatus is ready for operation. The NOR circuit G3 has another input which is connected to the output of the aforesaid timer T3. This output of the timer T3 is further connected via an inverter I6 to another input of the NAND circuit G2, while the output of this NAND circuit is connected via an inverter 17 to the motor, not shown, of the prize chip dispensing section.

A NAND circuit G4 has two inputs connected to the output of the inverter 16 and to the output of the NAND circuit G2 respectively, while the output of the NAND circuit G4 is connected to one of the two inputs of an OR circuit S8. Connected to the other input of the OR circuit S8 is the terminal Q of a flip flop circuit F. The output of the OR circuit S8 is connected via an inverter I8 to a terminal which is to be connected to a lamp, not shown, for indication that an extra game can be played. The output of the OR circuit S8 is also connected to a plurality of independently operable switches SW11 to SW13 which are further connected to the terminals P of flip flops F1 to F3 respectively. The terminals Q of these flip flops are connected to the respective inputs of an OR circuit S9, while the terminals Q of the flip flops are connected to the inputs 1H to 3H of the aforementioned NAND circuits U1 to U3 respectively.

The output of the OR circuit S9 is connected to a circuit adapted to prevent erroneous operation and also to prevent the extra game to be played twice consecutively. More specifically, the output of this OR circuit is connected to a switching element Tr1 via diode D1, resistances R2 to R5, and capacitor C2, which are interconnected as in the drawing. The collector of the switching element Tr1 is connected to the input of a NAND circuit G5 which has another input connected to the output line of the timer T3. The output of the NAND circuit G5 is connected to the terminal P of the aforesaid flip flop F, and the clear terminal C of this flip flop is connected to the output of the NAND circuit G6.

The OR circuit S9 has its output also connected to one of the two inputs of the NAND circuit G6, the other input of which is connected to the output line of the timer T3. The terminal Q of the flip flop F, the terminal C of which is connected to the output of the NAND circuit G6 as above mentioned, is connected to one of the two inputs of an OR circuit S10. The other input of this OR circuit S10 is connected to the output line of the timer T3. The output of the OR circuit S10 is connected via a cancel switch SW9 to the clear terminals C of the flip flop circuits F1 to F3. These terminals C of the flip flop circuits are further connected to the collector of a switching element Tr2. A diode D2 is connected between the base of the switching element Tr2 and the ground. The base of this switching element is further connected via a capacitor C3 to the collector of another switching element Tr3, and the base of the switching element Tr3 is connected to the output line of the timer T3.

The terminal Q of each of the aforesaid flip flop circuits F1 to F3 is also connected to one of the two inputs of each of NOR circuits S11 to S13 adapted to light up lamps, not shown, for indication of the extra game. The other input of each of these NOR circuits is connected to the output of the inverter 17. This output of the inverter 17 is also connected to one of the two inputs of an OR circuit S14, and the other input of the OR circuit S14 is connected to the output of a sound generator M which doubles as an alarm, as hereinafter described in more detail in FIGS. 13 and 14. The output of the OR circuit S14 is connected to the "reset" terminal R of the counter circuits C1 to C3. The sound generator M includes a sensor which responds when the game apparatus is unduly tilted or lifted as by the player himself, whereupon the counter circuits C1 to C3 are immediately reset by the signal delivered from the OR circuit S14. The counter circuits C4 and C5 have their reset terminals connected to the output of the timer T3 so that these counter circuits are permitted to operate only when the timer T3 is out of operation.

In the second preferred embodiment of the invention, configured essentially as described hereinabove with reference to FIG. 10, the switch SW1 is temporarily closed as in the preceding embodiment when a chip or the like is inserted into the slot of the game apparatus, thereby initiating the operations of the timers T1 to T3. It is to be noted that the NAND circuits U1 to U3 are conductive only when their inputs connected to the outputs of the respective timers T1 and T3 to their inputs 1H to 3H are both at a 1 level. As previously mentioned, the inputs 1H to 3H of the NAND circuits are connected to the terminals Q of the flip flop circuits F1 to F3 respectively. Since the flip flop circuits F1 to F3 normally have their terminals Q at a 1 level and their terminals Q at a 0 level, the NAND circuits U1 to U3 become conductive immediately when the timers T1 to T3 are set in operation, so that the pulses generated by the pulse generator OU are delivered therethrough to the respective counter circuits C1 to C3. The output signals of these counter circuits are introduced into the display sections via the driver circuits D1 to D3 and the matrix circuits N1 to N3 respectively. These signals are, for example, at a 0 level and causes the respective display sections to exhibit changing characters.

Since the timers T1 to T3 have different operating times as above stated, the operations of the counter circuits C1 to C3 terminate successively, in the order of C1, C2 and C3 in this embodiment. Thereupon the display sections also successively exhibit some particular characters in a manner which will be apparent from the foregoing discription of the preceding embodiment. When the characters exhibited by the three display sections all coincide, a prescribed number of prize chips are dispensed. No prize chip is dispensed when all the three exhibited characters differ. However, in this second preferred embodiment of the invention, the player is entitled to the extra game when the characters exhibited by the three display sections are all out of coincidence, in addition to when the characters exhibited by two of the display sections are in coincidence.

When, for instance, the three display sections exhibit some coinciding characters, the matrix circuits N1 to N3 produce 0 level outputs from the corresponding ones of their output terminals 1A to 1F, 2A to 2F, and 3A to 3F. Let it now be assumed that such 0 level outputs are produced from the terminals 1A, 2A and 3A of the matrix circuits. These outputs are then all delivered to the input terminals 1A, 2A and 3A of the OR circuit S1. Since the other input terminal .sigma. of this OR circuit is also at a 0 level, the OR circuit S1 delivers a 0 level output to the NAND circuit G1 and thence to the NAND circuit G2. Since this NAND circuit G2 is also supplied with the output from the timer T3 via the inverter I6, the NAND circuit has its two inputs both at a 1 level when the timer output switches to a 0 level, so that its output is brought to a 0 level. This 0 level output signal from the NAND circuit G2 again brought to a 1 level by the inverter 17 and is utilized to actuate the motor of the prize chip dispensing section.

As the motor is thus set in rotation, prize chips are successively dispensed, in such a way that each prize chip instantaneously closes the switch SW10 thereby causing the counter circuits C4 and C5 to count the number of such prize chips being dispensed. When, in this instance, 128 prize chips are counted, the counter circuits delivers a 1 level signal from the output terminal .sigma. to the corresponding input terminal .sigma. of the OR circuit S1 so that the output from this OR circuit switches to a 1 level. As a consequence, the output from the inverter I7 switches to a 0 level to set the motor out of rotation and hence to suspend the dispensation of the prize chips.

The extra game can be played as follows when the characters exhibited by the three display sections do not coincide at all or when the characters exhibited by two of the display sections coincide. It is necessary that prior to playing such extra game, the switches SW11 and SW13 be selectively operated to cause the two coinciding exhibited characters or any one of the three exhibited characters to remain unchanged during the extra game. For instance, if the switches SW11 and SW12 are closed, the characters exhibited by the display sections associated with the matrix circuits N1 and N2 will remain fixed during the extra game, because then the terminals P of the flip flop circuits F1 and F2 are connected to the output of the OR circuit S8.

In case the characters exhibited by the three display sections are all out of coincidence, the NAND circuit G4 delivers a 0 level output to one of the input terminals of the OR circuit S8. The other input terminal of this OR circuit is also supplied with a 0 level output from the terminal Q of the flip flop circuit F, so that the OR circuit S8 produces a 0 level output. Accordingly, since the terminals P of the flip flop circuits F1 and F2 are set at a 0 level, the closure of the switches SW11 and SW12 causes the terminals Q of these flip flop circuits to switch from 1 to 0 level. The NOR circuits S11 and S12 are thus caused to produce 1 level outputs to light up the lamps, not shown, connected thereto. The 0 level signals from the terminals 1H and 2H are delivered to the NAND circuits U1 and U2, respectively, thereby making the same nonconductive, so that the characters exhibited by the display sections associated with the matrix circuits N1 and N2 are held unchanged during the extra game to be played succeedingly.

The preparations for playing the extra game being now completed, a chip or the like may again be inserted into the slot of the game apparatus to close the switch SW1 and thus to set the timers T1 to T3 in operation. Since, however, the NAND circuits U1 and U2 are now both nonconductive, the counter circuit C3 only becomes operative to count the pulses delivered from the timer T3 via the NAND circuit U3, and the display section associated with the matrix circuit N3 only is caused to change its characters. Upon lapse of the predetermined length of time the timer T3 becomes inoperative to render the NAND circuit U3 nonconductive so that the display section associated with the matrix circuit N3 exhibits some particular character. When this character coincides with the two like characters already exhibited by the other display sections, a prescribed number of prize chips will be dispensed through a procedure already set forth.

Typically, the extra game switches SW11 to SW13 are to be closed by push buttons or the like arranged conveniently on this game apparatus, so that it is likely that the player close wrong switches. In this case the cancel switch SW9 may be closed to cancel out the previous instructions. Since the OR circuit S10 connected to the switch SW9 has its inputs at a 0 level, the closure of this switch causes the terminals Q of the flip flop circuits F1 to F3 to return from 0 to 1 level.

In this second preferred embodiment of the invention, too, the player is prevented from playing two extra games consecutively, by means described hereinbelow. When a single extra game is played as above explained, either of the terminals Q of the flip flop circuits F1 to F3 is brought to a 1 level, so that the output from the OR circuit S9 is at a 1 level. It will be noted from FIG. 10 that the output terminal of this OR circuit S9 is connected, on the one hand, to one of the input terminals of the NAND circuit G6 and, on the other hand, to one extremity of the resistance R4 and to the diode D1.

If now an extra game is started, the 1 level output from the timer T3 is delivered to the NAND circuits G5 and G6 and the switching element Tr3. However, in event a chip or the like is inserted substantially at the same time the extra game switches SW11 to SW13 are closed, the ouput from the timer T3 changes from 0 to 1 level with a certain transition time t1 as shown diagrammatically in FIG. 11a. This 1 level output is impressed to one of the input terminals of the NAND circuit G5 as above mentioned. Since the other input terminal of the NAND circuit G5 is connected to the output terminal of the OR circuit S9 via the switching element, it becomes conductive when the switches SW11 to SW13 are closed. Upon conduction of the switching element Tr1 the potential at its collector turns from high to low level with a certain time of transition as seen in FIG. 11b. This signal is delivered to the NAND circuit G5.

Thus, in event a chip or the like is inserted substantially at the same time the extra game switches are closed, the NAND circuit G5 will be impressed with a threshold voltage so that its output goes negative. This pulse signal of negative polarity is delivered to the terminal P of the flip flop circuit F. With the flip flop circuit in this condition the player is allowed to play the extra game repeatedly. In order to prevent such desirable outcome the threshold voltage impressed to the NAND circuit G5 must be eliminated. To this end the switching element Tr1 must be caused to turn on earlier than when the timer T3 starts its signal production, as indicated by the dot-and-dash lines in FIG. 11b. This can be accomplished by the provision of the diode D1.

A similar threshold voltage is also produced at the end of an extra game. When the output from the timer T3 returns to a 0 level as shown in FIG. 12a, the flip flop circuits F1 to F3 are all caused to regain their initial condition by the switching element Tr3. As a consequence, the output from the OR circuit S9 assumes a 0 level, as in FIG. 12b, at the same time the output from the timer T3 switches to a 0 level, so that the collector of the switching element Tr1 assumes a 1 level. If these changes in the levels of the output from the timer T3 and the potential at the collector of the switching element Tr1 took place simultaneously, the aforesaid threshold voltage would be produced. However, owing to the capacitor C2 connected to the input of the switching element Tr1, the level of this switching element is caused to change after the operation of the timer T3 has terminated, as indicated by the dot-and-dash lines in FIG. 12b, so that any erroneous operation of the NAND circuit G5 is prevented.

Thus, after an extra game is played once, the terminal Q of the flip flop circuit F is always at a 1 level to prevent the player from playing two extra games consecutively. It may be noted that during the progress of an extra game, the output of the NAND circuit G6 is at 0 level and the terminal Q of the flip flop circuit at a 1 level. When the extra game is over, the terminal Q of this flip flop circuit returns to a 0 level, and the other flip flop circuits also return to their initial condition.

The game apparatus described hereinbefore is so compact and lightweight that it may be tilted, vibrated or, what is worse, carried away from its place of installation. In view of these possibilities there is provided the sound generator and alarm mechanism M described later in more detail. When the apparatus is unduly tilted or raised the mechanism will deliver a pulse signal to the OR circuit S14 thereby causing the same to deliver a reset signal to the counter circuits C1 to C3. The operation of the game apparatus is thus suspended. The alarm mechanism will also emit a noise to warn the fact. However, in case some coinciding characters are already exhibited by the three display sections, a prescribed number of prize chips will be duly dispensed while only the warning noise is produced.

The detailed configuration of the sound generator and alarm mechanism M will now be described with reference to FIG. 13. A control circuit CS1 is composed of switching elements Q4 and Q5 and other circuit elements shown in the drawing. The switching element Q5 has its collector connected to a diode D3 and thence to an oscillator CS2 which may be in the form of a multivibrator composed of switching elements Q6 and A7 and so forth. This oscillator CS2 is further connected to an amplifier CS3 which is provided with a buzzer Bz or the like. The switching element Q6 of the oscillator CS2 has its base connected to the aforesaid diode D3, and a predetermined voltage is impressed thereto via resistance R5. The frequency of the oscillations by the oscillator CS2 is determined by the product of the values of the resistance R5 and the capacitor C4.

The control circuit CS1 is to be actuated by sensors Sn and Sn' shown in FIGS. 14a and b. The sensor Sn includes a housing having a substantially funnel-shaped bottom 50. A limit switch 51 fixedly mounted under the housing has its actuating member 52 projecting through the center of the funnel-shaped bottom 50. Thus, as long as the game apparatus is in its normal condition, the limit switch 51 is held closed by a ball 53 placed upon the funnel-shaped bottom of its housing. However, in case the apparatus is tilted to such an extent that the ball 53 displaces from its central position on the funnel-shaped bottom, the limit switch 51 opens.

The other sensor Sn' is substantially in the form of a normally open switch comprising a vertically movable contact 54 and a pair of fixed contacts 55. The movable contact 54 is normally held raised as by the floor surface on which the game apparatus is mounted. As the apparatus is lifted, however, the movable contact is lowered by gravity thereby establishing electrical connection between the pair of fixed contacts 55.

Further according to this invention it is considered desirable that while the game apparatus is operating properly, some sound be produced to indicate the proper operating condition of the apparatus and also to add to the thrills of the game. For producing such sound a signal which is generated only during the operation of the game apparatus is directed to a terminal T6, FIG. 13, of a control circuit CS4 which is substantially of the same configuration as the first mentioned control circuit CS1. The control circuit CS4 includes switching elements Q8 and Q9, and a voltage is impressed via resistance R6 to the collector of the switching element Q9. The collector of this switching element Q9 is also connected to the base of the switching element Q6 of the oscillator CS2 via diode D4 and resistance R7. The resistance R6 is of higher value than the resistance R5. A pair of supply terminals are provided at T and T'.

When a chip or the like is inserted into the slot of the game apparatus of FIG. 10 to set the same in operation, the aforesaid signal is delivered to the terminal T6 of the control circuit CS4. The switching element Q8 is then turned on, while the switching element Q9 is turned off. Thus, the voltage impressed to the base of the switching element Q6 of the oscillator CS2 via the diode D4 and resistance R6. As the switching element Q9 is turned off as aforesaid so that the voltage is impressed to its collector, the voltage regulated by the resistances R6 and R7 is impressed to the base of the switching element Q6. The oscillator CS2 thus produces its output at a predetermined frequency. This oscillator output is introduced to the amplifier CS3 to cuase the buzzer Bz to emit a sound which is not the loud noise usually emitted by such buzzer in the event of an emergency but is like that produced by similar game apparatus of mechanical construction.

In event the game apparatus is tilted or raised, whether it is in operation or not, the sensor Sn and/or sensor Sn' is closed to cause a biasing voltage to be impressed to the base of the switching element Q4 of the control circuit CS1. As the switching element Q4 is thus turned on, the other switching element Q5 is turned off. The collector voltage thereof, regulated by the resistance R5, is delivered via the diode D3 to the base of the switching element Q6 of the oscillator CS2. The resulting output from this oscillator, determined by the product of the values of the resistance R5 and the capacitor C4, is introduced to the amplifier CS3 to cause the buzzer Bz to produce a loud, warning noise. The frequency of this warning noise is to be appropriately determined on condition that the value of the resistance R5 is smaller than that of the resistance R6.

It is believed that the embodiments herein disclosed are well calculated to accomplish the various objects of the invention, either explicitly stated or otherwise set forth. However, it will also be understood that such specifically recited embodiments are susceptible to modifications, substitutions or changes within the usual knowledge of those skilled in the art. It is therefore appropriate that the invention be construed broadly and in a manner consistent with the fair meaning or the proper scope of the claims appended hereto.

Claims

What is claimed is:

1. An electronic game apparatus comprising:

means for initiating game operation;

a plurality of timers responsive to said game initiating means for providing electrical signals having predetermined different time durations;

means also responsive to said game initiating means for providing an output signal consisting of a series of pulses;

a plurality of gate circuits, each responsive to a different timer signal and to said pulse signal, for passing said pulses when said timer signals are present;

a plurality of counter circuits, each coupled to a respective gate circuit, for counting the pulses delivered from each of said gate circuits respectively;

a plurality of display sections, including respective driver circuits, each display section responsive to a corresponding counter circuit respectively, each display section including means for exhibiting a character randomly selected from a closed set of different characters and dependent upon the termination of a corresponding timer signal, said driver circuits being so connected to said exhibiting means that the probability of selection of each of the characters differs;

a coincidence circuit for sensing the characters exhibited by said display sections and for producing a plurality of outputs corresponding to said characters being in predetermined patterns of coincidence, and probability of occurrence of said coincidence patterns differing;

prize chip dispensing means having a reservoir of prize chips and responsive to the outputs of said coincidence circuit for dispensing a predetermined amount of prize chips corresponding to each of said outputs of said coincidence circuit; and

a plurality of selector means adapted to be set prior to game operation being connected between said driver circuits and said display sections for changing the connections between driver circuits and exhibiting means so that the probability of selection of each of the characters is changed resulting in a corresponding change in the probability of occurrence of said coincidence patterns and, correspondingly, the amount of prize chip dispensation.

2. An electronic game apparatus as in claim 1 wherein said driver circuits have a number of outputs which exceed the number in the set of characters to be exhibited, each driver output being adapted to excite a character, and wherein certain driver outputs are connected together, and connected to a corresponding display character exhibit means, the number of outputs being so connected together and being connected to a display character determining the probability of selection of that character.

3. An electronic game apparatus as in claim 2 wherein said selector means includes a plurality of individual switches between respective driver circuits and display sections for changing the connections between said driver circuits and corresponding display characters so as to change the probability of selection of that character, said selector switches being ganged together to move as a single switching unit.

4. An electronic game apparatus, said apparatus being in normal operation when substantially motionless and being in abnormal operation when a predetermined condition such as a substantial shock, force or motion is imparted to said apparatus, comprising:

means for initiating game operation;

a plurality of timers responsive to said game initiating means for providing electrical signals having predetermined different time durations;

means also responsive to said game initiation means for providing an output signal consisting of a series of pulses;

a plurality of gate circuits, each responsive to a different timer signal and to said pulse signal, for passing said pulses when said timer signals are present;

a plurality of counter circuits, each coupled to a respective gate circuit, for counting the pulses delivered from each of said gate circuits respectively;

a plurality of display sections, including respective driver circuits, each display section responsive to a corresponding counter circuit respectively, each display section including means for exhibiting a character randomly selected from a closed set of different characters and depending upon the termination of a corresponding timer signal, said driver circuits being so connected to said exhibiting means that the probability of selection of each of the characters differs;

a coincidence circuit for sensing the characters exhibited by said display sections and for producing a plurality of outputs corresponding to said characters being in predetermined patterns of coincidence, the probability of occurrence of said coincidence patterns differing;

prize chip dispensing means havng a reservoir of prize chips and responsive to the outputs of said coincidence circuit for dispensing a predetermined amount of prize chips corresponding to each of said outputs of said coincidence circuit; and

sound generator means for generating a sound during normal operation of said game apparatus, said sound generating means including a switching circuit to which a signal is supplied only during normal operation of said game apparatus, an oscillator circuit being driven by said switching circuit and a sound source being driven by said oscillator circuit, said sound generator means including alarm means for causing said sound source to provide a loud noise when the game apparatus is in abnormal operation, said alarm means including sensing means responsive to said predetermined condition causing abnormal operation, and a second switching circuit actuated by said sensing means for causing said oscillator circuit to cause said sound source to generate said loud noise.

5. The game apparatus of claim 4 wherein said sensing means includes a first sensor for actuating said second switching circuit when said game apparatus is tilted, and a second sensor for actuating said second switching circuit when the game apparatus is raised and wherein said counter circuits are reset by the sensor means.

6. The game apparatus of claim 4 wherein said counter circuits are reset by a signal delivered from an OR circuit to which is supplied an output from said sensing means and an output from said coincidence circuit.

7. The game apparatus as recited in claim 4, comprising means for changing the frequency of said oscillator circuit from one frequency corresponding to normal operation to another frequency corresponding to abnormal operation.

8. The game apparatus as recited in claim 7, wherein said means for frequency changing comprises a resistor and capacitor connected together for changing the repetition rate of said oscillator.