TV display system

Abstract

A character display system having a raster type cathode ray tube display including a continuously updated display segment for such information as date and time. Data defining the updated portion of the display is stored in a circulating shift register having a counter stage and an output stage connected to a character generator. The data is shifted in synchronism with the raster scan so that the output stage of the register synchronously provides information to the character generator to generate the updated portion of the display. The counter stage is appropriately incremented when containing data to be modified, thereby updating the display information being circulated.

Description

BACKGROUND OF THE INVENTION

This invention relates to the display of alpha numeric characters on a television screen. In particular, it relates to the display of continually updated information in alpha numeric form on a television screen that simultaneously displays a conventional picture.

The invention is primarily directed to those applications where a picture of an event or series of events is recorded on video tape for later display on a television screen and certain current auxilliary information relating to each event must be concurrently recorded for simultaneous display with the picture to which it relates.

For example, many banks position television cameras to view teller transactions. The pictures are recorded on video tape and later displayed if they are to be visually reviewed. Then if a bad check is passed or there is a holdup, the authorities can review the recorded pictures to identify the wrongdoers. To make the evidence more binding in court, it is desirable that the system record, along with the viewed event, the date and time thereof so that each person whose picture is recorded can be positively connected with a specific date and time.

Conventionally the date and time are entered into the system electronically. The various elements of this information, i.e. seconds, minutes, hours, days, months and years, are stored in counter-registers which are connected to operate as a running electronic calendar-clock. The digital contents of these registers are applied to a decoder which converts the signals to corresponding television raster presentation signals. The latter signals are then combined with the output of the television camera as the latter scans the area to be viewed. A suitable synchronizing and switching arrangement applies the contents of the respective registers in turn to the decoder so that they are fed into the video system in the proper order. Then, when the recorded, combined video signal is later displayed, numerals representing the date and time of the recorded pictures appear in a string across the bottom of the screen.

While this system effectively records the required information, it requires relatively involved and expensive switching circuitry to apply the contents of the various data-containing registers to the decoder. The principle object of the present invention is to simplify and thereby reduce the cost of the circuits.

SUMMARY OF THE INVENTION

In my system the auxilliary information to be recorded and/or displayed is stored in a circulating character register, each character of the information occupying one stage of this register. One stage of the shift register is connected to a video raster decoder so that as the contents of the shift register are rotated, each character in turn is applied to the decoder for combination with the video signal. In cases where the recorded information is numerical information to be updated by a counting operation, such as the keeping of time, this is preferably accomplished by including a counter as one stage of the shift register. Then whenever a quantity stored in the register is to be increased, the system adds to it as it passes through the counter.

The counting process requires a carry function in several different situations. For this I prefer to use a separate carry shift register having a stage corresponding to each stage in the character register and arranged for insertion of carry bits into certain stages. Whenever a carry bit reaches the stage corresponding to the counter, it increments the counter and thereby increases the value of the digit then contained in the counter.

DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram of the raster-encoding portions of the circuit;

FIG. 2 is a diagram of the character storage and selection portions of the circuit; and

FIG. 3 is a diagram of a display provided by the circuits of FIGS. 1 and 2.

In the following description, actuation of a circuit element, e.g. setting or clearing of a flip-flop, takes place on the trailing edge of the actuating signal unless otherwise stated or indicated by the circuit configuration. Thus, when actuation on the leading edge of a signal is desired, the signal is first passed through an inverter so that the leading edge of the inverted signal has the same effect as the trailing edge of the noninverted signal.

DESCRIPTION OF THE PREFERRED EMBODIMENT

As shown in FIG. 1, a television camera 10 set up for a surveillance operation provides a video output signal that is applied to a recorder 12 by way of a summing circuit 14. If desired, signal may be simultaneously displayed on a conventional remote television monitor 15. The other input of the summing circuit comes from a character generator, generally indicated at 16, that supplies signals corresponding to alpha numeric characters. These characters are displayed along with the scene viewed by the camera 10. The characters represent any desired information that is to be updated from time to time. In the system described herein they represent the date and time.

At this point it will be helpful to review the arrangement of the character display on the cathode ray screen. As shown in FIG. 3, the system displays in order a series of date and time segments: the month, day of the month, year, hour, minute and second. Thus, the indicated time and date are 14 hours, 23 minutes and 36 seconds on July 23, 1973.

The characters are formed in a conventional 5 .times. 7 matrix, i.e. 5 elements wide and 7 elements high. Each of the vertical elements corresponds to one line of the television raster. Specifically, the video display first sweeps across line 0 to form the top portion of each of the characters and then in succession it sweeps across lines 1-6 to complete the character display. The times during which the electron beam traces the respective lines are correspondingly designated V0-V6.

Similarly, the system has time divisions corresponding to the horizontal movement of the electron beam along each of the lines. Thus, the first character occupies a zone corresponding to horizontal times H0-H6. The character itself occupies the five elements H0-H4, H5 and H6 being used for intercharacter spacing.

In the display shown in FIG. 3, the characters are divided into time-segment blocks of two characters each, with punctuation marks separating the time segments as indicated. This requires additional spacing between the second character of each segment and the first character of the next segment and for this purpose I assign ten horizontal intervals H0-H9 to the second character in each block. Again the character itself occupies intervals H0-H4.

Each element in the field of each character of the FIG. 3 display is uniquely identifiable with a pair of vertical and horizontal time intervals. In order to generate the character, i.e. develop the electrical signals which will be used to display it, a digital code for the character is applied to a decoder, as described below, along with signals representing the respective vertical and horizontal time signals. The decoder provides an output for each time signal pair, indicating whether the display should be dark or light during that time interval, i.e. in the corresponding position of the display. The combination of these dark and light intervals provides the visual presentation of the character.

For example, when the character 7 is to be displayed, as shown in FIG. 3, the decoder provides a "dark" output signal during the vertical time V0, from horizontal time H0 through time H4. The decoder also provides a dark signal when horizontal time H4 occurs during vertical time V1. On the other hand, there is a "light" signal during the coincidences of horizontal times H0-H3 with vertical time V1.

In FIG. 3, I have designated the intervals occupied by the respective time segments as t.sub.MO, t.sub.D, t.sub.y, t.sub.H, t.sub.Mi, and t.sub.s, respectively. The system develops and uses correspondingly designated signals as described below.

With further reference to FIG. 1, the output of the camera 10 is also applied to a sync separator 18 which extracts horizontal and vertical sync pulses. These pulses are applied to variable horizontal and vertical delay units 20 and 22.

An oscillator 24 which, in the present example, has a frequency of 2.1 MHz applies a series of pulses through a gate 26 to a horizontal counter 28. The gate 26 is enabled by the output of a flip-flop 30 when the latter is set by the delayed sync pulse from the horizontal delay unit 20. The counter 28 nominally divides the frequency of the oscillator 24 by a factor of ten, except when its counting cycle is shortened, as described below, in which case it divides by a factor of seven. The counter 28 is provided with suitable gating so that in each of various counting states the counter 28 provides an output signal on a different one of its output lines. The signals from the counter 28 appear during the intervals bearing the corresponding designations in FIG. 3. Accordingly, since characters are generated during the horizontal time intervals H0-H4, the output signals H0-H4 from the counter 28 are applied to a raster encoder 32.

A second timing input for the encoder 32 is supplied by a vertical counter 34, which is similar to the counter 28. The counter 34 counts the t.sub.s signals, which are applied by way of an AND gate 36. Specifically, the counter 34 increases its count at the end of each displayed line of characters (FIG. 3).

The counter 34 has eight states and eight corresponding output signals, V0-V6, which correspond in turn to the intervals V0-V6 in FIG. 3, and also a state V7. These signals are applied to the raster encoder 32 as shown. The counter is cleared to its V0 state by the output of the vertical delay unit 22.

A third input for the encoder 32 is the content of a character register 38 which contains the codes for the various characters to be displayed. In the present example, where the characters are all numerals, the codes in the register 38 will merely be the binary representations of the numerals to be displayed.

The output of the encoder 32 is applied to the summing circuit 14 by way of a gate 40 and an OR circuit 42. The gate 40 is enabled by the coincidence of two signals. The first is a horizontal enabling signal from a flip-flop 44. The flip-flop 44 is set, through an inverter 45 by the leading edge of the H0 signal and reset by the trailing edge of the H4 signal. It is thus set during the intervals H0-H4, i.e. the horizontal time intervals during which each of the characters is displayed.

The second enabling signal for the gate 40 is a vertical enabling signal provided by the output of an inverter 46 whose input is the V7 signal from the vertical counter 34. Thus the vertical enabling signal is applied to the gate 40 when the counter 34 is in any of its states V0-V6, i.e. the vertical intervals during which the characters are generated (FIG. 2). When the counter 34 reaches its V7 state, the character generator 16 has completed the generation of the displayed characters. At this time the vertical enabling signal from the inverter 46 ceases, thereby disabling the gates 40 and 36.

This cuts off the output of the encoder 32 from the video channel. It also prevents the counting of further t.sub.s signals until the next delayed vertical sync signal clears the counter 34. By varying the delay in the vertical delay unit 22 one may thus adjust the vertical position of the characters in the video display. Similarly one may adjust the horizontal position of the characters by variation of the delay in the horizontal delay unit 20.

As shown in FIG. 2 the character register 38 is a circulating shift register having a stage for each of the characters to be displayed. Thus in the present example the register 38 contains 12 stages. Eleven of these are conventional shift register stages 38a-38k. The twelfth stage is a counter 48.

More specifically, each stage of the register 38 has sufficient capacity for the code of a single character. When only numerals are to be displayed, four bits are required for a binary representation of the decimal numerals 0-9. Accordingly, each register stage contains four binary storage elements. The contents of these elements are shifted in parallel from stage to stage in response to the H7 pulses.

The counter 48 may be a conventional binary counter arranged internally for decimal operation. Thus, it advances its count by one in response to a CI pulse and, whenever its content is a nine, the receipt of a further CI pulse clears it to 0, with the corresponding emission of a carry pulse (CO). The counter 48 has four character output lines, 48a-48d, that provide the input signals for the raster encoder 32 (FIGS. 1 and 3).

The circuit of FIG. 2 also includes a carry shift register 50 in which each stage has a capacity of one bit. The carry register 50 contains any carry bits that have to be stored temporarily. A principle reason to use a carry register is the order in which a string of characters is displayed on a television screen. Normally, the electron beam traces each line from left to right. Thus the higher order, tens, digits are fed to the raster encoder 38 before the lower order, ones, digits.

Illustratively, if the minute count is 29 and 2 will pass through the counter 48 before the 9 and when the 9 is in the counter 48, the 2 will be in the register stage 38A. Then, when the minute count is to be advanced, a CI pulse will clear the counter 48 to zero and cause the counter to emit a CO (carry) pulse. However, the CO pulse cannot add to the 2 in the tens position of the minute count until the 2 has circulated back to the counter 48. Therefore, the CO pulse passes to the carry register 50 where it sets a stage 50a correspnding to the stage 38a in the character register 38. The resulting carry bit in the stage 50a is then shifted through the register 50 by the H7 pulses in step with the shifting of the 2 through the register 38. As the 2 finally reaches the counter 48, the carry bit reaches the stage 50L. The stage 50L is connected to the counter so as to apply the carry bit to the counter as the CI signal. In the example under discussion, this increases the content of the counter 48 to 3. The minute count has thus completed its advance from 29 to 30.

The shift register 50 also handles carry signals generated for other purposes as described below. First, however, it will be helpful to review the preferred timing arrangement for the information updating operations.

As further shown in FIG. 2 a flip-flop 52 operates as a divide-by-two counter of the H7 signals emitted by the horizontal counter 28 (FIG. 1) after the right hand end of each character in the display (FIG. 3). The output of the flip-flop thus cycles once for each pair of characters in the display, i.e. once for each time segment. To insure the correct sequence of signals from the flip-flop 52, it is initially cleared by the delayed sync pulse from the horizontal delay unit 20, i.e. at the beginning of each line of a character display. Thus the flip-flop is in its cleared state during the display of the left hand character in each time segment and is in its set state during the display of the right hand character in each time segment.

As pointed out above, the first digit in each time segment requires seven horizontal time intervals, whereas the second digit requires ten intervals to accommodate the following punctuation mark. The flip-flop 52 controls the length of the counting sequence of the horizontal counter 28 to accomplish this difference in horizontal timing.

Specifically the SCND signal provided by the flip-flop 52 when it is in its set state passes through an inverter 58 whose output is therefore an FRST signal corresponding to the first digit in each time segment. The FRST signal enables the gate 60 (FIG. 1) to feed back the H7 signal from the counter 28 to a reset input of the counter by way of an inverter 61. Thus, at the beginning of the H7 time interval during the tracing of the first character in each time segment, the counter 28 is reset to a 0 count to limit it to seven horizontal time intervals for the first digit. On the other hand, during the tracing of the second digit of each time segment, the FRST signal is absent, the gate 60 is thereby disabled and the horizontal counter 28 counts through a full ten intervals, H0-H9.

The circuit of FIG. 2 also includes a divide-by-six counter 54 connected to count the H9 signals. The output of the counter 54 is decoded by a decoder 56. Since the H9 signal occurs only at the end of each time segment, the counter 54 counts the time segments and the decoder 56 provides an output on one of six output terminals during each time segment. These signals are designated in accordance with the display illustrated in FIG. 3. The counter 56 is also cleared by the delayed sync signal from the horizontal delay unit 20 and, when it is cleared, the decoder 56 emits the t.sub.MO signal.

The decoder 56 is enabled by the output of a gate 62 upon the coincidence of the SCND signal from the flip-flop 52 and the H6 signal from the horizontal counter 28. Thus the decoder 56 provides outputs only during the H6 time intervals immediately following the right hand digits of the respective time segments.

Since the system displays time, it includes a clock 64 synchronized to a stable frequency source such as the power line. Assuming a power frequency of 60Hz and a corresponding frequency of the clock 64, a frequency divider 66 divides the output of the clock to provide the basic one-second time intervals for the display. Preferably the divider 66 provides two output signals, one at 1Hz and the other at 2Hz, the latter output being used to set the correct time into the system initially.

More specifically, to set the time, the operator applies the 2Hz output of the divider 66 to the set input of a flip-flop 68 by way of a push button switch 70 and selector switch 71. The resulting output of the flip-flop 68 provides one enabling input for a gate 72. Also, by means of a selector switch 73, the operator selects, for example, the t.sub.MO output of the decoder 56 as a second enabling signal for the gate 72. Then, when the t.sub.MO signal and the set output of the flip-flop 68 coincide, the gate passes the next pulse from the oscillator 24 to the stage 50j of the carry register 50.

During the t.sub.MO signal, the second digit of the month is displayed, i.e. the second digit of the month is in the counter 48 in the character register 38. Therefore, the first digit of the day of the month is in the register stage 38k and the second digit of the day is in the register stage 38j. Accordingly, the output of the gate 72 inserts a carry bit into the carry register stage corresponding to the second digit of the day of the month.

Following the next H7 (shift) pulse this carry bit is in the carry register stage 50k. The content of the stage thus enables a gate 74 to pass the next pulse from the oscillator 24 to the flip-flop 68 and thereby reset the flip-flop to disable the gate 72.

The next H7 pulse moves the carry bit to the stage 50L and the content of this stage thereby enables a counter input gate 76. The gate 76 then passes the following H1 signal to the counter 48 as a CI signal to advance by one the content of the counter, i.e. advance the day of the month to the next date.

One-half second later the output of the counter 66 again sets the flip-flop 68 and the foregoing sequence is repeated to update the day of the month once again. This continues until the correct day of the month appears in the display, at which time the operator releases the switch 70 to prevent further advance of the date.

If the second, i.e. the least significant, digit of the date must advance past 9 to reach the correct date, the circuit performs a carry operation to advance the first digit in the manner described above.

In similar fashion the operator adjusts the other time segments contained in the character register 38 by setting the selector switch 73 to appropriate positions and actuating the switch 70 until the correct numbers appear in the display. The switch 73 is preferably provided with an indicator showing which time segment is adjusted for each position of the switch.

Ordinarily the last time segment to be adjusted in this manner will be the seconds segment. When the correct seconds count appears on the display, the operator moves the switch 71 to its other position to apply the 1Hz signal to the flip-flop 68. The seconds count in the character register 38 thus automatically advances in the manner described above, but at a rate of one per second, thereby to provide a continuous display and record of the seconds segment of the time.

When the seconds count reaches 60, it should reset to zero and the minute count should advance by one. The system accomplishes this by means of a decoder 78 that decodes the contents of the counter 48 and register stage 38a. When the combined content of these two stages reaches 60, the decoder 78 provides an output on a line 78a.

The outputs of the decoder 78 are applied to a coincidence logic unit 80 along with the time segment outputs of the decoder 56. If a signal on line 78a coincides with the t.sub.S signal, as it will when the minute count reaches 60, the logic unit 80 will emit an OF (overflow) signal. This signal clears the counter 48 and register stage 38a, thereby resetting the contents of both stages to zero.

At the same time, the logic unit 80 inserts a seconds-minutes carry bit (S-M) into the carry register stage 50b by way of an output conductor 80b. At this time, the corresponding stage 38b in the character register contains the right hand digit of the minute segment. Consequently, when this digit next reaches the counter 48, the carry bit in the stage 50b will reach the stage 50L. The H1 signal at the time will thus pass through the gate 76 as a CI signal for the counter 48, thereby increasing the minute count by one.

Even though the second count reaches 60, it remains at that figure only momentarily and consequently the viewer never perceives this number in the video display.

In similar fashion, when the minute count reaches 60, a decoder output on line 78a coincides with the t.sub.M signal to provide an OF signal from the logic unit 80 along with a minutes-hours carry signal (M-H) on line 80b. This clears the minute count to zero and advances the hour count.

When the hour count reaches 24, the decoder 78 provides an output signal on line 78b when the hour time segment is contained in the register stage 38a and counter 48. This will coincide with the t.sub.H signal and the logic unit 80 will again emit an OF signal, this time clearing the hour count to zero. The logic unit 80 will also provide an hours-days carry signal (H-D), but this time on a line 80d connected to the carry register stage 50d. Reference to FIGS. 2 and 3 will show that, at this time, the character register stage 38d contains the right hand digit of the day of the month. Accordingly, when that digit next reaches the counter 48, the carry bit inserted into the register stage 50d will reach the carry stage 50L. The resulting CI signal will thus advance the date by one day.

Since the number of days in a month varies according to the month, I have provided the logic unit 80 with a further input indicating the month, in order to control the date reading which will reset the day of the month and advance the month. Specifically, the decoder 78 has output lines 78d, 78e and 78f that provide signals when the date reaches 29 (February, non-leap year), 31 and 32, respectively. A month decoder 82 provides outputs when the contents of character register stages 38b and 38c correspond to months having 28, 30 and 31 days respectively. For example, if these two register stages contain the number 07, corresponding to July, the decoder 82 provides an output on line 82a, as it does for all other months having thirty-one days. The stages 38b and 38c contain the month whenever the stage 38b and counter 48 contain the day of the month.

Thus, whenever the combined content of the stage 38a and counter 48 is the day of the month, as indicated by the t.sub.D signal, and that content overflows, i.e. exceeds the number of days in the month indicated by the output of the month decoder 82, the logic unit 80 emits an OF signal to clear the stage 38a and counter 48. For example, with a month decoder output on line 82a during July, the logic unit 80 will emit its output signals when the day-of-the-month count reaches 32. The logic unit also transmits a days-months carry signal (D-M) over line 80b to the carry register stage 50b to advance the month count in the same manner that the minute and hour counts are advanced, as described above.

On the other hand, unlike the hour, minute and second time segments, the lowest day-of-the-month count is not zero but one. Accordingly, when the day-of-the-month count exceeds its maximum value, it must be reset to 01. This can be accomplished in several ways. For example, the logic unit 80 can be arranged to apply a signal to the counter 48, directly resetting counter to the count of one at the same time that the register stage 38a is cleared. Alternatively, the counter can be cleared as described above, along with the stage 38a, and then advanced by one count. The latter step can be accomplished by means of a CI signal developed after the counter 48 has been cleared and before the next shift (H7) pulse is applied to the register 38. However, I prefer to use the shift register 50 to develop a delayed count-advance signal.

Specifically, the carry register 50 includes a stage 50x that precedes the stage 50a. In this respect the stage 50x corresponds to the counter 48 in the shifting sequence. Thus when the day-of-the-month count overflows, the coincidence logic unit 80 applies a carry signal SC to the stage 50x by way of an output line 80x. This carry signal shifts into the stage 50a at the same time that the content of the counter 48 shifts into the stage 38a. Thus the carry signal reaches the carry register stage 501 the next time that the right-hand digit of the day of the month reaches the counter 48. The resulting CI signal then sets a 1 into the counter 48 to provide the correct day of the month.

The circuit of FIG. 2 may also include a switch (not shown) that changes the connections to the decoder 78 to provide a signal when the day of the month reaches 30 instead of 29, in order to take into account an increase in the number of days in February from 28 to 29 during leap years.

Whenever the combined content of the register state 38a and counter 48 is 13, the decoder 78 provides an output on line 78g. When this output signal coincides with the t.sub.MO signal, it indicates an end-of-the-year overflow of the month count. The logic unit 80 will therefore emit an OF signal to clear the register stage 38a and counter 48. The logic unit will also supply a months-years carry signal (M-Y) to carry register stage 50h over a line 80h. At this time the character register stage 38h contains the right hand digit of the year count. Therefore, when the latter digit reaches the counter 48, the carry signal will arrive at the stage 501 to advance the year count by means of the CI signal.

Moreover, since the month reading must be reset to 01 at the end of the year, the logic unit 80 applies an additional carry signal to the register stage 50x to reset the month count in the same manner that the day-of-the-month count is reset.

The punctuation marks shown in FIG. 3 are formed by a circuit shown in FIG. 1. With reference to the latter figure. the vertically centered dots following the month and day segments are generated by means of a gate 84 upon the coincidence of the V3 signal with either the t.sub.MO or t.sub.D signal as applied to an OR circuit 86. The output of the gate 84 is applied to the summing circuit 14 by way of the OR circuit 42.

Similarly, the colons following the hour and minute segments of the display are generated by a gate 88 upon the coincidence of outputs from OR circuits 90 and 92. The inputs for the OR circuit 90 are the t.sub.H and t.sub.MI signals and the inputs for the OR circuit 92 and the V0 and V6 signals.

Claims

I claim:

1. A character display system for displaying characters in raster form, said system comprising

A. a raster encoder that converts the combination of

1. vertical timing signals,

2 horizontal timing signals and

3 character code signals representing a character to be displayed into signals corresponding to a raster presentation of the character,

B. means for generating the horizontal timing signals,

C. means for generating the vertical timing signals,

D. a circulating character shift register that

1. shifts in response to shift signals,

2. contains, in the form of said character code, the characters to be displayed, and

3. includes

i. output conductors that provide to said encoder the character code input therefor, said characters being arranged in said shift register so as to be shifted to said output conductors in the order in which they are to be displayed,

ii. a counter as one stage thereof,

E. means for incrementing said counter to update the displayed information,

F. means for applying shift signals to said shift register in synchronism with the tracing of the portions of the raster lines associated with the respective displayed characters.

2. The system defined in claim 1 including

A. means for generating segment signals corresponding to the presence of predetermined parts of the displayed information in a predetermined stage of said character register, and

B. means for changing the contents of said predetermined register stage in synchronism with said segment signals, thereby to update the information displayed by said system.

3. The system defined in claim 2 including

A. a carry shift register having a stage corresponding to each stage in said character register and shifting in response to said shift signals,

B. means for inserting a bit into a first stage of said carry register when said counter overflows, and said first stage corresponding to the character register stage containing a first digit in a number whose next less significant digit is contained in said counter,

C. means for incrementing said counter whenever a second stage in said carry register, corresponding to said counter, contains said bit, thereby to advance said first digit when there is an overflow of said next less significant digit.

4. A system as defined in claim 3 having the capability of displaying different items of countable information having different moduli, said system comprising

A. a first decoder connected to decode the contents of one or more character register stages to provide output signals corresponding to predetermined contents of said one or more stages,

coincidence means for gating each of said decoder output signals with a segment signal, thereby to provide an overflow signal for each item when that item

1. is contained in said one or more stages and

2. exceeds the modulus for that item, and

C. means for clearing each item in response to the overflow signal corresponding thereto.

5. A system as defined in claim 2 having the capability of displaying different items of countable information having different moduli, said system comprising

A. a first decoder connected to decode the contents of one or more character register stages to provide output signals corresponding to predetermined contents of said one or more stages,

B. coincidence means for gating each of said decoder output signals with a segment signal, thereby to provide an overflow signal for each item when that item

1. is contained in said one or more stages and

2. exceeds the modulus for that item, and

C. means for clearing each item in response to the overflow signal corresponding thereto.

6. A system as defined in claim 5 including means for updating a first item of information in response to the overflow of a second item of information, and

A. in which said coincidence means further provides a carry signal upon the coincidence of an output signal with a segment signal, and

B. including means for applying the carry signal resulting from overflow of said second item to the stage of said carry register then corresponding to the character register stage containing the least significant digit of said first item, thereby to insert a carry bit into that carry register stage and consequently advance said least significant digit when that digit is next contained in said counter.

7. The system defined in claim 6 in which the items of information are time divisions and including

A. a clock and

B. means for advancing one of said time divisions in response to the output of said clock.

8. A system as defined in claim 7

A. in which said time divisions include the year, the month and the day of the month,

B. including a second decoder connected to said character register to provide month length signals indicating the lengths of months contained in the character register.

C. in which said coincidence means further responds to said month length signals in providing carry and overflow signals at the ends of months.