Traffic signal control system

Abstract

Fail-safe apparatus is provided for controlling traffic signals upon failure of an electronic computer. The computer normally controls traffic signals at a multiplicity of intersections. The computer and the fail-safe apparatus count the indication times of the traffic signals in synchronism. The indications of the traffic signals are controlled, upon failure of the computer, in accordance with signals generated corresponding to each countout of the indication times by the fail-safe apparatus.

Description

The invention relates to a traffic signal control system, and particularly relates to a centralized traffic signal control system for controlling traffic signals at a multiplicity of intersections from a central control station.

A centralized traffic signal control wherein traffic signals over a wide territory are centralizedly controlled at a central control station is well known. In such a traffic signal control, a central processing unit and an electronic computer, to which traffic informations at certain locations in the territory are supplied, are provided at the central control station. At the locations where traffic signals are installed, supersonic inductance or earth magnetism vehicle detectors for collecting traffic informations are profided. Such vehicle detectors are well known in which information of vehicle movements obtained by such vehicle detectors are supplied to the electronic computer. The computer computes traffic volumes, time occupancy and speed of vehicles according to the vehicle detection signals.

The computer computes traffic patterns to suit the conditions of vehicular traffic flows, and makes decision ot timings of traffic signals, such as times or respective phases of traffic signals. Such times of phases of traffic signals are counted by the computer. Each time the computer counts out the respective computed values, a signal for advancing the phase of traffic signals is transmitted to the traffic signals. The indication of the traffic signals is switched over in accordance with the signal transmitted from the central control station.

In the traffic signal control as above described, since the informations of traffic flows over a wide territory are continuously supplied to the computer, it is possible to systematically control traffic signals at a multiplicity of intersections.

However, if the computer fails, the systematic control of a multiplicity of traffic signals can no longer be performed. Therefore, a fail-safe apparatus, which continues, upon failure of the computer, systematic control of the traffic signals according to the traffic control pattern based on a pre-set program therein, is provided at the central control station. This fail-safe apparatus, as well as the computer, counts indication times of traffic signals and transmits signals for advancing phases of traffic signals. When the computer fails, each traffic signal is switched according to the signals for advancing phases from the fail-safe device, instead of the signals from the computer. In the fail-safe apparatus, one traffic control pattern may be pre-set, or two or three traffic control patterns, which are selected according to the time of day, may be pre-set. The failsafe apparatus counts the indication times independent of the computer during the normal operation of the computer. The phase advancing signals generated from the fail-safe apparatus are not supplied to the traffic signals during the normal operation of the computer.

When the computer fails, the phase advance signals generated by the fail-safe apparatus are supplied to the traffic signals. However, since the count of the indication times by the fail-safe apparatus is performed independent of the count by the computer, it takes a certain time for transfering the control of the traffic signals by the computer to the control by the fail-safe apparatus. Namely, if the computer fails within a short time after right-of-way of a certain main street has been given and the count of time by the fail-safe apparatus is, at that time, approaching to a value to finish the right-of-way of the main street, then the right-of-way of the main street given by the computer will be finished within a very short time by the phase advance signal from the fail-safe apparatus. Accordingly, in the prior art, each traffic signal was disconnected from the central control station at the time of failure of the computer, and controlled independently by corresponding local controller installed at corresponding intersection for a certain time and the control by the respective fail-safe apparatus was commenced at the time when the phase or indication of the fail-safe apparatus coincides with that of the local controller.

As can be understood from the above description, during the time when the traffic signals are disconnected from the central control station, the systematic control of the traffic signals cannot be performed. Thus the traffic flows over a wide territory may be very much confused for a certain time upon the failure of the computer.

The object of the present invention is to provide a traffic signal control system which can smoothly control traffic flows over a wide territory by immediately transfering the control of traffic signals by electronic computer to the control by fail-safe apparatus upon failure of computer.

According to the invention, a fail-safe apparatus is provided at the central control station or at other suitable location. In the fail-safe apparatus, indication times of traffic signals such as times of phases are pre-set.

The fail-safe apparatus counts the times of the indication of traffic signals in synchronism with the time count of the computer. The fail-safe apparatus is so constituted to commence the count of each time in accordance with the phase advance pulses generated by the computer, and also to commence the count of each time in accordance with signals transmitted from the respective traffic signals, as will be described later with respect to an embodiment of the invention. In other words, the count of times by the fail-safe apparatus according to the invention is not performed independent of the count of time by the computer.

When the computer is operating normally, the indication of the traffic signals is switched in accordance with the countout of the respective indication times by the computer, and when the computer fails, the indication of the traffic signals is switched in accordance with countout of the respective indication times by the fail-safe apparatus.

As described above, the unfavourable condition which has been involved in the prior art can be prevented even if the control of the traffic signals by the fail-safe apparatus is commenced immediately after the failure of the computer.

The nature of the invention and various further objects will be apparent from the following detailed description of a preferred embodiment of the invention, as illustrated in the accompanying drawings.

In the drawing:

FIG. 1 is a block diagram illustrating an embodiment of the invention,

FIG. 2 is a block diagram illustrating more particular constitution of fail-safe apparatus in FIG. 1,

FIG. 3 is an explanatory drawing showing synchronous time counting operation of computer and the fail-safe apparatus,

FIG. 4 is an explanatory drawing showing the manner of control before and after failure of the computer, and,

FIG. 5 is an explanatoly drawing showing the mutual relationship of phase advance signals for adjacent traffic signals.

In FIG. 1, a computer is shown as a block 100, and a fail-safe apparatus is shown as a block 200. The phase advance signal SC generated by the computer 100 is supplied respectively to one input terminal of gate circuits 300, 301 and 302. Signal S1 is respectively supplied to another input terminal of the gate circuits 300, 301 and 302. The phase advance signal SC supplied to the input terminals of the gate circuits 300, 301 and 302 appears at the output terminals thereof according to presence of the signal S1. The output signals of the gate circuits 300, 301 and 302 are supplied to OR gates 400, 401 and 402. The signal S1 is present when the computer 100 is normally operating, and is not present when the computer 100 fails.

The phase advance signal SF generated by the fail-safe apparatus 200 is respectively supplied to one input terminal of INHIBIT gates 500, 501 and 502. The signal S1 is supplied to respective other input terminal of the INHIBIT gates 500, 501 and 502. The signal SF generated by the fail-safe apparatus 200 appears at the output terminals of the gates 500, 501 and 502 when the signal S1 is absent. The output signals of the gate circuits 500, 501 and 502 are supplied to respective other input terminal of the OR gates 400, 401 and 402.

The output signals of the OR gates 400, 401 and 402 are transmitted to corresponding traffic signals 600, 601 and 602 through transmission lines 700, 701 and 702.

Accordingly, the indications of the traffic signals are switched, when the computer 100 is operating normally, in accordance with the phase advance signal SC generated by the computer 100, and are switched, when the computer 100 is in failure, in accordance with the phase advance signal SF generated by the fail-safe apparatus 200.

In the embodiment shown in FIG. 1, the fail-safe apparatus 200 is connected to the computer 100 through a control line CL and a bus line BL. When the computer 100 is operating normally, control parameters computed by the computer 100 are supplied to the fail-safe apparatus 200.

FIG. 2 shows the fail-safe apparatus 200. Registers 1, 2, 3, 4, 5 and 6 are provided in the fail-safe apparatus 200 for setting the respective time of phase of the traffic signals 600. The fail-safe apparatus may include additional registers and similar circuitry as described below for control of traffic signals 601, 602. The data to be stored in the registers 1, 2, 3, 4, 5 and 6 are emitted at a first bus line BL1 from the computer 100. The computer 100, in FIG. 1, is connected respectively to one input terminal of AND gates 21, 22, 23, 24, 25 and 26 through a bus line BL1, and also is connected respectively to another input terminal of the AND gates 21 through 26 through a first control line CL1. The output terminals of the AND gates 21 through 26 are respectively connected to the input terminals of the registers 1 through 6. The data signals from the computer 100 are conveyed on the bus line BL1 and appear at the output terminals of the AND gates 21 through 26 when a signal is supplied to a respective input terminal thereof from the computer 100 through the control line CL1. The output terminals of the AND gates 21 through 26 are respectively connected to the input terminals of the registers 1, 2, 3, 4, 5 and 6. Therefore, respective value of phase times computed by the computer 100 is stored in the registers 1, 2, 3, 4, 5 and 6 every unit time, for example, five minutes. In the present embodiment, the value of the time of a first phase is stored in the register 1, the value of the time of a second phase is stored in the register 2, and in sequence the value of the time of a sixth phase is stored in the register 6.

A counter 7 is provided for counting the respective time of phases. The counter 7 advances in accordance with clock pulses generated by a clock pulse generator 8, and is reset each time when a counter 9 advances. The clock pulses generated by the generator 8 are supplied to the input terminal of a frequency divider 10. A decoder 11 is provided for controlling the divider 10, and the divider 10 generates at its output terminal pulse signals by dividing the frequency of the clock pulses by the value instructed by the decoder 11. The decoder 11 is controlled by the computer 100 through a bus line BL2. The pulse signals appearing at the output terminal of the divider 10 are called "per-cent pulses." The output terminal of the divider 10 is connected to both input terminals of gate circuits 12 and 13. Both the output terminals of the gate circuits 12 and 13 are connected to input terminal of OR gate 14, and the output terminal of the OR gate 14 is connected to the input terminal of the counter 7.

The signal S1 is supplied to the other terminals of the gate circuits 12, 13. The set output terminal of a flip-flop 15 is connected to the remaining input terminal of the gate circuit 13.

Accordingly, when the computer 100 is operating normally, the counter 7 advances stepwise in accordance with the per-cent pulses with the flip-flop 15 being set. When the computer 100 fails, the counter 7 advances in accordance with the per-cent pulses regardless of the state of the flip-flop 15.

The flip-flop 15 is set by the signal SC transmitted from the computer 100. The signal SC is also supplied to the input terminal of OR gate 16. The output terminal of the OR gate 16 is connected to the reset terminal of the counter 7 and also to the counter 9. The output terminal of the counter 9 is connected respectively to one input terminal of AND gates 31, 32, 33, 34, 35 and 36. The respective other terminal of the AND gates 31, 32, 33, 34, 35 and 36 are connected to respective output terminals of the registers 1, 2, 3, 4, 5 and 6. The data signals stored in the registers 1, 2, 3, 4, 5 and 6 appear at the output terminals of the AND gates 31, 32, 33, 34, 35 and 36, respectively, in accordance with the supply of output signal from the counter 9 to the respective one input terminal of the AND gates 31 through 36. The output terminals of the AND gates 31 through 36 are connected to one input terminal of a coincidence circuit 17. The output terminal of the counter 7 is connected to the other input terminal of the coincidence counter 17. A signal S2 appears at the output terminal of the coincidence circuit 17 upon coincidence of the count value of the counter 7 with the data signal from the AND circuits 31, 32, 33, 34, 35 and 36. The output terminal of the coincidence circuit 17 is connected to the input terminal of a gate circuit 500 as well as to the reset input terminal of the flip-flop circuit 15.

The counter 9 advances stepwise in accordance with the output of the OR gate 16, and the output of the counter 9 in each stage opens a corresponding one of the AND gates 31 through 36 in sequence. The time value stored in each register 1 through 6 is supplied to the coincidence circuit 17 respectively in accordance with corresponding output of the counter 9 through the AND gates 31 to 36. Each time the counter 7 counts out the time stored in one of the registers 1 through 6, a signal S2 appears at the terminal of the coincidence circuit 17. The signal thus appears each time when one of the time value stored in the registers 1 through 6 has elapsed.

In the present embodiment, times of each phase computed by the computer are set in the registers 1 through 6 respectively, and the times of each phase are counted successively in the computer 100. The computer 100 generates the signal SC when it counts out the time of a respective phase. Since the counter 7 is reset by the signal SC, the signal S2 at the output terminal of the coincidence circuit 17 appears simultaneously with the signal SC generated by the computer 100.

As shown in FIG. 3(A), if, for any reason, the signal SC from the computer 100 is generated, during a phase (n), at the time t.sub.1 earlier than a time t.sub.2 where the signal S2 appears from the coincidence circuit 17, then the counter 7 is cleared at the time t.sub.1, and at the same time the counter 9 is advanced. Accordingly, in the next phase (n+1), both the advance signal SC from the computer 100 and the output signal S2 of the coincidence circuit 17 are generated at a same time t.sub.3. On the other hand, as shown in FIG. 3(B), if the output signal S2 of the coincidence circuit 17 appears at a time t.sub.1 earlier than a time t.sub.2 where the signal SC is generated by the computer 100, then the flip-flop 15 is reset at the time t.sub.1 thereby the percent pulses are no longer supplied to the counter 7 and later on, the counter 7 is reset and at the same time the flip-flop 15 is set by the signal SC generated by the computer 100 at a time t.sub.2. Accordingly, at the next phase (n+1), both the advance signal SC by the computer 100 and the output signal S2 of the coincidence circuit 17 appear at a same time T.sub.3.

As above described, when the computer 100 is operating normally, the counter 9 is advanced by the advance signal SC, and the count of time of the time counter 7 and the count of time of the computer 100 are commenced simultaneously, and accordingly, it will be understood that the time when the signal SC is generated by the computer 100 and the time when the output signal of the coincidence circuit 17 appears are in coincidence in every phase. Therefore, even if the computer 100 fails at a time t.sub.0 as shown in FIG. 4, since the phase of the counter 9 provided in the fail-safe apparatus 200 is same to that of the traffic signal, and the value of time count of the counter 9 in that phase is equal to that of the computer 100, the control of the traffic signals 600, 601, 602 can be switched from the control by the computer 100 to the control by the fail-safe apparatus without any troubles.

In the above, the description has been made in connection with the traffic signal at one intersection. However, as is well known by those skilled in the art, the signal SC from the computer 100 is transmitted to the traffic signals at adjacent intersections with an offset value OFV suited to the traffic flow. The mutual relationship between phase advance signals transmitted to those adjacent intersections are shown in FIG. 5. Namely, after the phase advance signal SCO has been transmitted to the traffic signal 500 shown in FIG. 1, the phase advance signal SC1 is transmitted to the adjacent traffic signal 501 with offset value OFV1 in that phase. Similarly, after the phase advance signal SC1 has been transmitted to the traffic signal 501, the phase advance signal SC2 is transmitted to the adjacent traffic signal 502 with offset value OFV2 in that phase. In this manner, the traffic signals are systematically controlled.

Since the relationship between the phase advance signals generated by the computer 100 and those of generated by the fail-safe apparatus 200 are as described above, the systematic control of the adjacent traffic signals can be realized immediately when the computer 100 fails.

Further, a third bus line BL3 is provided for the purpose of adjusting the phase of the counter 9, at a desired time, in coincidence with the phase of traffic signals instructed by the computer 100.

In the above described embodiment, the setting of the signal of data to the registers 1 through 6 is performed by the computer 100, however, it may be so constituted that the setting of signals of data to the registers 1 through 6 is performed manually. The values of data to be set in the registers 1 through 6 are not necessary in coincidence with the phase times computed by the computor 100. The only one condition necessary is that the sum of the data to be set in the registers 1 through 6 are equal with respect to the respective intersections to be systematically controlled.

Claims

What is claimed is:

1. A traffic signal control system for controlling traffic signals at a multiplicity of intersections, comprising,

a computer for counting first phase time of traffic signals and generating first signals for advancing phases of the traffic signals upon each countout of the first phase times,

a fail-safe apparatus, in which second phase times of the traffic signals are set, and to which said first phase advance signals generated by said computer are supplied,

said fail-safe apparatus commencing the count of the second phase times in accordance with said first phase advance signals from said computer when said computer is normally operating, and for generating second signals for advancing the phases of said traffic signals upon attaining a count of said set second phase times, and

logic switch means for transmitting said first phase advance signals from said computer when said computer is normally operating, and for transmitting said second phase advance signals from said fail-safe apparatus when said computer fails.

2. A traffic signal control system according to claim 1, wherein said fail-safe apparatus includes means responsive to said computer for setting the second phase times in said fail-safe apparatus by said computer.

3. A traffic signal control system according to claim 1, wherein said fail-safe apparatus includes means for manually setting said second phase times in said fail-safe apparatus.

4. A traffic signal control system according to claim 1, wherein said fail-safe apparatus includes:

means for generating clock pulses,

first means in which the second phase times are set and providing an output value indicative thereof,

second means for counting the clock pulses, and

third means for generating second phase advance signals upon coincidence of the count value of said second means with said output value of said first means.

5. A traffic signal control system according to claim 4, further including means for interrupting the supply of said clock pulses to said second means for a time period between the second generation of the phase advance signal by the third means and the generation of a first phase advance signal by said computer.

6. A traffic signal control system according to claim 4, wherein said first means includes a plurality of registers, each of said registers storing a value corresponding to a different phase time, said third means comparing the value of each of said registers with the count value of said second means for generating second phase advance signals upon coincidence thereof.

7. A traffic signal control system according to claim 6, further comprising means for sequentially supplying the output of each of said registers to said third means.

8. A traffic signal control system according to claim 7, wherein said means for sequentially supplying includes a counter for enabling a gating means at the output of each of said registers in a predetermined sequence.

9. A traffic signal control system according to claim 8, wherein said registers store a signal value therein supplied by said computer.