Street Traffic Signalling System

Obermaier , et al. March 18, 1

Patent Grant 3872422

U.S. patent number 3,872,422 [Application Number 05/369,725] was granted by the patent office on 1975-03-18 for street traffic signalling system. This patent grant is currently assigned to Siemens Aktiengesellschaft. Invention is credited to Peter Drebinger, Johann Hoisl, Anton Obermaier.


United States Patent 3,872,422
Obermaier ,   et al. March 18, 1975

STREET TRAFFIC SIGNALLING SYSTEM

Abstract

A street traffic signalling system in which the signal light units for each traffic flow of an intersection are independently regulated under the control of a central programmer with the signal unit for each traffic flow being controlled over a respective individual channel, by means of an actuating switch cooperable with and adapted to trigger respective time switches in the form of impulse counters, in combination with a timing generator which is common to the impulse counters of an intersection, which timing generator is periodically synchronized from the central station through synchronizing impulses at selected time intervals, for example, once per signalling cycle, and in which the impulses of the timing generator are sufficiently phase-shifted at the initiation of an order signal from the main station to prevent improper operation of the system and false indications in a test device.


Inventors: Obermaier; Anton (Munich, DT), Drebinger; Peter (Munich, DT), Hoisl; Johann (Ottobrunn, DT)
Assignee: Siemens Aktiengesellschaft (Berlin & Munich, DT)
Family ID: 5847877
Appl. No.: 05/369,725
Filed: June 13, 1973

Foreign Application Priority Data

Jun 15, 1972 [DT] 2229284
Current U.S. Class: 340/909
Current CPC Class: G08G 1/081 (20130101)
Current International Class: G08G 1/081 (20060101); G08G 1/07 (20060101); G08g 001/07 ()
Field of Search: ;340/40,41R,35,36

References Cited [Referenced By]

U.S. Patent Documents
1625990 April 1927 Garrett
1756490 April 1930 Mackall
3302170 January 1967 Jensen et al.
3675196 July 1972 Molloy et al.
Primary Examiner: Cooper; William C.
Assistant Examiner: Myers; Randall P.
Attorney, Agent or Firm: Hill, Gross, Simpson, Van Santen, Steadman, Chiara & Simpson

Claims



1. In a street traffic signalling system in which the signal light units for the traffic flow in each direction at an intersection are independently regulated under the control of a central programmer at a main station with the signal unit for each such traffic flow being controlled over a respective individual channel, the combination of an actuating switch, controlled by said programmer, for each channel at such main station, operative to transmit order signals to the associated unit, time switches, for the respective units, in the form of impulse counters adapted to be triggered in response to an order signal resulting from actuation of the cooperable actuating switch, a timing generator connected in common to the respective impulse counters of an intersection for supplying impulses thereto, said timing generator being connected to receive synchronizing impulses, from the main station, at selected time intervals, whereby such generator is periodically synchronized, for example, once per signalling cycle, said timing generator including means for effecting a phase-shifting of the timing impulses upon the initiation of an order signal from the main station, for preventing improper

2. A street traffic signalling system according to claim 1, wherein there is provided an additional individual channel over which said synchronizing

3. A street traffic signalling system according to claim 1, wherein said timing generator is connected to be responsive to the leading edge of an order signal as the synchronizing impulse.
Description



BACKGROUND OF THE INVENTION

The invention is directed to a street traffic signalling system in which the signal light units for each traffic flow at an intersection are to be independently regulated by a central programmer with the signal unit for each traffic flow being controlled from an individual control channel by means of an actuating switch cooperable with time switches which can be triggered thereby and are in the form of impulse counters.

The use of computers for the central control of the signal light units of a street traffic signalling system is becoming more and more extensive. However, their application is of primary use only when they are able to transmit all necessary orders for the control of the intersection from such central or main station whereby no programming operations are effected at the intersection itself. In order to achieve this result with a minimum of control channels, the signal light units for each traffic flow, which must be independently controlled, are controlled over a single individual control channel in cooperation with time switches which can be triggered by the actuating switch and which are in the form of impulse counters. This thereby permits the individual control of each signalling state at the intersection involved from the main station. However, no dangerous traffic conditions shall occur as a result of the release of opposing traffic flows as they may result from the geometry of the intersection, and thus safety devices must be provided at each intersection. As safety devices now employed operate with electronic switching circuits and thus would also determine short faulty switchings of the signal lamps, overlapping signal changes must be safely avoided.

BRIEF SUMMARY OF THE INVENTION

The invention is directed to the problem of efficiently combining these two requirements whereby the entire traffic operations of an intersection may be centrally programmed and determined with as few as possible transmission means between the intersection and the computer programmer in the main station, at the same time avoiding any possible dangerous traffic conditions which might arise by the utilization of fast reacting test devices.

According to the invention, these results are achieved in a street traffic signalling system employing a central programmer at the main station in which the signal light units for each traffic flow at the intersection involved, which must be independently adjusted, are respectively controlled over one individual control channel in cooperation with an actuating switch and timing switches triggerable thereby, and which may be in the form of impulse counters, which such impulse counters also being under the control of a local timing generator common to all of those at such intersection, and which timing generator can be synchronized from the main station by means of a synchronizing impulse at predetermined selected time intervals as for example once per programmed signalling cycle, with the impulses of the timing generator being sufficiently phase-shifted at the initiation of a change order signal from the main station, with such time delay preventing the undesired operation in the test device. Advantageously, the synchronizing impulse from the main station can be transmitted to the intersection over a special control channel, or such synchronizing impulse can be derived at the intersection from the impulse flank of a signal-changing order from the main station.

BRIEF DESCRIPTION OF THE DRAWINGS

In the drawings, wherein like reference characters indicate like or corresponding parts;

FIG. 1 is a diagram illustrating a simple traffic intersection with the traffic flows involved and associated signal units for the control thereof;

FIG. 2 is a circuit arrangement including a central programmer in the main station and a signal light unit or assembly at an intersection;

FIG. 3 is a time chart for the signal units regulating the intersection in accordance with FIG. 1;

FIG. 4 is a circuit diagram of a control device associated with each of the signal units;

FIG. 5 is a table illustrating various related states of certain components of the circuit of FIG. 4;

FIG. 6 is a circuit diagram of a control device for pedestrian signal units;

FIG. 7 is a circuit diagram of a timing generator for use in the circuit of FIG. 2;

FIG. 8 is a time chart in connection with the operation of the timing generator of FIG. 7; and

FIG. 9 is a circuit diagram of a test device for monitoring the signalling operations.

DETAILED DESCRIPTION OF THE INVENTION

Referring to FIG. 1, four traffic flows 1 through 4 directional, as well as four pedestrian flows, 11 through 14, are illustrated for the intersection Kr, adapted to be regulated by eight signal units or indicators, each of which contains the associated signals lamps for the desired control, the signal units Sg1 through Sg4 being provided for the control of the vehicle flow and the signal units sg11 through sg14 being provided for the regulation of pedestrian traffic. It will be apparent that traffic flows 3, 4 and pedestrian flows 13, 14 must be blocked when the vehicle traffic 1 is released to avoid the dangers that would otherwise arise. The corresponding red or stop lamps in the associated signal units Sg3, Sg4 and sg13, sg14 must thus be illuminated when the stop lamp in the signal unit Sg1 is extinguished. This result is monitored by a test device Pe as will subsequently be explained with respect to FIGS. 2 and 9, respectively.

In order to be able to control the traffic flows at the street intersection Kr from the main station Ze, illustrated in FIG. 2, control devices St1 to St4 are provided for the respective vehicle signal units Sg1 through Sg4 and control devices st11 through st14 are provided for the pedestrian signal generators sg11 through sg14 (For simplicity and to avoid mere duplication, signal unit sg2, sg11 and sg12 have been omitted from the drawing.).

All component elements illustrated in FIG. 2 are designated by reference characters comprising two letters, while component elements in the individual devices St, st, Tg, Pe, etc., are designated by reference characters comprising one letter.

The control devices St or st can be controlled in conjunction with a common timing generator Tg at the intersection Kr by the programmer Pg in the main station Ze, Pa control channel F1. The programmer pg is represented symbolically in FIG. 2 by a rotary selector Dr and information contact Inf. This is intended to broadly depict the actuating switches Sc1 through Sc14 in the buffer memory Sp as being sequentially actuated. From a practical standpoint, the programmer Pg would normally take the form of a computer or similar electronic system, and secondary devices usually employed with computers which can be in the form of intermediate memories, such as the buffer memory Sp.

With each change in signalling state, the orders therefore are not simultaneously transmitted from the main station Ze to the individual signal units Sg1 through sg14, but with a slight mutual phase shifting. As will be subsequently explained in connection with the test device Pe, this prevents the respective stop lamps involved from immediately lighting which otherwise might result in illumination of the control lamp S1 as a warning, with the entire signalling system possibly being simultaneously cut off at the intersection Kr by opening of the switch sch.

For a further explanation of this type of over-lapping signal change and the possibilities of avoidance thereof reference is made to FIG. 3. Section a.) of this figure discloses that the switches Sc1 through Sc4 or Sc11 through Sc14 only switches Sc1, Sc3, Sc4, Sc13, and Sc14 being illustrated in the figure.) are actuated sequentially within a time period between 0 and 1 second, and thus the actuation of the control devices St1 through st14 are actuated with a corresponding phase shift. Consequently, if the second impulse from the timing generator Tg were emitted when all order-designating signals had been transmitted for the desired signal change in this period between 0 and 1 second, possibly all control devices St1 through st14 would be simultaneously switched and thus also the signal units Sg1 through sg14 (compare section b of FIG. 3). The individual signal conditions red, red/yellow and green for the signal units Sg1 through sg14 are presented in section c of FIG. 3 in which the representative time period is correspondingly changed to provide a better illustration. The phase shifting of the timing impulses with respect to the order-designating signals is achieved by timing means in the timing generator Tg which allows a minimum time of 500 milliseconds to occur between the sychronizing impulse from the switch Sco and the timing impulses.

FIG. 3 also illustrates how an order-designating signal, for example, that for the signal generator Sg1 can also be employed as a synchronizing impulse. Thus, in Section (a.) the leading flank of the order-designating signal, as indicated in solid sectioning and the arrow, may be so employed.

FIG. 4 illustrates the construction of the control devices St for the individual vehicle signal units Sg. Assuming that no voltage is applied at the input q thereof, the flip-flop K1 will be in rest position over its inverted input, as indicated by the dot. The flip-flop K2 likewise will be in rest position. A voltage thus will appear at their outputs al, and the red lamp in the signal unit Sg will be illuminated.

If a voltage is now applied to the input q from the main station Ze, upon the appearance of a corresponding impulse from the timing generator Tg at the input u, K1 will be flipped into operational condition. A voltage thus will appear at the outputs of Nand gates G1 and G2 whereby the yellow lamp will be illuminated over the Nand gates G3, G4. Simultaneously, however, the counter Z1, which previously was maintained in zero position over its reset input R.sub.o, will be actuated and after a given time period, for example, after three seconds, the counter Z1 will emit an impulse which will be conducted to Nand gates G5, G6, which in cooperation with an impulse from the timing generator Tg, will flip the flip-flop K2 into operational condition. A voltage will therefore appear at the output K2 thereof which will be conducted over Nand gates G9, G10, and additional power switches, not illustrated, to extinguish the red and yellow lamps in the signal unit Sg and illuminate the green lamp. At the same time, the counter Z1 will be reset over input R.sub.o.

If the voltage at the input q ceases, as a result of it being cut off at the main station Ze, upon receipt of the second timing impulse from the input u, flip-flop K1 will return to its rest condition. This will result in a cutting off of the actuation of the green lamp over the Nand gates G9, G10, while Nand gates G1 through G4 will result in illumination on the yellow lamp without actuation of any further means. At the same time, the reset input R.sub.o of the counter Z1 is released and after a given time period, for example, 4 seconds, the flip-flop K2 will be returned to its rest position over Nand gates G7, G8, cooperably with the second impulse at the input u. Now, only the red lamp in the signal unit Sg will be illuminated and the counter Z1 will be returned into its zero condition. The control device St is also provided with two Nand gates G11, G12 whereby a voltage will always appear at the output v when only the red lamp is illuminated in the signal unit Sg.

FIG. 5 illustrates the conditions at various components of the control circuit as well as illuminating conditions of the red, yellow and green lamps in the signal unit Sg.

FIG. 6 illustrates a simple control switch st for the pedestrian signal sg. If no voltage is present at the input q', the flip-flop K3 will be in its rest position and the red lamp will be illuminated in the signal unit sg. However, if a voltage is applied to the input q' from the main station Ze, upon receipt of the next following impulse from the timing generator Tg, the flip-flop K3 will be flipped into its operational position, and the green lamp in the signal unit sg will be illuminated. Likewise, a voltage will appear at the output v only when the red lamp is illuminated.

FIG. 7 illustrates a circuit for the common timing generator Tg for the intersection Kr. Initially, no voltage is at the input w, so that flip-flops K4 and K5 are in operational position as the input e2 of the flip-flop K4 is inverted, as indicated by the dot. Alternating voltage of 50 Hz frequency is present at the input x and timing generator T thus will apply a frequency of 100 Hz of the flip-flops K4, K5 and the counters Z3, Z4. The latter are adapted to function as frequency dividers and respectively emit one impulse per second over Nand gates G15, G16 to the output y.

Upon the arrival of a synchronizing impulse over the switch Sc O, sco from the main station Ze, at the input w of the timing generator Tg, flip-flops, K4, K5 will be returned into their rest positions, one after the other, by the two following impulses of the timing generator T. At the intermediate phase, when the flip-flop K4 is in rest position and flip-flop K5 in operational position, the counters Z3, Z4 will receive a reset impulse over Nand gates G13, G14 applied at the reset inputs R.sub.o, R.sub.50, which synchronizes the counters Z3, Z4 and brings them into the counting position "500." The impulse following the synchronized impulse at output y will therefore be emitted after 500 milliseconds. This, as will be noted from FIG. 3, will shift the second impulse from the timing generator Tg with respect to the synchronizing impulse from the main station Ze by 500 milliseconds. Thus, any danger of an over-lapping signal-image change will be eliminated.

In FIG. 8, the phase relationship existing between the 20th and 21st seconds, illustrated on the time axis t are shown for the synchronizing impulse from the switch sco, the impulses from the timing generator T, the switching functions of the flip-flops K4, K5, Nand gate G14, counters Z3, Z4, as well as the time delay tv=500 milliseconds between the synchronizing impulse and the timing impulse of the timing generator Tg.

FIG. 9 illustrates the construction of the test device Pe in which the individual outputs v1 through v14 of the control devices St or st, illustrated in FIG. 2, have been interlinked in a predetermined logic over Nand gates G17, G18, G19 and the Or gates O1, O2.

Thus, no voltage will appear at the output of the common Nand gate G19 as long as the red lamps are illuminated in the respective signal unit under which circumstances no dangerous traffic conditions can occur. If one of such red lamps fails the warning lamp S1 will be illuminated in the main station Ze, over the common Nand gate G19, and simultaneously the entire signalling system at the intersection Kr will cut off by means of the switch Sch, sch.

Although various minor modifications might be suggested to those versed in the art, it should be understood that I wish to embody within the scope of the patent warranted hereon all such modifications as reasonably and properly come within the scope of my contribution to the art.

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