Electronic Stop-watch And Timepiece

Abstract

An electronic time-keeping device capable of functioning both as a stop-watch and as a timepiece. A signal generator constructed as a crystal oscillator provides a base frequency that is divided in a plurality of stages of frequency dividers and is then counted by counters that effect a time count displayed visually on a time display. The time count is applied from the counters to display elements through latch circuits constituting storage circuits under control of latch control means when the device functions as a stop watch and through these latch or storage circuits and other counting circuitry handling hour counts when the device functions as a timepiece. A reset unit resets the frequency dividers and the counters but is ineffective on the content of the counting unit consisting of the counters during a time count while the device functions as a stop-watch. A time-adjust unit receives count signals from the counters and generates a time-adjust signal applied to make time adjustments on the content of the counters when the device is used as a timepiece.

Description

BACKGROUND OF THE INVENTION

This invention relates generally to electronic watch movements and more particularly to a time-keeping device or apparatus capable of functioning both as an electronic stop-watch and timepiece.

Time-keeping devices are constructed as either stop-watches or as timepieces. Those that are stop-watches are used infrequently so that as to the number of times they are used stop-watches are expensive. Moreover, timepieces are not able to be used as stop-watches.

Furthermore, electronic timepieces having a signal generator that generates a base frequency which is then divided by a plurality of frequency-dividing stages are known. The output of the electronic circuitry may be used to drive an electromechanical system for driving the hands of a time-keeping device. These devices, however, are not able to function both as stop-watch and timepiece.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide an electronic time-keeping device having components and circuitry common to both a stop-watch and a timepiece mode of operation.

Another object is to provide a time-keeping device in which a reset unit allows resetting when the device is used as a stop-watch and is ineffective during a time count in the event resetting is inadvertently attempted during a time count.

Still another object is to provide a device having a time-adjust unit for making time adjustments when the device is being used as a timepiece.

The electronic time-keeping device has a signal generator constructed as a crystal oscillator generating a base freqeuncy which is divided in a plurality of stages and counted in counters effecting a time count. The time count as to minutes is stored temporarily in storage circuits and is then displayed on a display unit activated by decoder drivers. Counting of the hours is done in a separate counter and the hours are displayed on a display unit. The storage circuits and associated counters are used to effect time counts when the device functions as a stop-watch or as a timepiece. The hours of a time count are displayed when the device is operating in a timepiece mode of keeping time.

Counting control means comprise time-adjust means having means for generating a time-adjust signal applied to the counters to effect a time count adjustment thereby to adjust a time indication when the device is operating as a timepiece. Reset means are also provided in the counting control means to reset the counters and gate means therein render a reset signal ineffective in the event that resetting is attempted during a time count, for example when operating in a stop-watch mode.

BRIEF DESCRIPTION OF THE DRAWINGS

Other objects and advantages of the time-keeping device in accordance with the invention will appear from the following description and the novel features will be particularly pointed out in the appended claims and drawings in which:

FIGS. 1 and 2 are jointly a block diagram of a time-keeping device according to the invention.

FIGS. 3 and 4 are block diagrams of portions of other embodiments of a time-keeping device according to the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

In accordance with the drawing the time-keeping device embodying the invention comprises a signal generator 1 which is a crystal oscillator that produces a base or standard frequency which is applied to a plurality of frequency dividers 2,3,4 constructed as flip-flop circuits connected in cascade, which divide the base frequency to the desired unit of time. The divided frequency signals or pulses are applied to a group of counters 5-11. The last counter 11 is an hour counter connected through a connection S to the other counters which count time for minutes, seconds and fractions thereof.

Assume, for example, that the device is a 12 hour time-keeping device in which the time unit is 1/100 sec. and as a stop-watch it can function as such for 60 minutes, i.e. it can count for 60 minutes for operation in a stop-watch mode. Thus in the embodiment the first counter 5 counts 1/100 unit of a second, the second counter 6 counts 1/10 unit of a second, the third counter 7 counts 1 unit of a second, the fourth counter 8 counts 10 units of a second, the fifth counter 9 counts 1 unit of a minute, the sixth counter 10 counts 10 units of a minute and the seventh counter 11 counts 1 hour unit and 10 units of an hour.

The outputs of the counters are applied to latch or storage circuits 12-17 that temporarily store the time counts of corresponding counters 5-10. The outputs of the first six latch circuits 5-10 are applied to respective decoder driver circuits 18-23 which change the codes of the output signals of the corresponding latch circuit and at the same time amplify the outputs.

A separate decoder driver 24 is connected to the seventh or hour counter 11 and comprises a decoder 25 used for decimal transformation. Gate circuits 26,27 constructed as NAND gates are likewise connected to receive outputs of the hours counter and one of these has inverter 28 connected intermediate it and the hours counter 11.

The time count whether the device is operating as a stop-watch or a time-keeping device must be displayed. The minutes and seconds and fractions thereof are displayed on six display elements 29-34 connected to the decoder drivers 18-23 connected to the latch circuits which are connected to the counters which effect the counts of the minutes and seconds, etc. The outputs a-k of the decoder driver 24 connected to the hours counter 11 are displayed on 11 elements 35-45. The minute and seconds display elements 29-34 are, for example, light emission diodes that display numeral patterns and and the hour display elements 35-45 are lamps, but, of course, light-emitting diodes may be used instead of the lamps.

A time count start-stop switch unit 46 is provided and comprises two NAND gates 47,48. A grounded movable switch contact 49 is operable to contact either a fixed contact 49b connected to one NAND gate 48 or another stationary contact 49c connected to the other NAND gate 47. A J-K flip-flop 50 is connected to the NAND gates and has a terminal Q which connects the start-stop switch unit 46 to the frequency dividers at the first frequency divider 2 for applying signals thereto as later explained.

A latch control switch unit 51 has a latch control switch 52 comprising two NAND gates 53,54 and a grounded movable contact 52a connectable either to a fixed contact 52c electrically connected to one NAND gate 54 or another fixed contact 52b electrically connected to the other NAND gate 53. A J-K flip-flop 55 is connected to the NAND gates 53,54 and has a terminal Q connected to the latch circuits through a control connection l as shown for applying control signals thereto as hereinafter described.

Provision is made for time-adjusting when the device is being used as a time-keeping device. A time-adjust unit 56 has two parallel NAND gates 57,58 both connected to a third NAND gate 59 connected to an exclusive OR-gate 60 which is connected to the fifth counter 9 of the counting unit to apply a reset signal thereto, as later described, and receives an input from the fourth counter 8 as shown. Two grounded parallel switches 61,62 have movable contacts 61a, 62a connected to respective parallel NAND gates 57,58 operable to engage respective grounded fixed contacts 61b, 62b. The parallel NAND gates 57,58 are connected in parallel to the first, and second counters 5,6 to receive count signals therefrom as will be seen hereinafter.

A reset unit 63 makes provision for resetting the device during operation as a stop-watch and it is not effective during a time count. The reset unit has a reset switch 64 connected to two NAND gates 65,66 connected to a third NAND gate 67 providing connection through it to the frequency dividers and the counters. The connections are to the second and third frequency dividers 3,4 and the counters at a junction to a connection r between all of the counters. An inverter 68 is connected to the gate 67 and at a junction to the output connection between the start-stop switch and the frequency dividers. The reset switch 64 has a grounded movable contact operable to contact a fixed contact 64b connected to one of the NAND gates 66 and to contact another fixed contact 64c connected to another of the NAND gates 65.

DESCRIPTION OF THE STOP-WATCH MODE OF OPERATION

Next the action of the device when used as a stop-watch is explained. At first the switches are set in the following way. The movable contact piece 49a of the start-stop switch 49 is connected to the fixed contact 49b, and the output of the output terminal Q of flip-flop 50 is at a low value level (to be indicated by the logic value "L" hereafter), therefore, the input gate of the first divider 2 is in a closed state. The movable contact 64a of the reset switch 64 is connected to the fixed contact 64b, and the output of the output NAND gate 67 is at a high level (to be indicated by a logic value "H" hereafter), therefore, a state exists where a reset is not taking place. The movable contact 52a of the latch control switch 52 is connected to the fixed contact 52b, and the output of the output terminal Q of the reset unit flip-flop 55 is at the level H; therefore, the input gates of the latch circuits 12-17 are in opened states. The time-adjust switches 61,62 are both in a closed condition and the output of the NAND gate 59 is in a state of level L. The frequency dividers 2,3,4 and counters 5-11 are considered to have been already set.

When the movable contact 49a of start-stop switch 49 is changed over through the contact point 49b .fwdarw. the contact point 49c .fwdarw. the contact point 49b, the output of the NAND gate 48 assumes a level H .fwdarw. L .fwdarw. H, and at level H .fwdarw. L the flip-flop 50 is triggered. The output of the output terminal Q is reversed from level L to H to open the gate of the first divider 2. Consequently, the output frequency of the signal generator 1 is divided to 1/100 sec by the frequency dividers 2, 3, 4 and applied to the counter 5. When the time count has progressed and has been counted up to 9/100 sec and the next time signal of 1/100 of a sec is further supplied, a carry signal is generated and applied to the second counter 6 of 1/10 sec of the next step. Then with the lapse of time successive countings are carried out in the remaining counters 6,7... For example, when a time of 6 min 54 sec 21 has passed after the start-stop switch 49 has been closed, 1, 2, 4, 5, 6, are counted in the counters 5, 6, 7, 8, 9. These outputs are applied to the decoder drivers 18-22 through the corresponding latch circuits 12-16. Thus the numerical patterns 1, 2, 4, 5, 6 of display elements 29-33 are selected to display 6 min 54 sec 21. After that, the display time changes in correspondence with the lapse of time.

Suppose at the point in time when 7 min 54 sec 21 is counted in the counters 5-9, the latch control switch is closed, that is, the movable contact 52a is changed over in such a way that the contact is at point 52b .fwdarw. the contact point 52c .fwdarw. the contact point 52b. Then the output of the NAND gate 53 changes through levels H .fwdarw. L .fwdarw. H, and in the change from level H to L the flip-flop 55 is triggered, and the output of the output terminal Q is reversed from level H to L. Therefore, the input gates of the latch circuits 12-17 are all closed and thereby in the latch circuits 12-17 are stored 1, 2, 4, 5, 7. The outputs of the latch circuits 12-17 display statically 1, 2, 4, 5, 7, that is, the time 7 min 54 sec 21 on the display elements 29-33 through the decoder drivers 18-22. In this way it is possible to read out a particular time during the lapse of time.

In the meantime, counting of time is carried out in the counting unit, and the time elapsed aafter closing of the start-stop switch 49 is displayed again in the following way. The movable contact 52a of the latch control switch 52 is changed over through the contact point 52b .fwdarw. the contact point 52c .fwdarw. the contact point 52b to reverse the output of the terminal Q of flip-flop 55 from level L to H, and the gates of the latch circuits 12-17 are opened. Thus the outputs of the counters 5-10 are supplied to the decoder drivers 18-23 through the latch circuits 12-17 making the display elements 29-34 display the time elapsed.

RESETTING OF THE COUNTING UNIT

Resetting of the counting unit is carried out as follows. By actuating the start-stop switch 49, the output of the terminal Q of flip-flop 50 is reversed to the level L and the gate of the first frequency divider 2 is closed. Then, the movable contact 64a of the reset switch 64 is changed over to the contact point 64c, and the output of NAND gate 65 is reversed from the level L to H to keep the input of the NAND gate 67 at the level H. Since the other input of the NAND gate 67 has been supplied the output level H of flip-flop 50 is reversed by the inverter 68, the output of the NAND gate 67 assumes the level L. As a result, the frequency dividers 3,4 and the counters 5-11 are reset.

This resetting does not occur, however, when a counting action is being performed in the counting unit, namely, when the input gate of divider 2 is in an open state. More precisely, when the input gate of the divider 2 is in the open state, the output of the terminal Q of flip-flop 50 is at the level H. Accordingly, the level L is supplied to the input of the NAND gate 67 through the inverter 68. Therefore, whatever level is supplied to the other input of the NAND gate 67, the level thereof is kept at level H, so that resetting is not effected.

DESCRIPTION OF TIMEPIECE MODE OF OPERATION

Next, an explanation is given of the device when used for time display as a timepiece. The state of each switch is understood to be the same as in the initial state assumed in the explanation of the action in the stop-watch mode. Assume a case when the time is adjusted to a correct time of 3 o'clock 25 min 00 sec, for example. The present time is provisionally taken as 3 o'clock 23 min. When the movable contact 62a of the time adjust switch 62 is opened, an input of the NAND gate 57 assumes the level H, generating a time signal of 1/100 sec in the output of the NAND gate 59. This time signal of 1/100 sec is supplied to the counter 9 through the exclusive OR-gate 60. a counting operation then is performed by the counters 9, 10, 11 and at the point in time when the counter 11 counts 3, the switch 62 is closed, thereby the supply of a time signal 8 1/100 sec to the counter 9 is stopped. Next, by opening the time adjust switch 61, an input of the NAND gate 58 is kept at the level H, and a time signal of 1/10 sec is supplied to the counter 9 through the NAND gates 58,59 and the exclusive OR-gate 60. When the counter 9 counts 4 and the counter 10 counts 2, that is when 24 minutes have been counted, the time adjust switch 61 is closed. After that, at the point in time when the counter 9 counts up to 5, the input gate of divider 2 is closed by the action of the start-stop switch 49. Consequently, the counters 7, 8, 9, 10, 11 store 3 o'clock 25 min which has been reached, the input gate of the frequency divider 2 is opened by actuating the start-stop switch 49 and the time is successively counted. The time is displayed through the latch circuits and the display unit.

In case the time of adjustment is a little before noon, the adjustment may be made in such a way that by resetting the divider stages and the counting unit with the reset switch unit so when the time count corresponds to noon, actuating the start-stop switch 49 at once to open the input gate of divider 2 starts the time count.

The hour display is indicated by the lamps 35-45, for example, when it is 3o'clock, the lamp 37 is lighted. But during the time from 0 to 1 o'clock no lighting occurs in order to reduce consumption of electric power. If it is desired to display 0 o'clock clearly this is possible by connecting a lamp in the display unit to the output) terminal for 0 o'clock of the display actuating unit and supplying electric power thereto as in the other display elements.

In this embodiment the time count of the stop-watch was taken as 60 min maximum, but in a stop-watch for longer periods that need the hour unit it may be arranged by providing a latch circuit for the unit of an hour as shown in FIG. 3. In this alternative embodiment, the output of the counter 11 is supplied to the dispslay actuating unit 70 through a latch circuit 69.

The two kinds of signals of the time-adjust switch 56, the signals of 1/100 sec and 1/10 sec, are utilized in the embodiment described but the device need not be limited to these signals and any required time signals may be used.

In this embodiment the time was illustrated as displayed on a twelve hour display, but it is possible to have a 24 hours display by using a 24 notation counter and others, for example, a digital display 72, as shown in FIG. 4, may be used instead of a time display with lamps, provided electric power consumption is not critical.

Claims

What we claim and desire to secure by Letters Patent is:

1. An electronic time-keeping device usable as a stop-watch and as a timepiece comprising, a signal generator for generating pulses having a base frequency, frequency-dividing means dividing the base frequency in time, time count start-stop means for controlling a time count, counting means for counting the output pulses of said frequency-dividing means and developing therefrom signals representative of a time count having predetermined units of time, latch means comprising storage circuits receptive of said signals representative of a time count, latch control means to control storage of said time count signals to cause said device to function as a stop-watch means, display means for displaying a time count when said device functions as a stop-watch and as a timepiece and in which said time count start-stop means develops a signal output maintaining said counting means in a counting state, and includes counting means for controlling the content of a time count of said counting means comprising reset means for generating a reset output signal applied to said counters and gate means receiving a signal from said counting start-stop means and said reset output signal from said reset means rendering the reset output signal ineffective when said time count start-stop means develops said output signal thereof for maintaining said counting means in said counting state.

2. An electronic time-keeping device usable as a stop-watch and as a timepiece according to claim 1, in which said counting control means includes time-adjust means having means for generating a time-adjust output signal applied to said counting means to effect a time count adjustment to thereby adjust a time indication on said display means, and gate means receiving time count signals from said counting means and said time-adjust output signal applying said time-adjust output signal to said counting means advancing the time count content of said counting means.

3. An electronic time-keeping device usable as a stop-watch and as a timepiece comprising: a signal generator for generating pulses having a base frequency, frequency-dividing means dividing the base frequency, time count start-stop means for controlling a time count, counting means for counting the output pulses of said frequency-dividing means and developing therefrom signals representative of a time count having predetermined units of time, latch means comprising storage circuits receptive of said signals representative of a time count, latch control means for selectively controlling said latch means to continuously store one time count signal corresponding to a desired stop time thereby defining a stop-watch mode of operation and to successively store each time count signal thereby defining a time-piece mode of operation, and display means for displaying a time count when said device functions in said stop-watch and said timepiece modes of operation, wherein said counting means has means enabling it to continuously count when said latch means continuously stores one time count signal during the stop-watch mode to permit a plurality of time counts to be displayed during one timing sequence in the stop-watch mode.

4. An electronic time-keeping device according to claim 3, wherein said time count start-stop means develops an output signal for maintaining said counting means in a counting state and wherein said device further comprises counting control means for controlling the content of a time count of said counting means comprising reset means for generating a reset output signal applied to said counters and gate means receiving a signal from said counting start-stop means and said reset output signal from said reset means rendering the reset output signal ineffective when said time count start-stop means develops said output signal thereof for maintaining said counting means in said counting state.

5. An electronic time-keeping device according to claim 4, wherein said connecting control means includes time-adjust means for generating a time-adjust output signal applied to said counting means to effect a time count adjustment to adjust the time indication on said display means and gate means receiving time count signals from said counting means and said time-adjust output signal for applying said time-adjust output signal to said counting means to advance the time count content of said counting means.