U.S. patent number 3,845,243 [Application Number 05/336,598] was granted by the patent office on 1974-10-29 for system for producing a gray scale with a gaseous display and storage panel using multiple discharge elements.
This patent grant is currently assigned to Owens-Illinois, Inc.. Invention is credited to Theodore C. Baker, Ellsworth M. Murley, Larry J. Schmersal.
United States Patent |
3,845,243 |
Schmersal , et al. |
October 29, 1974 |
SYSTEM FOR PRODUCING A GRAY SCALE WITH A GASEOUS DISPLAY AND
STORAGE PANEL USING MULTIPLE DISCHARGE ELEMENTS
Abstract
A method and system for producing a gray scale in a gas
discharge storage and display panel. The discharge panel is divided
into a number of discharge regions each having the same number of
storage and discharge areas which number is equal to the number of
gray levels to be produced. In synchronism with the line by line
scanning of an image a plurality of storage means are loaded for
each picture element scanned with a number of information bits
which corresponds to the intensity of the picture element scanned.
After the scanning of each image line the stored information
corresponding to that line is read out to excite the appropriate
number of discharge areas in each discharge region. When viewed
from a distance a gray scale is produced.
Inventors: |
Schmersal; Larry J. (Toledo,
OH), Baker; Theodore C. (Toledo, OH), Murley; Ellsworth
M. (Toledo, OH) |
Assignee: |
Owens-Illinois, Inc. (Toledo,
OH)
|
Family
ID: |
23316819 |
Appl.
No.: |
05/336,598 |
Filed: |
February 28, 1973 |
Current U.S.
Class: |
348/797;
348/E3.014; 315/169.4; 345/690; 345/63; 315/169.1 |
Current CPC
Class: |
H04N
3/125 (20130101) |
Current International
Class: |
H04N
3/10 (20060101); H04N 3/12 (20060101); H04n
005/66 () |
Field of
Search: |
;178/73D ;340/324M
;315/169R,169TV |
References Cited
[Referenced By]
U.S. Patent Documents
Primary Examiner: Richardson; Robert L.
Attorney, Agent or Firm: Wedding; Donald Keith
Claims
1. A system for producing a gray scale in a cross conductor gas
discharge storage and display panel having discharge regions, each
discharge region including a plurality of storage and discharge
areas disposed laterally across said panel which correspond to the
crossing areas of said conductors, comprising; means for scanning
an image field and producing an image signal corresponding thereto,
means for defining a plurality of discrete gray level signal
magnitudes which correspond to a plurality of discrete gray level
magnitudes which said image signal exceeds, means for generating a
number of information bits from the part of said image signal
corresponding to each image element of said image field, the number
of information bits generated for each part of said image signal
corresponding to the highest gray level signal magnitude which said
level detector determines that the part exceeds, means for storing
the information bits for each line scanned at least for the
duration of that line scan, and means for reading out the stored
information bits for exciting the discharge areas of each discharge
region of the panel line by line with signals corresponding to said
information bits so that the number of areas in each discharge
region excited corresponds to the gray level associated with the
part of the image field to which that region
2. The system of claim 1 wherein said storage means includes a
plurality of sub-storage means equal in number to the number of
lines of storage and discharge areas located in each discharge
region, means for loading information bits corresponding to each
scanned line of image signal into all of said sub-storage means;
and means for sequentially reading out said sub-storage means to
sequentially excite the lines of discharge areas of
3. The system of claim 2 wherein each of said sub-storage means
comprises a serial shift register, said level detector means has a
plurality of outputs equal in number to the number of discrete gray
levels and includes means for causing one or more of said outputs
to go high depending on the detected gray level magnitude of said
image signal, a clock means for producing said information bit
signals, and gate means connected between said clock means and said
serial shift registers for allowing a plurality of bit signals
equal in number to the number of outputs of said level detector
which are high to load said shift registers for each image
4. The system of claim 3 wherein each serial shift register
includes at least as many bit storage positions as the number of
discharge areas in a row of said panel if it is excited column by
column and wherein the clocks signal output of said clocks means
activates a divider means for dividing said clock signal output
into a number of signals equal to the number of bit positions in
each shift register corresponding to one of said regions,
5. The system of claim 4 wherein said level detector means includes
a plurality of Schmitt triggers.
Description
This invention relates to a method and system for producing a gray
scale in a gaseous discharge storage and display panel. Since a
gaseous discharge panel such as a plasma panel is an on-off device,
light intensity emitted therefrom cannot inherently be varied. This
represents a serious disadvantage for a display device as it is
frequently desirable to display an image having variable shades of
brightness.
It has been discovered that a gray scale can be produced in a
gaseous discharge panel if multiple discharge areas are used for
each picture element scanned. The discharge panel is thus divided
into a number of discharge regions, each having the same number of
discharge areas. A different number of discharge areas are excited
to produce different gradations of gray.
It is thus an object of the invention to provide a method and
apparatus for producing a gray scale in a gaseous discharge
panel.
It is a further object of the invention to provide a method and
apparatus for displaying a half-tone picture with a gaseous
discharge panel.
The above objects are accomplished by providing a gaseous discharge
and storage panel which divided into a plurality of discharge
regions, each region having a given number of discharge areas. In
synchronism with the line-by-line scanning of an image, a pair of
shift registers are loaded for each picture element scanned with a
number of information bits which corresponds to the intensity of
the picture element scanned. The shift registers are read out to
the discharge panel line-by-line and excite the appropriate number
of discharge areas in each discharge region to produce the gray
scale.
The invention will be better understood by reference to the
accompanying specification and the drawings in which:
FIG. 1 shows the lay-out of crossed conductors of storage display
panel 53 of FIG. 2.
FIG. 2 is a diagram of a gray scale producing system according to
an embodiment of the invention.
FIG. 3 is a diagram of the waveforms produced at various circuit
points of the diagram of FIG. 2.
FIG. 4 is a detailed diagram of gray scale converter 14 of FIG.
2.
In the embodiment of the invention shown in FIG. 2 a gray scale is
produced on gaseous discharge storage and display panel 53. While
for ease of illustration panel 53 in FIG. 2 is shown as having only
5 picture elements and 10 conducting elements per scanning line, in
an actual device several hundred picture elements and conducting
elements would be used.
The panel 53 shown in FIG. 2 can, for instance, be the gas
discharge memory and display panel disclosed in U.S. Pat. No.
3,499,167 assigned to the same assignee as the present application.
The sustaining voltage of panel 53 is defined as being that voltage
which when applied to the conducting elements is great enough to
cause continued discharge after the excitation voltage is removed.
A voltage at least as great as the sustaining voltage is applied to
all of the conducting elements of panel 53 by a sustaining voltage
generator (not shown in FIG. 2) to provide the panel with a memory
capability. The output of the sustaining voltage generator is
further arranged to be small enough so that it will, by itself, not
cause excitation of the discharge areas but great enough so that
when combined with the excitation voltage provided by the
combination of the voltage output of line voltage generator 55 and
the output signals of buffers 32 and 33 excitation of the discharge
areas is effected. The excited discharge areas may be erased row by
row by providing another voltage from erase voltage generator 54
which is of a magnitude and phase so that for each row to which it
is applied the resultant voltage of it and the voltage outputted by
the sustaining voltage generator is less than the sustaining
voltage.
The conducting elements of storage and display panel 53 are laid
out in a unique manner according to the invention as can be best
seen by referring to FIG. 1 which shows a portion of the panel 53
of FIG. 2. In FIG. 1, it is seen that both the row conducting
elements 101, 102, 103 and 104 and column conducting elements 105,
106, 107, 108, 109 and 110 are arranged in pairs to provide a
number of discharge regions 115 and 120. Each discharge region is
comprised of four discharge areas, such as 111, 112, 113 and 114 in
FIG. 1. Each discharge area corresponds to the crossover area of a
row conducting element and a column conducting element. According
to the invention, each of the discharge regions 115 to 120
corresponds to a picture element scanned and the gray scale is
produced by exciting either 1, 2, 3 or 4 of the discharge areas
within the discharge region. For instance, the brightest gray scale
level would be produced at discharge region 115 in FIG. 1 by
exciting all of the discharge areas 111, 112, 113 and 114 whereas
the next brightest level would be produced by exciting only three
of the areas, the next-to-dimmest level would be produced by
exciting only two of the areas, and the dimmest level would be
produced by exciting only one of the areas. While the illustrated
embodiment of the invention utilizes four gray levels and four
discharge areas per discharge region it is to be understood that it
is within the scope of the invention to use any number of gray
levels and discharge areas per discharge region.
In FIG. 2 each of the shift registers 32 and 33 has a number of bit
positions equal to the number of discharge areas in a row of panel
53. The image to be reproduced with panel 53 is scanned by vidicon
36 and shift registers 32 and 33 are loaded during the scanning of
a single line in accordance with the gray tones of the line
scanned. Positions in shift register 32 corresponding to leads 130
and 131 and positions in shift register 33 corresponding to leads
132 and 133 are filled with bits corresponding to the gray level of
the first picture element scanned. That is, if the first picture
element corresponds to the brightest gray level scanned, all four
positions of shift registers 32 and 33 are filled, whereas if the
element corresponds to the next-to-brightest level scanned, only
three of the positions are filled, if it corresponds to the
next-to-dimmest gray level, only two of the positions are filled
and if it corresponds to the dimmest level, only one of the
positions is filled. Each of the scanning elements of a scanning
line are loaded into the shift registers in this manner and at the
end of the scanning line, the contents of the shift registers are
read out to panel 53 at the same time that line voltage generator
55 excites the appropriate row conducting element. If in FIG. 2
rows 1 and 2 of panel 53 were being excited corresponding to the
first image line scanned, then the bits from shift register 32 from
the bit positions corresponding to the leads 130 and 131 would
excite discharge areas 111 and 112 while the bits from shift
register 33 corresponding to the leads 132 and 133 would excite
discharge areas 113 and 114. Region 115 of the panel 53 would thus
have either one, two, three or four discharge areas excited in
accordance with the gray level of the first scanning element of the
image.
The operation of the embodiment shown in FIG. 2 will now be
described in greater detail. Vidicon 36 is caused to sweep a raster
to scan the image by making the horizontal sweep frequency many
times the vertical sweep frequency. While the embodiment or the
invention has been illustrated using a vidicon as the image pick-up
tube, is to be understood that any suitable image pick-up device
may be used. Horizontal and vertical sweep voltage generator 37 is
arranged so that the horizontal sweep frequency divided by the
vertical sweep frequency equals the number of pairs of rows of
discharge panel 53, which will cause the vidicon to sweep a raster
having a number of scanning lines equal to the number of pairs of
rows of panel 53.
Clock 10, which may be a pulse generator such as an astable
multivibrator as known to those skilled in the art, is arranged to
generate a train of pulses having a period equal to the duration of
the horizontal sweep pulse divided by the number of positions in
the shift registers which, as indicated above, is equal to the
number of discharge areas in a row of panel 53. This insures that
the bits corresponding to each scanning line exactly fills the
shift registers.
As well as being fed to the vidicon, the horizontal sweep voltage
is fed on line 80 to threshold detector 81 which is arranged to
generate a signal on line 82 when the signal fed in on line 80
rises above a threshold value. This threshold value is set to be
very low so that effectively a signal appears on line 82 when the
horizontal sweep voltage begins. A voltage on line 82 triggers
one-shot multivibrator 84 which produces a pulse on line 86 causing
flip flop 38 to become set and to emit an output signal on line 40.
Threshold detector 81 is arranged to provide an output signal on
line 83 when the horizontal sweep pulse falls below the threshold
again which would occur at the end of the sweep voltage. The signal
on line 83 is fed to one-shot multivibrator 85 which generates a
pulse on line 87 to reset flip flop 38 and generate an output
signal on line 39. The clock pulses generated by clock 10 are fed
to gate 11 on input line 70. Gate 11 is arranged to allow the input
pulses to pass through to lines 82 and 83 only if a signal appears
at input 84 to which line 40 is fed. Since a signal appears on line
40, only during the time that the horizontal sweep voltage is
present, gate 11 passes clock pulses to lines 82 and 83 only during
the time that the horizontal sweep pulse is present.
The output of clock 10 at line 70 is shown at waveform 1 in FIG. 3.
The pulse train shown at waveform 1 is fed through gate 11 to delay
network 15 on line 83. The output of delay network 15 appears at
line 75 and is shown as waveform 2 in FIG. 3. The pulse train is
fed on line 82 to flip flop 12 which has two output lines 23 and
24. Flip flop 12 is arranged to change state each time a pulse
appears on line 82 and the output of flip flop 12 on line 23 is
shown at waveform 3 in FIG. 3. The output on line 24 is not shown
in FIG. 3 but is a waveform which is 180.degree. out of phase or
the inverse of waveform 3 of FIG. 3. The output appearing on line
23 of flip flop 12 also appears at output 71 of flip flop 12 and is
fed to flip flop 13. Flip flop 13 is arranged to change state each
time a positive going edge appears on line 71 and the output of
flip flop 13 on line 72 is shown at waveform 4 of FIG. 3.
The output on line 72 is fed to video gray scale converter 14 as is
the image signal output of the vidicon on line 87. Converter 14
which is shown in greater detail in FIG. 4 is arranged to produce
an output pulse corresponding to the input pulse on line 72 on
selected ones of output lines 26, 27, 28 and 29 in accordance with
the magnitude of the signal fed in on line 87. Thus, if the signal
fed in on line 87 corresponds to the brightest gray level, then
pulses will appear on all four of lines 26, 27, 28 and 29.
Waveforms 5, 6, 7 and 8 in FIG. 3 correspond to the pulses on lines
26, 27, 28 and 29 and for the column of pulses labeled C in FIG. 3
it is noted that pulses appear at 5, 6, 7 and 8 indicating that
column C corresponds to an image element of the brightest gray
level. If an image element corresponding to the next-to-brightest
gray level is scanned, then outputs appear on lines 27, 28, or 29
or pulse trains 6, 7 and 8 as indicated in column D of FIG. 3. If a
next-to-dimmest gray level element is scanned, then outputs appear
on lines 28 and 29 as shown at waveforms 7 and 8 in column E in
FIG. 3 while if an image element corresponding to the dimmest gray
level is scanned, an output appears only on line 29 or waveform 8
in column F of FIG. 3.
AND gates 16, 17, 18 and 19 each have three inputs fed thereto. The
output of delay network 15 on line 20, shown as pulse train 2 in
FIG. 3 is fed to each of the AND gates. The pulse train of output
23 of flip flop 12 shown as waveform 3 in FIG. 3 is fed to AND
gates 16 and 18 at leads 21 and 22 respectively, while the output
24 of flip flop 12 which is the inverse of the output 23 is fed to
AND gate 17 on line 25 and AND gate 19 on line 24. The third input
to AND gate 16 is the output 26 of gray scale converter 14, the
third input to AND gate 17 is output 27 of gray scale converter 13,
the third input to AND gate 18 is output 28 of the gray scale
converter and the third input to AND gate 19 is output 29 of the
gray scale converter.
It will now be demonstrated how either 1, 2, 3 or 4 bits are fed to
shift registers 32 and 33 for each image element scanned depending
on the gray level of the element. Turning first to the case of the
brightest gray level, which is represented at column C in FIG. 3,
it is seen that pulse outputs appear at 5, 6, 7 and 8 corresponding
to lines 26, 27, 28 and 29 of gray scale converter 24. During part
A of the cycle of waveform 3 inputted at inputs 21 and 22
respectively to AND gates 16 and 18 a pulse on line 20 shown at
waveform 2 of FIG. 3 is passed through the gates to output lines 90
and 92 respectively. These pulses are passed through OR gates 30
and 31 respectively and are inputted to shift registers 32 and 33
respectively. During part B of the cycle of waveform 3, the output
at line 24 of flip flop 12 goes positive and another pulse of
waveform 2 on line 20 is fed through AND gates 17 and 19 to lines
91 and 93 respectively to OR gates 30 and 31 and to shift registers
32 and 33 respectively. Shift registers 32 and 33 are shifted
serially by the pulses of waveform 2 appearing on line 75 and
insuring that each time a pulse is outputted from OR gates 30 or 31
there is a corresponding shift pulse inputted to shift registers 32
and 33. An entire line of bits corresponding to a scanned line is
thus fed to shift registers 32 and 33 until gate 11, responsive to
the absence of a signal on line 40 at the end of the scanning line
no longer passes the clock pulses.
If the image element scanned was at the next-to-brightest gray
level, then as shown in column D of FIG. 3 only three pulses would
be present at waveforms 6, 7 and 8 corresponding to lines 27, 28
and 29 and only one bit would be inputted to shift register 32
while two would be inputted to shift register 33. If the image
element scanned corresponded to the next-to-dimmest level as shown
at column E of FIG. 3, then only the pulses at waveforms 7 and 8
appearing at lines 28 and 29 would be present and two bits would be
inputted to shift register 33 while no bits would be inputted to
shift register 32. Where an image element corresponding to the
dimmest gray level is scanned, referring to column F of FIG. 3,
only a pulse of waveform 8 is present at line 29 and a single bit
is inputted to shift register 33.
The bits are shifted out of the shift register to excite the panel
in the following manner. At the end of each horizontal sweep
voltage signal the signal at output 40 of flip flop 38 disappears
and a signal appears on output 39 of flip flop 38. The signal on
line 39 is delayed by delay network 42 long enough to insure that
the last bit from the line just scanned is inputted to shift
registers 32 and 33 but short enough so that no bits from the next
horizontal scan line have been inputted to the shift registers. The
output from delay network 42 is fed to counter 43 which is "count
to five" counter the details of which are known to those skilled in
the art. Counter 43 is arranged to have five outputs 45 a to 45 e
and one output 44. The first signal appearing on line 88
corresponding to the end of the first line scanned causes counter
43 to emit an output signal on line 45 a, the second signal
appearing on line 88 corresponding to the end of the second line
scannned causes counter 43 to emit an output signal on line 45 b
and so on for the other outputs of the counter. Each time an output
signal appears on any of lines 45 a to 45 e, counter 43 is arranged
so that an output signal also appears on line 44. Lines 45 a to 45
e are connected respectively to activate lines 1, 3, 5, 7 and 9 of
erase voltage generator 54. Line 44 is connected to the parallel
shift input 140 of shift register 32, a signal on which causes all
of the serial information in shift register 32 to be shifted out in
parallel form to buffer 34. Thus, just after the first horizontal
sweep signal terminates, an output signal appears on output 44 of
counter 43 causing the information in shift register 32 to be
shifted out in parallel form to buffer 34. At the same time that a
signal appears on line 44 of counter 43, a signal appears on line
45 a of counter 43 activating line 1 of erase voltage generator 54
and causing the topmost row of panel 53 to be erased. Delay network
143 is connected to line 44 and after a delay just long enough to
insure that all of the information bits have been transferred from
shift register 32 to buffer 34 the output of delay network 143 is
inputted to the buffer at input 52 to shift all of the information
bits out of the buffer and into a row of panel 53. Each of the
output lines 45 a to 45 e of counter 43 is connected to a delay
network 46 a to 46 e respectively with the delay of each delay
network 46 a to 46 e being equal to the delay of delay network 143.
The outputs of the delay networks 46 a to 46 e connected
respectively to activate the lines 1, 3, 5, 7 and 9 of line voltage
generator 55. Hence, at the same time that the information
corresponding to the first line scanned is shifted out of buffer
34, a signal will appear at the output of delay network 46 a
causing line voltage generator 55 to generate a voltage at output
line 1 which is connected to the topmost row of the panel.
Discharges will appear at those discharge areas along the topmost
row at which information bits have been read out of buffer 1.
Hence, if the scanning were from left to right and if the first
picture element scanned were at the brightest gray level, then both
discharge areas 111 and 112 would emit light. If the second picture
element scanned were at the next-to-dimmest gray level, then
neither of the topmost discharge areas of discharge region 116
would emit light since only the bottom two discharge areas are
arranged to emit light when the next-to-dimmest gray level is
scanned. The voltage levels outputted from line voltage generator
55 and buffer 34 are arranged so that in combination with the
sustaining voltage, applied to the panel continuously during the
operation thereof as discussed above, the resultant voltages are
high enough to cause discharge at the appropriate discharge
areas.
The signal at input 52 of buffer 34 is delayed by delay network 49
and the delayed signal is inputted to parallel shift input 141 of
shift register 33 to parallel shift the information out to buffer
35. The combined delay times of delays 42, 143 and 49 should be
short enough so that at the time that the information is shifted
out of shift register 33, no new information from the next scan
line has been inputted thereto. Delay networks 47a to 47e have
delay times equal to the delay time of delay network 49 and the
outputs of delay networks 47a to 47e are fed to erase voltage 54 to
activate lines 2, 4, 6, 8 and 10 of the generator. Hence, at the
same time that the bits corresponding to the topmost scanning line
are shifted out of shift register 33 into buffer 35 line 2 of erase
voltage generator 54 provides erase voltage to the second row of
the display 53.
Delay network 50 is connected to input 141 of shift register 33 and
delays the signal at input 141 just long enough to insure that all
of the information from shift register 33 has been transferred to
buffer 35. After the delay period introduced by delay network 50, a
signal is provided to input 51 of buffer 35 which shifts all of the
information bits in buffer 35 to panel 53. Delay networks 48a to
48e are connected to the outputs of delay networks 47a to 47e and
each of networks 48a to 48e provides a delay equal to the delay
provided by delay network 50. The outputs of delay networks 48a to
48e are connected to line voltage generator 55 and are arranged to
activate output lines 2, 4, 6, 8 and 10 of generator 55. Hence, at
the same time that the outputs representative of the first scanning
line are shifted from buffer 35 to the column conducting elements
of the panel, line voltage generator 55 provides an excitation
voltage to the second row conducting element and discharge areas
along the second row of panel 53 are excited in accordance with the
locations of the information bits read out of buffer 35. At this
point, all of the appropriate discharge areas of the topmost two
rows of panel 53, corresponding to the first scanning line of the
image are excited and each discharge region such as 115 and 116
will have either 1, 2, 3 or 4 discharge areas excited in accordance
with the gray level of the part of the scanned image corresponding
to the discharge region. The delay networks are arranged with
respect to the sweep voltage so that immediately after the bits of
shift register 33 are shifted out, the shift registers begin
filling up with the bits corresponding to the next scanning line.
The same procedure takes place for each successive scanning line.
For instance, for the second scanning line leads 45b and the
outputs of delays 46b, 47b and 48b respectively activate erase
voltage generator output line 3, line voltage generator output line
3, erase voltage generator output 4, and line voltage generator
output line 4. In this way, the scanned image is displayed on the
panel line by line.
FIG. 4 is a detailed diagram of the video gray scale converter 14
of FIG. 2. In FIG. 4 vidicon 36 produces an image output signal on
line 87 which is fed to four level detectors 200, 201, 202 and 203
each of which may be any conventional electronic level detector as
known to those skilled in the art such as, for instance, a Schmitt
trigger. The gray level ranges are determined in advance and each
Schmitt trigger is set to provide on an output signal its zero
state output line when the input signal thereto exceeds the
predetermined level. In FIG. 4, Schmitt trigger 201 is set to
trigger at a higher level than Schmitt trigger 200, Schmitt trigger
202 is set to trigger at a higher level than 201 and Schmitt
trigger 203 is set to trigger at a higher level than Schmitt
trigger 202, corresponding to the different gray level ranges. Each
of the zero state output lines of the Schmitt triggers is connected
to the gating terminal of gates 205, 206, 207 and 208 respectively.
Gates 205, 206, 207 and 208 are operative to pass the signals
appearing at inputs 209, 210, 211 and 212 respectively when a
gating signal is present at the respective gating terminals of the
gates.
If the vidicon output signal on line 87 is greater than the
triggering level of Schmitt trigger 200 but not as great as the
triggering level of Schmitt trigger 201, then only the gating
terminal of gate 205 will become activated and the pulse signal on
line 72 present at input 209 of gate 205 will be passed through to
output line 29. In a similar fashion, if the vidicon output signal
on line 87 has a magnitude which is greater than the triggering
level of the Schmitt triggers 200 and 201 but not as great as that
of 202, then the pulse signal on line 72 will be passed through
both gates 205 and 206 and appear on both lines 29 and 28.
Likewise, vidicon output signals between the triggering levels of
Schmitt triggers 202 and 203 and vidicon output signals greater
than the triggering level of Schmitt trigger 203 will respectively
produce output pulse signals on lines 29, 28, 27 and lines 29, 28,
27 and 26.
While we have disclosed and described the preferred embodiments of
our invention, we wish it understood that we do not intend to be
restricted solely thereto, but that we do intend to include all
embodiments thereof which would be apparent to one skilled in the
art and which come within the spirit and scope of our
invention.
* * * * *