Electronically Programable Switching System

Abstract

A switching device comprises a plurality of control points and a plurality of switching elements, and each control point is associated with one or more switching elements. The switching elements are actuated by the presence of actuation information at the associated control point. A shift register having states related to the control points supplies actuation information to the control points in a predetermined sequence under the control of timing pulses which advance the states of the register whereby a series of combination of switching functions may be performed.

Description

The present invention relates to switching devices of the kind comprising a plurality of control points, each control point of the plurality being associated with a combination of one or more switching elements whereby the switching elements for each combination are adapted to be actuated by the presence of actuation information at the control point associated therewith, a shift register having states related to the control points of the plurality for supplying actuation information to the control points of the plurality in a predetermined sequence under the control of timing pulses which advance the states of the register whereby a series of combinations of switching functions may be performed, the intervals between occurrence of consecutive timing pulses determining the period of time for which actuation information is present at the respective control points, pulse supply means capable of supplying to the shift register timing pulses either recurring at relatively long intervals or recurring at relatively short intervals, means for deriving programme information from the actuation information present at respective control points, the derived programme information being applied to the pulse supply means for determining, in accordance with a programme, whether the timing pulses supplied to the shift register recur at relatively long intervals or recur at relatively short intervals.

Such switching devices are proposed in the applicant's co-pending Australian Pat. application Nos. 48775/72 and 49305/72.

In one known kind of switching device, the said pulse supply means include a first pulse source for producing pulses recurring at relatively long intervals, a second pulse source for producing pulses recurring at relatively short intervals and a selection circuit arrangement permitting timing pulses for supply to the said shift register to be derived from either the first pulse source or the second pulse source.

In an alternative known kind of switching device, the said pulse supply means includes a pulse source from whence timing pulses may be derived for supply to the shift register, the pulse source being adapted to operate in either a first mode of operation or a second mode of operation, the pulse source producing pulses recurring at relatively long intervals when operating in the first mode and producing pulses recurring at relatively short intervals when operating in the second mode. With this kind of switching device the said pulse source may be in the form of a relaxation oscillator, the repetition frequency of which is determined by the series combination of two capacitors one of which is shunted by the collector-emitter path of a transistor adapted to be rendered either conductive so that the pulse source operates in the said first mode or non-conductive so that the pulse source operates in the said second mode.

A switching device of the kind to which the invention relates generally also comprises programme selection means for providing selection information and comparison means for comparing selection information thus provided with actuation information present at respective control points of the plurality for determining, during the course of the selected programme, whether the timing pulses supplied to the shift register recur at relatively long intervals or recur at relatively short intervals. Switching devices comprising programme selection means are described in the aforementioned Australian Pat. application No. 48775/72.

In a switching device of the kind to which the invention relates and comprising such selection means, if desired, the said programme selection means may be adapted to alter one or more of said combinations of one or more switching elements upon alteration of programme selection. In addition, or as an alternative thereto, a manually operable switching element combination alteration means may be incorporated in the device whereby alteration to one or more of said combinations of one or more switching elements may be accomplished independently of the programme selection means.

The programme selection means of a device of the kind to which the invention relates may be relatively simple or may be complex depending upon the application for which the switching device is intended. It will be appreciated that the recurrence period of the timing pulses recurring at relatively short intervals is chosen to be only a few milliseconds for most applications and since each timing pulse produced advances the state of the shift register, the provision of selection information by the programme selection means such that during the course of a selected programme a timing pulse occurs at a relatively short interval after a preceding timing pulse results in a corresponding state of the shift register being occupied for a few milliseconds only also or, in other words, the shift register is rapidly advanced. Under such conditions, actuation information supplied to the appropriate control points and the resultant actuation of switching elements related to the state of the shift register in question is of such short duration that for many applications of the device it may, for practical purposes be regarded as an omission of one of the combinations of switching functions from the series since the duration of the combination concerned is compressed. For other applications, means may be provided for inhibiting the actuation of the switching elements for the total duration of a succession of timing pulses recurring at relatively short intervals whereby one or more combinations of switching functions may be omitted from the series by the supply to the shift register of timing pulses recurring at relatively short intervals.

As an alternative to providing such means for inhibiting the actuation of the switching elements for the total duration of a succession of timing pulses recurring at relatively short intervals, suppression means may be provided, the suppression means being responsive to the said programme selection information and/or to information representing the existence of a physical condition and/or to the actuation information present at the said control point and being arranged to either prevent actuation of one or more of the switching elements of a combination of a series related to the programme in question or to permit such actuation and counteract the effect of such actuation.

It is advantageous in some applications for the said programme selection means to comprise a plurality of programme selection switching members each associated with a particular programme, each member being adapted to occupy either a selected state or a non-selected state and each so related to the other members that only one of the plurality may occupy the selected state at a given time, the plurality of switching members collectively providing the said selection information and, when all members of the plurality occupy the non-selected state, the selection information so provided in combination with the said actuation information supplied to the control points determining the performance of a basic series of combinations of said switching functions, whereas when one of the members of the plurality occupies the selected state the selection information so provided in combination with the said actuation information supplied to the control points determines the performance of the basic series of combinations of said switching functions modified by the omission of one or more of the combinations from the basic series and/or by the compression of the duration of one or more of the combinations of the basic series and/or by the substitution of one or more of the combinations in the basic series by a different combination. However, for other applications of the invention it is advantageous for the said programme selection means to comprise a plurality of switching members each associated with a portion of a basic series of combinations of switching functions, each adapted to occupy either a selected state or a non-selected state, the plurality of switching members collectively providing the said selection information and, when all members of the plurality occupy the selected state, the selection information so provided in combination with the said actuation information supplied to the control points determining the performance of a basic series of switching functions whereas when one of the members of the plurality occupies the non-selected state the said selection information so provided in combination with the said actuation information supplied to the control points determines the performance of the basic series of combinations of switching functions modified by the omission from the basic series of that portion associated with the member occupying the non-selected state or by the compression of the duration of that portion of the basic series associated with the member occupying the non-selected state.

In a switching device where means for inhibiting the actuation of the switching elements is provided, preferably the said timing pulses recurring at relatively short intervals are caused to recur periodically and for every timing pulse supplied to the shift register, the actuation of the switching elements is inhibited for a period of time commencing at or prior to the commencement of the timing pulse and terminating at or after elapsement of a period equal to the recurrence period of the timing pulses recurring at relatively short intervals, Still preferably, every timing pulse applied to the shift register is derived from a reference pulse generator producing reference pulses of fixed duration, the leading edges of the reference pulses being employed to determine the commencement of the period of inhibition of the actuation of the switching element and the trailing edges of the reference pulses being employed to determine the instant of triggering the shift register. With such an arrangement, the reference pulse generator may be arranged to be triggered either from a source of trigger pulses recurring at relatively long intervals or from a source of periodically recurring trigger pulses recurring at relatively short intervals.

The present invention provides a useful improvement to switching devices of the kind to which the invention relates.

In accordance with the invention, a multi-stable override circuit is associated with the said pulse supply means, the multi-stable programme override circuit having two stable output states, one output state providing for continuous supply to the shift register of timing pulses recurring at relatively short intervals, the other output state providing for supply to the shift register of timing pulses recurring at either relatively long intervals or at relatively short intervals in accordance with the programme, transition of the output state of the override circuit being controlled by information derived from one or more predetermined control points of the plurality.

Different forms of the invention are possible. In one form of the invention, the switching device is such that the said pulse supply means include a first pulse source for producing pulses recurring at relatively long intervals, a second pulse source for producing pulses recurring at relatively short intervals and a selection circuit arrangement permitting timing pulses for supply to the said shift register to be derived from either the first pulse source or the second pulse source, output information from the said override circuit being so applied to the selection circuit arrangement that when the output of the said override circuit is in the said one output state the selection circuit arrangement permits timing pulses to be derived only from the said second pulse source, whereas when the output of the said override circuit is in the said other state, the selection circuit arrangement permits timing pulses to be derived from either the first or second pulse source in accordance with the said programme information.

In another form of the invention, the switching device is such that the said pulse supply means includes a pulse source from whence timing pulses may be derived for supply to the shift register, the pulse source being adapted to operate in either a first mode of operation or a second mode of operation, the pulse source producing pulses recurring at relatively long intervals when operating in the first mode and producing pulses recurring at relatively short intervals when operating in the second mode, output information from the said override circuit being so applied to control the pulse source that when the output of the said override circuits is in the said one output state the pulse source operates only in the second mode, whereas when the output of the said override circuit is in the said other state, the pulse source operates in either the first or second mode in accordance with the said programme information. In this form, the said pulse source may be in the form of a relaxation oscillator, the repetition frequency of which is determined by the series combination of two capacitors one of which is shunted by the collector-emitter path of a transistor adapted to be rendered either conductive so that the pulse source operates in the said first mode or non-conductive so that the pulse source operates in the said second mode, pulse source contol means being provided for rendering the transistor conductive when the output of the said override circuit is in the said one output state or conductive in response to the said programme information when the output of the said override circuit is in the said other output state.

Preferably, a switching device in accordance with the invention is provided with switching means for switching the said override circuit into or out of a non-override condition in which the output of the override circuit is in the said other output state and transition of the output state is inhibited.

When provided with such switching means, with the override circuit in the non-override condition, the programme of switching operations determined by the said programme information is followed. However, with the override circuit not in the non-override condition, with transition of the output state controlled by information derived from predetermined control points of the plurality, rapid advancement of the shift register through one or more selected portions of the programme may be achieved. For this purpose, the override circuit may be in the form of a relatively simple bistable circuit.

The invention also offers the possibility, when the switching device is provided with such switching means and with the override circuit further modified in a manner to be described latter that with the override circuit not in the non-override condition, with transition of the output state controlled by information derived from predetermined control points of the plurality, of the switching device performing a series of combinations of switching functions in accordance with a first portion of the programme, whereupon the shift register is rapidly advanced, whole or part of the performed programme is repeated and the remaining portion of the programme is then performed.

If desired, the switching operations of the device may be inhibited in known manner during such rapid advancement, for example in accordance with the invention described in Australian Pat. application No. 48775/72.

Preferably also, a switching device in accordance with the invention includes programme selection means for providing selection information and comparison means for comparing selection information thus provided with actuation information present at the said respective control points of the plurality to thereby produce the said programme information.

This invention will now be described with reference to the accompanying drawings in which:

FIG. 1 is a schematic diagram of a known switching device of the kind to which the invention relates.

FIG. 2 illustrates wave forms to assist in describing the operation of a part of the circuit illustrated in FIG. 1.

FIG. 3 illustrates wave forms produced at various parts of the circuit of FIG. 1 in the course of operation of a particular programme.

FIG. 4 is a schematic diagram of a switching device embodying the present invention.

FIG. 5 is a schematic diagram of the multistable programme override circuit of another switching device embodying the present invention.

FIG. 6 is a schematic diagram of another known switching device of the kind to which the invention relates.

FIG. 7 is a chart to assist in describing the operation of FIG. 6.

FIG. 8 is another chart to assist in describing the operation of the circuit of FIG. 6.

FIG. 9 is a schematic diagram of a further embodiment of the invention.

FIGS. 1, 2 and 3 of the accompanying drawings are identical with FIGS. 1, 2 and 3 respectively of the complete specification of the applicant's co-pending Australian Patent Application No. 48775/72 and FIGS. 6, 7 and 8 of the accompanying drawings are identical with FIGS. 4, 5 and 6 respectively of that complete specification.

In FIG. 1, the control points 1, 2, 3, 4, 5, 6, 7 and 8 are each connected to the output of a stage of the shift register 9 having stages 9a, 9b, 9c etc., control point 1 being connected to the output of stage 9a, control point 2 being connected to the output stage 9b etc. The shift register 9 is driven by timing pulses supplied via the terminal 10. The shift register 9 is of known kind and operates in a known manner. In an initial state, the control point 1 is in the "high" state with the remaining control points all at the "low" state. The terms "high" and "low" indicate, in the present instance, a predetermined positive voltage level and a zero voltage level respectively.

At the occurrence of the first timing pulse supplied via the terminal 10, the shift register 9 is advanced so that the control point 2 goes to the "high" state, the control point 1 goes to the "low" state and terminals 3 to 8 remain in the "low" state. This condition remains until the occurrence of the next timing pulse whereupon the control point 3 goes to the "high" state and control point 2 returns to the "low" state, control point 1 and control points 4 to 8 remain in the "low" state. The process is continued with the "high" state being transferred sequentially along the plurality of control points 1 to 8 at the occurrence of successive timing pulses. When the control point 8 is at the "high" state, the next succeeding timing pulse results in the shift register 9 being returned to its initial state.

The control points 1 to 8 are connected via the matrix 11 to the switching elements 12, 13, 14 and 15. The switching elements 12, 13, 14 and 15 are each in the form of a transistor provided with a load in its collector circuit. The load may be in the form of a relay, a lamp, a resistance etc. The connections from the control points 2 to 8 to the switching elements 12, 13, 14 and 15 are such that each of the control points 2 to 8 is associated with a combination of one or more of the switching elements 12 to 15, each control point being connected via the matrix 11 to the base electrodes of the transistors of the switching elements associated therewith.

Accordingly, if a particular control point is in the "high" state then the base electrodes of the transistors of the switching elements with which that particular control point is associated will also be in the "high" state and if the particular terminal is in the "low" state, then the base electrodes of the transistors of the switching elements with which that terminal is associated will also be in the "low" state. The transistors of the switching elements are arranged so that each transistor is cut off when its base electrode is at the "low" state and is conducting when its base electrode is at the "high" state. Thus, the switching elements 12 to 15 may be regarded as being actuated when the base electrode of their respective transistors is in the "high" state and the information provided by the control points 2 to 8 being in either the "high" or the "low" state may be regarded as actuating information.

The emitter electrodes of the transistors of the respective switching elements 12 to 15 are connected to earth via the collector emitter path of a single transistor TR4 to the base electrode of which is supplied a control potential in a manner to be discussed later. The foregoing description of the operation of the switching elements 12 to 15 assumes that the control potential at the base of the transistor 16 is such that the transistor 16 in the "on" state.

Two programme selection switches S1 and S2 are provided. One side of each of the switches S1 and S2 is connected to the positive supply line 17. The other side of the switch S1 is connected to an input of the "and" gate G1, whereas the other side of the switch S2 is connected to an input of the "and" gate G2. Control points 2, 3, 7 and 8 are connected to the other input of the "and" gate G1 whereas control points 3 and 8 are connected to the other input of the "and" gate G2. The output of the "and" gates G1 and G2 are connected to separate inputs of the "or" gate G3. The output of the "or" gate G3 is fed via the terminal 18 to both the gating network 19 and to the timing generator 20. The timing generator 20 consists of a simple relaxation oscillator denoted generally by the numeral 28 and comprising the silicon controlled switch SCS1, the resistances 21, 22, 23, 24 and the capacitance 25. The values of the resistances 21, 22 and 23 and that of the capacitance 25 are so chosen that the period of the oscillator 28 is approximately 2 minutes, i.e., at 2 minute intervals after initiation of the oscillator 28, a pulse of short duration is produced at the cathode of the switch SCS1. The capacitance 25 is bridged by the collector/emitter path of the transistor 26 which is provided for disabling or resetting the oscillator 28. If the base electrode of the transistor 26 is high, the collector/emitter path of the transistor 26 conducts and short circuits the capacitance 25. Accordingly, a positive pulse applied via the terminal 27 resets the oscillator 28 by discharging the capacitance 25. Alternatively, if the control point 1 is high or the terminal 18 is low, the oscillator 28 is disabled since capacitance 25 is short circuited.

The output of the oscillator 28 is fed to an input of the "and" gate G4, the other input of which is connected to the terminal 18. Accordingly, if the terminal 18 is high then the oscillator 28 functions and the oscillator output is applied via the gate G4 and the "or" gate G5 to the reference pulse oscillator 29 for triggering purposes.

The shaping network 30 is connected to a source of alternating voltage (not shown) having a frequency of 50 cycles per second to convert the alternating voltage into a square wave pulse train, having the same frequency. The output of the network 30 is continuously supplied to one of the inputs of the "and" gate G6. The other input of the "and" gate G6 is connected to the output of the "nor" gate G7 which has two inputs. One of the inputs of the gate G7 is connected to the terminal 18 and the other input of the gate G7 is connected to the control point 1. The control point 1 may be connected to earth by operation of the starting switch S3. If both of the inputs of the "nor" gate G7 are in the "low" state then the output of the gate G7 is "high" and the square wave output of the network 30 will be produced at the output of the "and" gate G6 and will be fed to the input of the reference pulse generator 29 via the "or" gate G5. However, if either or both of the inputs of the "nor" gate G7 are in the "high" state then the output of the gate G7 will be "low" and the gate G6 will remain closed thus disconnecting the output of the shaping network 30 from the generator 29.

The reference pulse generator 29 comprises a monostable multivibrator constituted by the transistors TR1 and TR2 which delivers a positive going fixed width output pulse at the collector electrode of the transistor TR2 each time the generator is triggered. In known manner, the width of the output pulse is determined by the value of the resistance 31 and that of the capacitance 32. The generator is triggered whenever a triggering pulse appears at the output of the gate G5, such a triggering pulse being conveyed to the base electrode of the transistor TR1 via the differentiating network constituted by the capacitance 33 and the resistance 34. The pulse 40 of FIG. 2a depicts a typical positive going reference pulse produced at the collector electrode of the transistor TR2. The pulse 40 has a duration of 5 milliseconds. Output pulses from the collector of the transistor TR2 are supplied to the terminal 27, to the inhibiting circuit 35 and to the base of the transistor TR3. The transistor TR3 functions as an inverter and for each reference pulse 40 applied to its base electrode, a negative going pulse 41, of FIG. 2b, also having a duration of 5 milliseconds is produced at the collector electrode of the transistor TR3.

The trailing edge 42 of each negative going pulse 41 is employed to advance the state of the shift register 9. As mentioned, the output pulse produced at the collector electrode of the transistor TR2 is also applied to the inhibiting circuit 35. The inhibiting circuit 35 comprises a re-triggable monostable multivibrator including the transistors TR5 and TR6. The operation of such a monostable multivibrator is well known and briefly is as follows. The capacitance 36 is connected to be charged from the positive supply line 37 via the resistance 38 so that when the apparatus is switched on, the capacitance 36 becomes charged after approximately 30 milliseconds with the transistor TR6 conducting and the transistor TR5 cut off. The capacitance 36 is charged to a predetermined voltage determined by the value of the resistance 39 and the voltage drop across the base emitter path of the transistor TR6. At the occurrence of a positive going input pulse at the base of the transistor TR5, the transistor TR5 will conduct thereby rapidly discharging the capacitance 36 and cutting off the transistor TR6. At cessation of the input pulse, the capacitance 36 commences to charge again. Whilst the transistor TR6 is conducting, a positive voltage is supplied to the base electrode of the transistor TR4 from the base resistance of the transistor TR6 causing the former to conduct but when the transistor TR6 is cut off, owing to the discharge of the capacitance 36, the voltage across the emitter resistance 39 falls, causing the transistor TR4 also to be cut off. The values of the resistance 38 and that of the capacitance 36 are chosen so that for every input pulse applied to the transistor TR5, the transistor TR6 will remain cut off for 30 milliseconds following each input pulse whilst the capacitance 36 is recharged to the predetermined value. Accordingly, if a further input pulse is applied before termination of the 30 milliseconds cut off period (i.e., before the capacitance 36 has sufficiently recharged for the transistor TR6 to recommence conduction), the capacitance 36 is discharged once more and the charging process is repeated.

Accordingly, each time a positive going pulse 40 is produced at the collector electrode of the transistor TR2, the transistor TR4 is cut off and the switching elements 12, 13, 14 and 15 are inhibited for a period commencing with the occurrence of the leading edge of the pulse 40 which lasts for a period of at least 30 milliseconds after the termination of the pulse 40. The pulse 43 of FIG. 2c shows the negative going pulse produced at the base electrode of the transistor TR4 for every generated reference pulse 40. Whereas the duration of the pulse 40 is 5 milliseconds, the duration of the pulse 43 is 35 milliseconds. Both pulses commence at the same instant. Of course, the pulse 43 denotes the period of time for which the transistor TR4 is in the cut-off state.

The operation of the circuit of FIG. 1 can be explained in association with FIG. 3 as follows. With the power supplies to the circuit switched on and assuming the switch S1 is closed to select the desired programme, the shift register 9 is in its initial state with the control point 1 in the "high" state and the remainder of the control points 2 to 8 in the "low" state. The "high" state of the control point 1 ensures that the transistor 26 is conducting and the oscillator 28 is disabled.

Under these conditions, the switch S1, being closed, has no effect at the initial state of the register 9 although the positive potential of supply line 17 is connected to an input of the gate G1, the output of the gate G1 remains "low " because the other input of the gate G1 (derived from the respective control points) is in the "low" state. Thus, the output of the "or" gate G3 is "low" so that the input of the "nor" gate G7 connected to the gate G3 is "low" and the input of G7 connected to the control point 1 is "high." Accordingly, the output of the gate G7 is also "low" ensuring that the "and" gate G6 is closed and the output of the shaping network 30 cannot be supplied to the reference pulse generator 29. Since no triggering information is supplied to the reference pulse generator 29 from either the oscillator 28 or from the shaping network 30, no timing pulses are produced by the generator 29 and the shift register 9 remains in the initial state.

If now the start switch S2 is operated, the programme associated with the switch S1 is commenced and, in this regard, the wave forms of FIG. 3 illustrate the wave forms produced at the various parts of the circuit of FIG. 1 as follows:

FIG. 3a.sub.1 to 3a.sub.8 illustrate respectively the voltage wave forms present at the control points 1 to 8.

FIG. 3b illustrates the wave forms present at the base electrode of the transistor TR1.

FIG. 3c illustrates the wave forms present at the collector of the transistor TR2.

FIG. 3d illustrates the wave forms present at the collector of the transistor TR3.

FIG. 3e illustrates the wave forms present at the base of the transistor TR4.

FIG. 3f illustrates the wave forms present at the cathode of the silicon control rectifier SCS1.

FIG. 3g illustrates the wave forms present at the output of the gate G6.

With the operation of the start switch S3, the control point 1 is momentarily shorted to earth and the output of the "nor" gate G7 becomes "high," momentarily opening the gate G6 and allowing the single pulse 50 of FIG. 3g to be applied via the gate G6 and the gate G5 to the reference pulse generator 29 resulting in the differentiated pulse 51 of FIG. 3b being produced at the base of the transistor TR1. The fixed duration pulse 52 is thus generated at the collector electrode of the transistor TR2 so that the inhibiting circuit 35 is triggered and the switching elements 12 to 15 are inhibited from the instant coinciding with the leading edge of the pulse 52. The inhibition period is illustrated by the pulses 54 of FIG. 3e in which the time t1 is approximately 35 milliseconds. Although the pulse 52 is also applied to the terminal 27, it has no effect since the transistor 26 is already in the "on" state. The trailing edge of the negative going pulse 53 of FIG. 3d, generated simultaneously with the pulse 52, advances the shift register 9 to the second state. It will be appreciated that the trailing edge of the pulse 53 occurs 5 milliseconds later than the leading edge of the pulse 52 so that the switching elements 12 to 15 are in a state of inhibition during advancement of the state of the register 9.

Advancement of the shift register 9 to the second state results in the "high" state formerly present at the control point 1 to be transferred to the control point 2 and since the switch S1 is alreacy closed, both inputs of the gate G1 are now "high," the output of gates G1 and G3 also become "high" and the output of the gate G7 becomes "low " immediately closing the gate G6 again to prevent any further pulses from the network 30 from reaching the generator 29. Simultaneously, since the terminal 18 is now "high," the transistor 26 is cut off and the oscillator 28 commences a cycle of oscillation. Since also the control point 2 is now in the "high" state, the base electrodes of the transistors of the respective switching elements 12 to 15 associated with the control point 2 are also placed in the "high" state so that the switching elements concerned will be actuated when the inhibition period terminates and the transistor TR4 is switched on again.

As mentioned, the period of oscillation of the oscillator 28 is approximately 2 minutes. Accordingly, the shift register 9 remains in the second state for an equivalent period. At the end of the 2 minute period, the oscillator 28 produces a positive going output pulse 55 of short duration at the cathode of the silicon control switch SCS1. As the terminal 81 is "high," the gate G4 is open and the pulse 55 is conveyed via the gates G4 and G5 to the input of the reference pulse generator 29 whereupon another pulse 52 is generated again resulting in inhibition of the switching elements 12 to 15 and the triggering of the shift register 9 into the third state.

The process described in relation to the second state is thus repeated once more except that since the "high" state has been transferred to the control point 3, the switching elements associated with the control point 3 are actuated when the second period of inhibition is completed. At the completion of the third state of the shift register 9, another pulse 55 is produced by the oscillator 28, triggering the register 9 into its fourth state.

In the fourth state, the control point 4 becomes "high" and the gate G1 is closed so that the oscillator 28 is disabled and the gate G6 is opened so that the output of the network 30 is supplied to the generator 29.

The fourth state of the register 9 follows a similar pattern of operations to that of the first or initial state except that the gate G6 is not closed at the termination of the fourth state because, unlike the control point 2, the control point 5 is not connected to an input of the gate G1. Under these conditions, the oscillator 28 remains disabled and the gate G6 remains open whilst allowing further pulses recurring at relatively short intervals to be supplied from the network 30 to the generator 29 thereby advancing the state of the shift register rapidly to progress through the fifth state and the sixth state. In the seventh state, the control point 7 is, of course, "high" so that the gate G6 is closed and the oscillator 28 is enabled to commence a further cycle of oscillation. Thus, the seventh state and the eighth state of the register 9 follow a similar pattern of operations to the second and third states. At the conclusion of the eighth state, the register 9 is returned to its initial state completing the programme associated with the switch S1.

It will be appreciated that the reference pulses 52 associated with the commencement of the fourth, fifth and sixth states of the register each initiate a period of inhibition of the switching elements 12 to 15 which is of greater duration than the interval between those pulses so that the switching elements 12 to 15 remain inhibited for the total duration of the succession of the relevant reference pulses and the shift register 9 is therefore "rapidly advanced" through the fourth, fifth and sixth states without the switching elements associated with the control points 4, 5 and 6 being actuated for the selected programme under discussion (i.e., the programme associated with the switch S1). Of course, during the programme there is no rapid advance of the shift register 9 in the case of the second, third, seventh and eighth states of the register 9. Each of these states has a duration of 2 minutes during which the combinations of the switching elements 12 to 15 associated with the respective control points 2, 3, 7 and 9 are actuated.

Now, in the programme associated with the switch S2, the initial state of the register 9 would be similar to the initial state in the case of the programme associated with the switch S1. However, there would be a rapid advancement of the register through the second state, accompanied by inhibition of the switching elements 12 to 15, the third state would be for a duration of 2 minutes with the switching elements associated with the control point 3 actuated, there would be rapid advancement through the fourth, fifth, sixth and seventh states accompanied by inhibition of the switching elements 12 to 15 and the eighth state would be for a period of two minutes with the switching elements associated with the control point 8 actuated.

The switching device diagrammatically illustrated in FIG. 4 has many parts identical to those of the known switching device of FIG. 1 and such parts are denoted by a similar reference number in each case. The difference between the switching device of FIG. 4 and that of FIG. 1 is that the device of FIG. 4 incorporates a bistable control circuit 60, an "or" gate G8 and an inverter G9. The input terminals 61 and 62 of the bistable circuit 60 are connected respectively to the control terminals 2 and 7 and the reset terminal 63 is connected to the control terminal 1. The output terminal 64 of the bistable circuit 60 is connected to one of the inputs of the "or" gate G8, the other input being from the output of "nor" gate G7. As distinct from FIG. 1, in FIG. 4 the terminal 18 is connected to the timing generator 20 via the diode D2 for the purpose of disabling the latter and, in addition, in similar manner and for the same purpose, the output terminal 64 is also connected to the timing generator 20 via the diode D1, and inverter G9, the diodes D1 and D2 isolating the terminal 18 from the output of G9.

The bistable circuit 60 is in the form of a conventional flip-flop circuit which in a first stable state causes the terminal 64 to be "low" and in the second stable state causes the terminal 64 to be "high." In a known manner, application of a "high" voltage to the terminal 63 sets the bistable circuit 60 in the first state whereas application of a "high" voltage to the terminal 61 causes the state of the circuit 60 to be changed from the first state to the second state and application of a "high" voltage to the terminal 62 causes the state of the circuit 60 to be changed from the second state to the first. The bistable circuit 60 is only operative when the switch S4 is closed. When the circuit 60 is inoperative, the output terminal 64 is in the "low" state.

When the switch S4 is in the open position, since the bistable circuit is inoperative the operation of the circuit of FIG. 4 is substantially the same as the operation of the circuit of FIG. 1 as described in the specification of Australian Pat. application P.A. No. 7205/71. The output of the gate G8 is not affected by the bistable circuit 60 since the terminal 64 is "low" under such conditions. Accordingly, whenever the start switch S2 is closed, the programme of switching operations then followed by the circuit depends upon which of the switches S1 and S2 is closed.

On the other hand, with the switch S4 in the closed position so that the bistable circuit 60 is operative, the operation of the circuit of FIG. 4 is no longer substantially the same as that of FIG. 1. Upon closure of the start switch S3 under such conditions, the device follows a switching programme in which, regardless of which of the switches S1 or S2 is closed, there is rapid advance of the switching device through the states associated with the control points 2, 3, 4, 5 and 6.

Assuming for instance that the programme selection switch S1 is closed and that the switch S4 is open to make the bistable circuit 60 inoperative, upon closure of the start switch S3, the programme of switching operations followed by the device of FIG. 4 would be substantially the same as the programme of switching operations described in relation to FIG. 3 of the present specification. If, upon completion of the programme, the switch S4 is closed to make the bistable circuit 60 operative and the start switch S3 is closed once more, the same programme would be repeated except that there would be a rapid advance through the second, third, fourth, fifth and sixth states. In other words, there would be a repetition only of the combination of switching functions associated with the control points 7 and 8. In the programme followed, the second, third, fourth, fifth and sixth states would be "skipped."

As an example, if the combination of switching functions associated with the control points 7 and 8 coincided respectively with the rinse and the spindry functions in an automatic washing machine incorporating the device of the invention, then an operator would be able to readily repeat the rinse and the spindry functions only. Of course, connection of the terminals 61 and 62 is not restricted to the control points 2 and 7 respectively but may be to any of the control terminals appropriate for the register state of which skipping is desired. Whilst the device of FIG. 4 is a relatively simple one, the principles of the invention may be incorporated in a more complicated device of the same general kind, for instance in a device provided with a shift register having more than eight states and hence more than eight control points and associated combinations of switching functions.

The bistable device 60 may be replaced by the bistable control circuit of FIG. 5 constituted by the "and" gate G13 the inputs of which are interconnected, as illustrated, with the flip-flop circuits FF1 and FF2 and the "nand" gates G11 and G12. In FIG. 5, the terminals 61, 62 and 64 respectively correspond with the terminals 61, 62 and 64 of FIG. 4.

When the bistable device 60 is replaced by the control circuit of FIG. 5, the information at the control point 2 is applied via the terminal 61 to one of the inputs of the "nand" gate G12 and the other input of the "nand" gate G12 is connected to the output A of the flip-flop FF1. The output of the "nand" gate G12 is used for triggering the flip-flop FF2, the output B of which is connected to one input of the "and" gate G13, the other input of the "and" gate G13 being also connected to the output A of the flip-flop FF1.

The information of the control point 7 is applied via the terminal 62 to one input of the "nand" gate G11 and also is used to reset the flip-flop FF2. The other input of the "nand" gate G11 is connected to the "repeat cycle" switch S5 which, when closed, applies a positive voltage to that input. The output of the "nand" gate G11 acts as a trigger source for the flip-flop FF1.

Table 1 following, is a truth table showing the status of the relevant inputs and outputs of the gates G11, G12 and G13 and the flip-flops FF1 and FF2 corresponding with the eight states of the shift register 9 when the switch S5 is open.

TABLE 1 ______________________________________ State of Register 9 1 2 3 4 5 6 7 8 ______________________________________ G 11 INPUT (a) 0 0 0 0 0 0 1 0 G 11 input (b) 0 0 0 0 0 0 0 0 G 11 OUTPUT 1 1 1 1 1 1 1 1 FF1 OUTPUT A 0 0 0 0 0 0 0 0 G 12 INPUT (a) 0 0 0 0 0 0 0 0 G 12 INPUT (b) 0 1 0 0 0 0 0 0 G 12 OUTPUT 1 1 1 1 1 1 1 1 FF2 OUTPUT B 1 1 1 1 1 1 1 1 G 13 INPUT (a) 0 0 0 0 0 0 0 0 G 13 INPUT (b) 1 1 1 1 1 1 1 1 G 13 OUTPUT 0 0 0 0 0 0 0 0 ______________________________________

From Table 1 it will be appreciated that the input (a) for the gate G11 (derived from the control point 7) is in the "low" state for all states of the register 9 except the seventh state whereas the input (b) for the gate G12 (derived from the control point 2) is in the "low" state for all states of the register 9 except the second state. However, since the switch S5 is open, changeover of the flip-flop FF1 or FF2 cannot occur and the state of the output of the gate G13 remains in the "low"state during every state of the register 9. Accordingly, with the switch S5 open, the programme of switching operations followed by the device depends upon the setting of the appropriate programme selection switch S1 or S2 and is not influenced by the control circuit 7. Since the output of the gate G13 is in the "low" state at the end of the eighth state of the shift register 9, the shift register 9 is arrested in the initial state following the eighth state provided that the push button start switch S3 is open.

Table 2 following is a truth table showing the state of the relevant input and output of the gates G11, G12 and G13 and the flip-flops FF1 and FF2 corresponding with the indicated state of the shift register 9 when the switch S5 is closed.

TABLE 2 ______________________________________ State of Register 9 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 ______________________________________ G 11 INPUT (a) 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 G 11 INPUT (b) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 G 11 OUTPUT 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 FF1 OUTPUT A 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 G 12 INPUT (a) 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 G 12 INPUT (b) 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 G 12 OUTPUT 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 FF 12 OUTPUT B 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 G 13 INPUT (a) 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 G 13 INPUT (b) 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 G 13 OUTPUT 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 ______________________________________

From Table 2, as in the case of Table 1, it will be appreciated that the input (a) for the gate G11 (derived from the control point 7) is in the "low" state for all states of the register 9 except the seventh state whereas the input (b) for the gate G12 (derived from the control point 2), is in the "low" state for all states of the register 9 except the second state. However, as a result of the switch S5 being closed, the input (b) of the gate G11 is in the "high" state thereby resulting in changeover of the state of the flip-flop FF1 each time the seventh state of the register 9 is reached. Accordingly, the output A is initially in the "low" state, the state changing to "high" when the register 9 reaches the seventh state for the first time, remaining in the "high" state until the register 9 reaches the seventh state for the second time whereupon the state of the output A is returned to "low."

Since the output A is applied to the input (a) of the "nand" gate G12 and also to the input (a) of the gate G 13, changeover of the flip-flop FF2 and changeover of the state of the output of the gate G13 becomes possible during the period that the output A of the flip-flop FF1 is in the "high" state. As indicated by the table 2, such changeover occurs when the register 9 reaches the seventh state for the first time, because the flip-flop FF2 is reset by the signal present at the terminal 62 so that output B of the flip-flop FF2 is "high." Accordingly, the output of the gate G13 is in the "high" state during the time that the register 9 is in the seventh and eighth states for the first time. When the output of the gate G13 is in the "high" state, the output of the gate G8 will be "high" so that the square wave output of the network 50 will be produced at the output of the "and" gate G6 and will be fed to the input of the reference pulse generator 29 via the "or" gate G5 resulting in rapid advance of the shift register 9. Further, as the output of the gate G13 is still "high" at termination of the said eighth state of the register 9, the register 9 is not arrested during the following initial state of the register 9 but is rapidly advanced into the second state.

When the register 9 reaches the second state for the second time, the control point 2 becomes "high" causing the output of the gate G12 to become "low" and causing the state of the flip-flop FF1 to change so that the output B becomes "low " and the output of the gate G13 becomes "low" once more and remains "low" until the shift register 9 is ultimately arrested when the initial state is reached for the third time.

From the foregoing description of the operation of the control circuit of FIG. 5, it will be understood that the control circuit provides a means of automatically interrupting the course of a selected programme, repeating a portion of the programme preceding the interruption and then resuming and completing the selected programme. For example, in the case of the sequence of operations associated with Table 2, regardless of which programme has been selected, the selected programme would be followed through the first, second, third, fourth, fifth and sixth states of the shift register 9, the register would then be rapidly advanced through the seventh and eighth states and again through the first state for the second time whereupon the selected programme would be repeated through the second, third, fourth, fifth and sixth states and then the process would be completed by the performance of the seventh and eighth states in accordance with the selected programme, the device being arrested as the first, or initial state was reached for the third time.

As before, connection of the terminals 61 and 62 is not restricted respectively to the control points 2 and 7 but may be to any desired control points. Moreover, the control circuit of FIG. 5 may be employed associated with devices other than that described in relation to FIG. 4, for instance, in association with devices provided with a shift register having more than eight states and hence more than eight control points and associated combinations or switching functions.

Referring now to the switching device diagrammatically illustrated in FIG. 6:

The switching device of FIG. 6 is intended to be employed for controlling switching operations required in an automatic clothes washing machine of the kind in which a washing container and an impeller having a common axis of rotation and capable of being independently driven by an electric motor are located within a wash tub to which hot or cold water may be supplied or removed. As is well known, clothes may be washed and partly dried in such washing machines by suitably arranging the sequence and/or repetition of operation including water supply, impeller agitation, water removal, container spinning, etc.

In FIG. 6, the control points 101, 102, 103, 104, 105, 106, 107 and 108 are each connected to the output of a stage of the shift register 109 having stages 109A, 109B, 109C etc. The shift register 109 is driven by timing pulses supplied via the terminal 110. The shift register 109 is of known kind and operates in a known manner. When the start switch PSS is closed, the mains voltage is supplied to the power supply circuit X and accordingly appropriate DC voltages are applied from the power supply circuit X to the respective DC supply lines (not shown). In addition, mains voltage is supplied to the mains supply line Y. When the shift register is in an initial state, with the switch PSS closed, the control point 101 is in the "high" state with the remaining control points all at the "low" state.

At the occurrence of the first timing pulse supplied via the terminal 110, the shift register 109 is advanced so that the control point 102 goes to the "high" state, the control point 101 goes to the "low" state and terminals 103 to 108 remain in the "low" state. This condition remains until the occurrence of the next timing pulse whereupon the control point 103 goes to the "high" state and the control point 102 returns to the "low" state, the control point 101 and control points 104 to 108 remain in the "low" state. The process is continued with the "high" state being transferred sequentially along the plurality of control points 101 to 108 at the occurrence of successive timing pulses. When the control point 8 is at the "high" state, the next succeeding timing pulse results in the shift register 9 being returned to its initial state and simultaneously the start switch PSS is returned to the open condition owing to the energisation of the solenoid SOL by the operation of the reset circuit RC when the state at control point 8 changes from the "high" state to the "low" state.

The control points 101 to 108 are connected via the matrix 111 to one or more of the switching elements SE1, SE2, SE3 and SE4, SE5. The switching elements SE1, SE2, SE3 and SE4, SE5 are each in the form of a transistor provided with a load in its collector circuit. The load of the individual switching elements may be in the form of a relay, a lamp, a resistance, a solenoid, etc. However, in the present instance, the load of the switching element SE1 is in the form of solenoid for actuating a cold water supply valve for supplying cold water to the washtub of the machine, the load of the switching elements SE2 is a similar solenoid for actuating a hot water supply valve, the load of the switching element SE3 is the winding of a relay RL1, the load of the switching elements SE4 and SE5 are each in the form of a solenoid for respectively actuating a mechanism for causing the impeller of the machine to "agitate" or actuating a mechanism for causing the washing container to spin, provided that the motor M is running.

The connections from the control points 101 to 108 to the switching elements SE1 to SE5 are such that each of the control points is associated with a combination of one or more of the switching elements SE1 to SE5, each control point being connected directly or indirectly to the base electrodes of the transistors of the switching elements associated therewith.

Accordingly, if a particular control point is in the "high" state then depending upon programme selection, the control electrodes of the transistors of thr switching elements with which that particular control point is associated will also be in the "high" state and if the particular point is in the "low" state, then the electrodes of the transistors of the switching elements with which that control point is associated will also be in the "low" state. The transistors of the switching elements are arranged so that each transistor is cut off when its base electrode is at the "low" state and is conducting when its base electrode is at the "high" state. Thus, the switching elements SE1 to SE5 may be regarded as being actuated when their respective base electrodes are in the "high" state and the information provided by the control points 101-102 being in either the "high" or the "low" state may be regarded as actuating information.

A programme selection means PSM is provided which includes a switch assembly of the kind in which the two push-button operated switches, S101 and S102, are mechanically interlocked with each other so that only one switch of the assembly can remain in the closed condition at a given time. The switch assembly also incorporates a push-button, hereinafter referred to as the blank push-button, which is not capable of closing any of the switches but is coupled with the mechanical interlocking mechanism in such a manner that, if operated, either switch of the assembly occupying the closed condition is opened.

The programme selection means PSM also includes the auxiliary push-button operated switches S103, S104 and S105 which are mechanically independent of the pushbutton switch assembly of which the switches S101 and S102 form part. Switch S106 is a further auxiliary pushbutton button operated switch which may, or may not form part of the programme selection means PSM upon the requirements. One side of each of the switches S101 to S106 is connected to the positive supply line 117. The other side of the switch S101 is connected to an input of the "nand" gate G102, the other side of the switch S102 is connected to an input of the "nand" gate G104, the other side of the switch S103 is connected to an input of the "nand" gate G103, the other side of the switch S104 is connected to an input of the "or" gate G107 and also to an input of the "and" gate G108 via the inverter INV1, the other side of the switch S105 is connected to the other input of the "or" gate G107 whereas the other side of the `hold` switch S106 is connected via the inverter INV3 to an input of the "nand" gate G101, to an input of the "and" gate G112 and to an input of the "and" gate G115.

The pulse supply means PG comprises a relaxation oscillator 128 constituted by the silicon controlled switch SCS101, the resistors 121, 122, 123 and 124, and the capacitances 125 and 126. The oscillator 128 is capable of being operated in any one of two alternative modes, the particular mode of operation depending upon the state of conductivity of the transistor TR102. When the transistor TR102 is non-conductive, the period of oscillation is determined by the values of the resistances 121, 122 and 123, and by the resultant values of the series combination of the capacitances 125 and 126. The selection of the values of the respective components is such that in this mode of operation the period of oscillation of the oscillator 128 is approximately 5 milliseconds. Alternatively, when the transistor TR102 is in the conductive state, the period of oscillation of the oscillator 128 is determined by the value of the resistances 121, 122, and 123, and by the value of the capacitance 125. The respective components are selected so that in this mode of operation the period of oscillation is approximately 30 seconds. Thus, the ratio of the period of oscillation in one mode to the period of oscillation to the other mode is of the order of 1:6,000. In either mode of operation, a positive going output pulse of short duration is produced across the resistance 124 for every cycle of oscillation. The transistor TR102 is non-conductive when its base electrode is at more potential, or in other words when the base potential is "low." The transistor TR102 is rendered conductive by application to the electrode of a positive potential greater than approximately 0.6 volts, or in other words when the base potential is "high."

The series combination of the capacitances 125 and 126 is shunted by the collector-emitter path of the control transistor TR101. Application of a "high" voltage to the base of the transistor TR101 causes the transistor to conduct, short-circuiting the series combination of the capacitances 125 and 126 and thereby inhibiting operation of the oscillator 128 altogether. On the other hand, application of a "low" voltage to the base of the transistor TR101 ensures that the transistor is non-conductive and that the oscillator 128 operates in one mode of operation or the other depending upon the state of conductivity of the transistor TR102 and the presence of suitable operating potentials.

The output pulses of the pulse supply means PG are derived from across the resistance 124 and supplied to the divider DIV. The output pulses of which are fed to the terminal 110 and serve as timing pulses for triggering the shift register 109. The divider DIV is in the form of an eight-bit shift register which produces an output pulse for every eighth input pulse.

A comparison means C.M. includes the "nand" gates G102, G103 and G104 the outputs of which are connected to the timing line TL, the state of the timing line T.L. determines the mode of operation of the oscillator 128.

The operation of the switching device of FIG. 4 will now be described in conjunction with the chart of FIG. 7 which sets out in tabular form a basic programme and modifications of that basic programme for different settings of the programme selection means.

The basic programme is followed when the start button PSS is closed provided the `blank` push-button has previously been selected and none of the switches S103, S104, S105 and S106 are selected. The `blank` push-buttons may conveniently be marked `superwash` and the word `superwash` is employed in the chart of FIG. 7 to denote this basic programme. In the chart of FIG. 7 there are eight columns, numbered accordingly, which coincide with the eight states of the shift register 109. As indicated in each column, certain events are carried out during each state of the basic programme `superwash,` the activities in question are each indicated in the column concerned and for the basic programme `superwash` an asterisk appears in each column to show that every event is carried out in the course of the basic programme. For other programmes or modifications indicated in the chart of FIG. 7, asterisks are omitted in certain columns alongside the indicated programme or modification indicating that the particular event related to the column is omitted as the shift register 109 advances through the eight states.

In following the basic programme `superwash,` upon closure of the switch PSS under these conditions, the shift register 109 is in its initial state and accordingly the control points 101 is "high," the remaining control points 102-108 being "low."

Since neither of the switches S101 and S102 are closed, the timing line TL is in the "high" state ensuring that the transistor TR102 is conductive so that the oscillator 128 is set for that mode of operation for producing an output pulse every 30 seconds provided the transistor TR101 is simultaneously non-conductive. However, the state of conductivity of transistor TR101 depends, inter alia, upon the condition of the water level switch WLS. The water level switch WLS is associated with the wash tub of the machine and produces a "high" at one of the inputs of each of the "and" gates G105, G106 and G113 whenever the level of the water in the wash tub is below a predetermined `full` level and produces a "low" at those inputs of the gates G105, G106 and G113 whenever the water in the wash tub has reached the predetermined `full` level. If the water level in the machine wash tub is below the `full` level when the shift register is in the initial state, the "high" produced by the switch WLS results in a "high" being produced at the output of the "and" gate G114 provided the timing line TL is also "high" thereby preventing oscillation of the oscillator 128. Thus, the shift register must remain in the initial state so long as the water level of the machine is below the `full` level. During the initial state of the shift register 109 when performing the basic programme with the water level of the machine wash tub below the `full` level, since the control point 101 is in the "high" state the switching elements SE1 and SE4 are actuated but the switching elements SE2, SE3 and SE5 are not actuated. Switching element SE1 is actuated via the "and" gate G105 and the "or" gate G109 and since the switching element SE1 is actuated, the solenoid forming the load is energised thereby opening the `cold water` supply valve for supplying cold water to the machine wash tub. Accordingly, the wash tub commences to fill. Even through the switching element SE4 is actuated, the actuation has no effect since the motor M is not energised, the contacts of the relay RL1 being open because the switching element SE3 is not actuated.

Once the water level in the machine wash tub has reached the `full` level, changeover of the switch WLS results in a "low" being applied to an input of each of the "and" gates G105, G106 and G113. Accordingly, the "and" gate G106 is closed so that actuating information from the control point 101 is no longer applied to the switching element SE1 and the cold water supply valve is closed. The closure of the gate G106 also results in the output of the "or" gate G111 going "low" so that via the inverter INV4, the "nand" gate G101 and the "and" gate 104, the transistor TR101 is rendered non-conductive and via the inverter INV5 and the "and" gate G112, the switching element SE3 is actuated so that the contacts of the relay RL1 are closed and the motor M is energised. As the switching element SE4 is already actuated, the impeller of the washing machine commences to agitate. Transistor TR101 being rendered conductive, permits the oscillator 128 to commence oscillation and produce an output pulse every 30 seconds and since the output of the oscillator 128 is connected to the shift register 109 via the divider DIV, a timing pulse is supplied to the shift register 109 four minutes after the oscillator 128 has commenced to oscillate thereby triggering the shift register 109 into the second state whereupon the control point 101 goes "low" and the control point 102 goes "high."

In theory, similar switching operations are carried out for the second state of the shift register 109 as in the initial state whilst performing the basic programme under discussion. However, in practice, as the water level in the machine wash tub has already reached the predetermined `full` level required for changeover of the switch WLS, the state of affairs existing during the latter portion of the initial state are continued, i.e. the output of the "or" gate G111 is "low" so that the switching elements SE3 and SE4 are still actuated. Accordingly, throughout the second state, the impeller continues to agitate whereas the transistor TR101 remains non-conductive so that the oscillator 128 continues to oscillate and the divider DIV produces another timing pulse four minutes after the commencement of the second state which triggers the shift register 109 into the third state whereupon the control point 102 goes "low" and the control point 103 goes "high."

Again, in theory, similar switching operations are carried out for the third state of the shift register 109 as in the initial state during performance of the basic programme under discussion. Again however, in practice, as the water level in the machine wash tub has already reached the predetermined level required for changeover of the switch WLS, the state of affairs existing during the latter portion of the initial state, and existing throughout the second state are continued, i.e., the output of the "or" gate G111 is low so that the switching elements SE3 and SE4 are still actuated. Accordingly, during the third state the impeller continues to agitate whereas the oscillator 128 continues to oscillate and the divider DIV produces another timing pulse four minutes after the commencement of the third state which triggers the shift register 109 into the fourth state whereupon the control point 103 goes "low" and the control point 104 goes "high."

Before commencing a description of the operations associated with the fourth state of the shift register 109 during performance of the basic programme, it should be mentioned that the motor M is arranged to drive a water pump whenever the motor is running. Moreover, the mechanism for either causing the impeller of the machine to agitate or causing the washing container to "spin" provided that the motor is running is so arranged that when neither the switching elements SE4 and SE5 are actuated, the water pump is connected to pump water out of the machine wash tub.

As there are no connections between the control point 104 and the matrix 111 then the change of state of the shift register 109 from the third state to the fourth state results in the switching element SE4 being no longer actuated. However, the timing line TL remains in the "high" state and the output of the "or" gate G111 is still "low" so that other conditions of the third state continue in the fourth state in that the switching element SE3 remains actuated so that the motor M continues to be energised and in that the transistor TR101 remains non-conductive and the transistor TR102 remains conductive. Thus, the oscillator 128 continues to oscillate in the mode producing an output pulse every 30 seconds so that 4 minutes after the commencement of the fourth state the divider DIV produces a further timing pulse which triggers the shift register 109 into the fifth state whereupon the control point 104 goes "low" and the control point 105 goes "high." Of course, during the fourth state, since neither of the switching elements SE4 and SE5 are actuated, the water pump driven by the motor M is connected to pump water out of the machine wash tub whilst the impeller of the machine remains stationary. Owing to the removal of water from the machine wash tub, the switch WLS returns to the condition under which it produces a "high" inter alia at one of the inputs of the gate G113.

In the fifth state, a "high" being produced at the control point 105 supplies a "high" to the base of the transistor incorporated in the switching element SE5 via the "and" gate G113 which is open and the switching element SE5 is therefore actuated. Since the timing line TL is still "high" and since the output of the "or" gate G111 is low, the oscillator 128 continues to oscillate in the mode producing output pulses every 30 seconds and the switching element SE3 remains actuated so that the motor M continues to be energised. Actuation of the switching element SE5 thus results in the impeller of the washing machine being caused to spin but the water is no longer pumped from the wash tub. Again, four minutes after the commencement of the fifth state, the divider DIV produces a timing pulse triggering the shift register into its sixth state whereupon the control point 105 goes "low" and the control point 106 goes "high."

The operation of the device for the sixth state is similar to that of the first state during performance of the basic programme although the information from the control point 106 reaches the related switching elements via a different series of gates. Again, since the switch WLS supplies a "high," the switching element SE1 is actuated so that water is supplied to the machine wash tub until the predetermined `full` level is reached whilst simultaneously the transistor TR101 is rendered conductive thereby rendering the oscillator 128 inoperative. Again, when the water level in the machine wash tub has reached the `full` level, the switch WLS delivers a "low" so that the switching element SE1 ceases to be actuated and a "low" is produced at the output of the "or" gate G111 so that the switching element SE3 is actuated and the motor M is energised whereupon the switching element SE4 being actuated from the control point 106 causes the impeller of the machine to agitate. In addition, when the output of the "or" gate G111 goes "low" the transistor TR101 is rendered non-conductive and the oscillator 128 commences to oscillate. Four minutes after the commencement of oscillation, the divider DIV produces a further timing pulse triggering the shift register 109 into the seventh state whereupon the control point 106 becomes "low" and the control point 107 becomes "high."

The operation of the device for the seventh state is similar to that of the fourth state during performance of the basic programme, the switching element SE3 being actuated whilst the switching elements SE4 and SE5 are not actuated so that the water pump driven by the motor M removes water from the machine wash tub once more whilst the transistor TR101 remains non-conductive so that the oscillator continues to oscillate and four minutes after the commencement of the seventh state the divider DIV supplies a further timing pulse triggering the shift register into the eighth state whereupon the control point 107 goes "low" and the control point 108 goes "high."

The operation of the device during the eight state is similar to that of the fourth state during performance of the basic programme, the switching elements SE3 and SE5 being actuated so that the washing container is caused to spin whilst the transistor TR101 remains nonconductive so that the oscillator 128 continues to oscillate in the mode producing output pulses each 30 seconds and 4 minutes after the commencement of the eighth state, the divider DIV supplies a further timing pulse triggering the shift register 109 into the initial state once more whereupon the control point 108 goes "low" and the control point 101 goes "high". However, upon transition of the control point 108 from the "high" state to the "low" state, the differentiating network constituted by the resistance 127 and the capacitance 130 in the reset circuit RC causes the normally conducting transistor TR103 to be momentarily cut-off and the momentary increase of the collector voltage of the transistor TR103 causes the transistor TR104 to conduct heavily for a short period energising the solenoid SOL and releasing the switch PSS from the closed condition thus removing the mains power supply voltage from the mains line Y and from the power supply X.

Instead of selecting the basic programme "Superwash," a secondary programme may be selected such as `Normal wash` or `Spin Dry.` If either of these secondary programmes are selected, then upon closure of the start switch PSS, the basic programme is followed except that the basic programme is modified by the shift register 109 being rapidly advanced through certain states during the performance of the programme and the switching elements of the respective combinations associated with the states through which the shift register is rapidly advanced are still actuated. For some of the combinations of switching elements through which the shift register 109 is rapidly advanced, one or more of the switching elements are rendered ineffectively by the state of the relay RL1, the contacts of which thus set as a cancelling switch, producing cancellation of the function that would otherwise occur. Those switching elements not so rendered ineffective control functions, the occurrence of which is of such short duration that they may be disregarded for practical purposes.

From the chart of FIG. 7, it can be seen that in performance of the secondary programme `Normal Wash,` the basic programme is followed except that the shift register 109 is rapidly advanced through the second state. The result of selecting `Normal Wash` instead of `Super Wash` is that after the filling of the machine wash tub to the predetermined level, agitation of the impeller is for a total period of only 8 minutes instead of for a total period of 12 minutes.

Rapid advancement of the shift register 109 through the second state during performance of the secondary programme `Normal Wash` occurs as follows:

Upon closure of the switch PSS, after previously selecting the `Normal Wash` push-button S102, without any of the switches S103 to S106 being selected, power supplies are supplied to the device as previously described, the shift register 109 being in the initial state with the control point 101 being "high." As mentioned, the initial state of the register 109 during performance of the secondary programme `Normal Wash` coincides with the initial state of the register in the basic programme `Super Wash` and at the end of the initial state, the control point 101 goes "low" and control point 102 goes "high" as the second state commences. The "high" present at the control point 102 is applied to one input of the "nand" gate G104, the other input of which is also "high" since the switch S102 is closed. Accordingly, the output of the "nand" gate G104 is "low" making the timing line TL also "low" thereby rendering the transistor TR102 non-conductive and ensuring that the transistor TR101 is also non-conductive. Thus, the oscillator 128 commences to oscillate in the mode in which an output pulse is produced every 5 milliseconds so that 40 milliseconds after the commencement of oscillation, the divider DIV produces a timing pulse which advances the shift register into the third state whereupon the control point 102 goes "low" and the control point 103 goes "high." During the second state, since the timing line TL is in the "low" state, the output of the "and" gate G112 is also "low" and the switching element SE3 is not actuated and hence the contacts of the relay RL1 are open. Of course, since the contacts of the relay RL1 are open, the motor M is not energised and although the switching element SE4 is actuated, such actuation is rendered ineffective owing to the cancelling effect produced by non-actuation of the switching element SE3. In addition, the switching element SE1 is actuated but since actuation is for such a short period (40 milliseconds) its actuation may be ignored for practical purposes.

The third, fourth, fifth, sixth, seventh and eighth states of the register 109 in the performance of the secondary programme `Normal Wash` coincide with the third, fourth, fifth, sixth, seventh and eighth states respectively of the performance of the basic programme `Super Wash.`

From the chart of FIG. 7, it can be seen that in performance of the secondary programme `Spin Dry,` the basic programme is followed except that the shift register 109 is rapidly advanced through the first six states. The result of selecting `Spin Dry` instead of `Super Wash` is that the function of filling and agitating associated with the first, second and third states, the pumping associated with the fourth state, the spinning associated with the fifth state and the filling and agitating associated with the sixth state do not occur. The function of pumping associated with the seventh state and that of spinning associated with the eighth state are however carried out.

The selection of the secondary programme `Spin Dry` is accomplished by selection of the switch S101, without selection of any of the switches S103 to S106 and in the performance of this secondary programme it will be appreciated that during the initial, second, third, fourth, fifth and sixth states of the shift register, the timing line TL is "low" since S104 is closed and that a "high" is present at both inputs of the "nand" gate G102. As the timing line TL goes "low," the oscillator 128 is operative and oscillates in that mode producing output pulses each 5 milliseconds so that the shift register is advanced by timing pulses supplied each 40 milliseconds to the terminal 110. Simultaneously, as the timing line TL is "low" the output of the "and" gate G112 is also "low" and the switching element SE3 is not actuated and the motor M is not energised. Thus, the agitating function associated with the initial, second, third and sixth states, the pumping function associated with the fourth state and the spinning function associated with the fifth state do not occur even though the switching element SE4 is actuated in the initial, second, third and sixth states and the switching element SE5 is actuated in the fifth state. Although actuation of the switching element SE1 occurs during the initial, second, third and sixth states, the energisation of the solenoid controlling the cold water supply valve is of such short duration that it can be neglected for practical purposes. Upon termination of the sixth state, the control point 106 goes "low" and the control point 107 goes "high." Thus, the seventh state commences and coincides with the seventh state of the basic programme. Similarly, the eighth state of the register, identical with the eighth state of the basic programme is carried out and the register is ultimately triggered into the initial state once more, whereupon the shift register is arrested by the release of the switch PSS upon transition from the eighth to the initial state.

Regardless of whether a basic programme or a secondary programme is selected, the programme in question may be modified, as desired, by the additional selection of one or more of the auxiliary push-button operated switches S103 to S106. The effect of selecting any of the switches S103 to S105 is to alter the combination of switching elements associated with one or more states of the shift register 109 during performance of the selected basic or secondary programme. The chart illustrated in FIG. 6, of the accompanying drawings illustrates the modifications to the basic programme `Super Wash` produced by selection of one or more of the switches S103 to S105.

The programme illustrated in relation to `Super Wash` in FIG. 8, of course, coincides with that illustrated in FIG. 7 since the conditions are those in which none of the auxiliary switches S103 to S105 are selected. The programme illustrated in relation to `Super Wash` + `Hot Wash` is produced by the combined selection of the `Super Wash` push-button and the `Hot Wash` push-button (S104). In this event, the modified basic programme followed is identical with that for the basic programme `Super Wash` except that in the initial, second and third states, the switching element SE1 is actuated in the basic programme `Super Wash` whereas the switching element SE2 is actuated in lieu thereof in the modified basic programme. This change of combination of switching elements is brought about for the states in question by the "and" gate G108 being disabled and by the "and" gate G110 being enabled by the "high" produced by the switch S104 respectively supplied via the inverter INV1 to an input of the gate G108 and via the "or" gate G107 to an input of the gate G110. It will be appreciated that actuation of the switching element SE2 in lieu of the switching element SE1 results in energisation of the solenoid for opening the hot water supply valve instead of energisation of the solenoid for opening the cold water supply valve. Similarly, the programme illustrated in relation to `Super Wash + Warm Wash` is produced by the simultaneous selection of the `Super Wash` push-button and the `Warm Wash` push-button (S105). In this event, the modified basic programme followed is identical with that for the basic programme `Super Wash` except that in the initial, second and third states of the basic programme, the switching element SE1 alone is actuated for water filling whereas in the modified basic programme the switching element SE2 as well as the switching element SE1 is actuated. This change of combination of switching elements is brought about for the states in question since "and" gate G110 is enabled by application of a "high" from the switch S105 via the "or" gate G107.

The programme illustrated in relation to `Super Wash + Drip Dry` is produced by the simultaneous selection of the `Super Wash` push-button and the `Drip Dry` pushbutton (S103). In this event, the modified basic programme followed is identical with that for the basic programme `Super Wash` except that the `spin` function associated with the eighth state os imitted, the shift register 109 being rapidly advanced through the eighth state since the "high" produced at the control point 108 during the eighth state, in combination with the "high" produced by the switch S103 results in a "low" at the output of the "nand" gate G103 during the state in question thereby making the time line TL "low."

The consequences will be evident to persons skilled in the art if there is a simultaneous selection of `Super Wash` and two of the auxiliary switches S103 to S105, for example, `Super Wash + Hot Wash + Drip Dry.`

The `hold` switch S106 may be selected, if desired, at any part of a basic or secondary programme, mofidifed or otherwise. The selection of the `hold` switch S106 results in a "low" being produced at the output of the inverter INV, which disables the "nand" gate G101 thus inhibiting the oscillator 128 altogether, disables the "and" gate G112 so that the switching element SE3 cannot remain in the actuated condition and thus the motor M cannot remain energised, and disables the "and" gate G115 thereby inhibiting any actuation of either of the switching elements SE1 and SE2.

Thus, selection of the `hold` switch S106 arrests the performance of any function regardless of which state of the register is occupied at the time of selection. Return of the switch S106 to the "open" state resotres the switching device to the condition existing at the time of selection thereby permitting the remainder of the programme to be completed.

The switching device diagrammatically illustrated in FIG. 9 has many parts identical to those of the known switching device of FIG. 6 and such parts are denoted by a similar reference numeral or letter in each case. The difference between the switching device of FIG. 9 and that of FIG. 6 is that the switching device of FIG. 9 incorporates a programme override circuit POC having separate trigger input terminals 212 and 213, a control input terminal 214, an output terminal 210 and an auxiliary output terminal 211. The output terminal 210 is connected to the timing line TL, the input terminal 212 is connected to the control point 108, the input terminal 213, is connected to the control point 106 and the control input terminal 214 is connected to earth via a resistance 215 and to a source of positive potential (not shown) via the switch S200. In addition, the electrode of the capacitance 130 remote from the base of the transistor TR103 and the input of the "nand" gate G103 instead of being directly connected to the control point 108 as in FIG. 6 are instead connected to the output of the "and" gate G203, one input (b) of which is connected to the control point 108 and the other input (a) of which is connected to the output of the "nand" gate G202. One input (a) of the "nand" gate G202 is connected to the auxiliary output terminal 211 of the circuit POC whereas the other input (b) of the "nand" gate G202 is connected to the junction of the resistance 215 with the switch S200.

The programme override circuit POC is constituted by two identical JK master-slave flip-flops FF201 and FF202 and a "nand" gate G201. The flip-flops FF201 and FF202 are, in the present instance, in the form of a Dual JK Master-Slave Flip-Flop Philips type FJJ 121/7473, the operation of which is well known and which is provided in a single package. For convenience of reference, the same symbols are employed in FIG. 9 as those used in published data information on the Philips type FJJ 121/7473, i.e., the symbols T1, J1, K1, Q1 and Q2 respectively denote the trigger input, J input, K input, and the complementary output of the flip-flop FF201 whereas the symbols T2, J2, K2, Q3 and Q4 respectively denote the trigger input, J input, K input and complementary outputs of the flip-flop FF202. As is known, the operation of a flip-flop of a Philips type FJJ 121/7473 is as indicated by the function table set out below as Table 3.

TABLE 3 ______________________________________ t n t n + 1 J K Q1 (Q3) ______________________________________ L L Q n L H L H L H H H Q n ______________________________________ H = High State L = Low State

In Table 3, the column indicated as tn shows alternative states of the J and K inputs at a time tn i.e. at the occurrence of a trigger pulse applied to the trigger input whereas the column indicated as tn + 1 shows the resultant output produced at the Q1 (or Q3) output at the occurrence of the next succeeding trigger pulse. The symbol Qn indicates that the Q1 (or Q3) output produced is the same as the Q1 (or Q3) output existing at the time tn whereas the symbol Qn indicates that the Q1 (or Q3) output produced is the reciprocal of the Q1 (or Q3) output existing at the time tn. Of course, although not indicated in table 3, the Q2 (or Q4) outout is the reciprocal of the Q1 (or Q3) output at any given time.

The flip-flops FF201 and FF202 are interconnected with each other and with the "nand" gate G201 and connections to respective input and output terminals of the circuit POC exist. The trigger input terminals 212 and 213 are respectively connected to the trigger inputs T1 and T2. The control input terminal 214 is connected to the J1 input of the flip-flop FF201. The K1 and K2 inputs of the flip-flops FF201 and FF201 respectively are both connected to a positive potential. The Q1 output of the flip-flop FF201 is connected to the J2 input of the flip-flop FF202 and to an input (a) of the "nand" gate G201. The output Q2 of the flip-flop FF201 is connected to the auxiliary output terminal 211. The Q4 output of the flip-flop FF202 is connected to the other input (b) of the "nand" gate G201 and the output of the "nand" gate G201 is connected to the output terminal 210 of the circuit POC.

Table 4 following is a truth table showing the states of the relevant parts of the programme override circuit POC and at relevant inputs and outputs of the gate G202 and G203 corresponding with eight states of the shift register 109 when the switch S200 is open.

TABLE 4 ______________________________________ State of Shift Initially 1 2 3 4 5 6 7 8 Register 109 ______________________________________ Terminal 214/J1 0 0 0 0 0 0 0 0 0 Terminal 212/T1 0 0 0 0 0 0 0 0 1 Q1 0 0 0 0 0 0 0 0 0 Q2 1 1 1 1 1 1 1 1 1 J2 0 0 0 0 0 0 0 0 0 T2 0 0 0 0 0 0 1 0 0 Q3 0 0 0 0 0 0 0 0 0 Q4 1 1 1 1 1 1 1 1 1 G 201 INPUT (a) 0 0 0 0 0 0 0 0 0 G 201 INPUT (b) 1 1 1 1 1 1 1 1 1 G 201 OUTPUT 1 1 1 1 1 1 1 1 1 G 202 INPUT (a) 1 1 1 1 1 1 1 1 1 G 202 INPUT (b) 0 0 0 0 0 0 0 0 0 G 202 OUTPUT (a) 1 1 1 1 1 1 1 1 1 G 203 INPUT (a) 1 1 1 1 1 1 1 1 1 G 203 INPUT (b) 0 0 0 0 0 0 0 0 1 G 203 OUTPUT 0 0 0 0 0 0 0 0 1 ______________________________________ 1 = HIGH STATE 0 = LOW STATE

From Table 4 in association with Table 3, it will be appreciated that since the J1 input of the flip-flop FF201 is "low" and the K1 input is "high," then the terminal Q1 will be "low" and the output terminal 210 will be "high" for every state of the shift register 109 so long as the switch S200 is open. Thus, the timing line TL is not rendered "low" due to the operation of the gate G201. Accordingly, with the switch S200 open, the programme of switching operations followed by the device depends upon the setting of the appropriate push-button or buttons of the programme selection means PSM and is not influenced by the programme override circuit POC. However, since the Q2 output of the flip-flop FF201 is in the "high" state and the switch S200 is open, making the input (b) of the "nand" gate G202 "low" then the output of the "nand" gate G202 is "high" opening the gate G203 to actuation information produced at the control point 108. Accordingly, the output of the gate G203 goes "high" in the eighth state of the shift register 109 and at the transition from the eighth state to the initial state, the shift register 109 is arrested by the release of the switch PSS as previously described.

Table 5 following is a truth table showing the states of the relevant parts of the programme override circuit POC and at relevant inputs and outputs of the gates G202 and G203 corresponding with indicated states of the shift register 109 when the switch S200 is closed.

TABLE 5 __________________________________________________________________________ State of Shift Initially 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 Register 109 __________________________________________________________________________ Terminal 214/J1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Terminal 212/T1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Q1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Q2 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 J2 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 T2 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 Q3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 Q4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 G201 INPUT (a) 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 G201 INPUT (b) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 G201 OUTPUT 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 G202 OUTPUT (a) 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 G202 INPUT (b) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 G202 OUTPUT 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 G203 INPUT (a) 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 G203 INPUT (b) 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 G203 OUTPUT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 __________________________________________________________________________ 1 = High State 0 = Low State

From the Table 5, it will be appreciated that during the first eight states of the shift register 109, the output of the gate G201 and hence the output terminal 201 is "high" and thus the timing line TL is not made "low" due to the operation of the circuit POC during these first eight states. Accordingly, with the switch S200 closed, the programme of switching operations followed by the device depends upon the setting of the appropriate pushbutton or buttons of the programme selection means PSM and is not influenced by the programme override circuit POC during these first eight states. However, with the switch S200 closed, both inputs of the gate G202 are "high" during the first eight states of the shift register 109 so that the output of the gate G202 is "low" and the gate G203 is closed to actuation information produced at the control point 108. Thus, the shift register 109 is not arrested upon termination of the eighth state but commences a second, eight-state cycle. In addition, upon transition from the eighth state of the first cycle to the initial state of the second cycle, the output Q1 of the flip-flop FF201 changes from "low" to "high" so that both inputs of the "nand" gate G201 are now "high" and the output of the "nand" gate G201 goes "low" making the timing line TL "low" thereby rendering the transistor TR102 non-conductive and ensuring that the transistor TR101 is also non-conductive. Thus, the oscillator 128 commences to oscillate in the mode in which an output pulse is produced every 5 milliseconds and the shift register 109 is rapidly advanced through the first, second, third, fourth, fifth and sixth states of the second, eight-state cycle. At the end of the sixth state, the flip-flop FF202 changes state as the control point 106 goes from "high" to "low" and as a result the output terminal Q4 goes "low" making the output of the "nand" gate "high" once more so that the timing line TL is no longer made "low" due to the circuit POC and the seventh and eighth states of the second cycle of the shift register are carried out in accordance with the selected programme.

Of course, with the change of state of the flip-flop FF201 at the end of the eighth state of the first cycle, the output Q2 became, "low" and, since the input (b) of the "nand" gate G202 is "high" as a result of the switch S200 being closed the output of the gate G202 is "high" rendering the "and" gate G203 open for actuation information to be passed by the gate G203 so that when the end of the eighth state of the second cycle of the shift register 109 is reached, the shift register 109 is arrested in the manner previously described.

In practice, assuming the "Super-Wash" programme had been selected and the switch S200 had been closed, then after pressing the start switch PSS, the "Super-Wash" programme in accordance with the chart of FIG. 5 would be performed followed by repetition of the "pump" and "spin" functions whereupon the shift register would be arrested.

Again, connection of the terminals 211 and 213 is not restricted to the control points 108 and 106 respectively but may be to any desired control points of the plurality. Moreover, the programme override circuit POC of FIG. 9 may be employed in association with devices other than that described. For instance, in association with switching devices having more than eight states and hence more than eight control points and associated combinations of switching functions.

Claims

What is claimed is:

1. A switching device comprising: a plurality of control points and a plurality of switching elements, each said control point being associated with one or more of said switching elements, said switching elements being actuated by the presence of actuation information at said associated control point, a shift register having states related to said control points for supplying actuation information to said plurality of control points in a predetermined sequence under the control of timing pulses which advance the states of the register whereby a series of combinations of switching functions may be performed, the intervals between occurrence of consecutive timing pulses determining the period of time for which actuation information is present at the respective control points, a pulse supply means capable of supplying to the shift register timing pulses either recurring at relatively long intervals or recurring at relatively short intervals, means for deriving programme information from the actuation information present at said control points, the derived programme information being applied to said pulse supply means for determining, in accordance with a programme, whether the timing pulses supplied to said shift register recur at relatively long intervals or recur at relatively short intervals, a multistable programme override circuit having two stable output states, one output state providing for continuous supply to the shift register of timing pulses recurring at relatively short intervals, the other output state providing for supply to the shift register of timing pulses recurring at either relatively long intervals or at relatively short intervals in accordance with the programme, transition of the output state of the override circuit being controlled by information derived from one or more control points.

2. A switching device as claimed in claim 1, wherein said pulse supply means includes a discrete first pulse source for producing pulses recurring at relatively long intervals, a discrete second pulse source for producing pulses recurring at relatively short intervals and further including a selection circuit selectively making said shift register responsive either to said first pulse source or said second pulse source, said selection circuit being responsive to said override circuit output information and when the output of said override circuit is in said one output state said selection circuit permits timing pulses to be derived only from the said second pulse source and when the output of said override circuit is in the said other state, said selection circuit permits timing pulses to be derived from either the first or second pulse source in accordance with said programme information.

3. A switching device as claimed in claim 1, wherein said pulse supply means includes a pulse source from whence timing pulses may be derived for supply to the shift register, the pulse source being adapted to operate in either a first mode of operation or a second mode of operation, the pulse source producing pulses recurring at relatively long intervals when operating in the first mode and producing pulses recurring at relatively short intervals when operating in the second mode, said override circuit output information being so applied to control the pulse source that when the output of said override circuit is in said one output state said pulse source operates only in the second mode, whereas when the output of the said override circuit is in the said other state, the pulse source operates in either the first or second mode in accordance with the said programme information.

4. A switching device as claimed in claim 3, wherein in that the said pulse source is in the form of a relaxation oscillator, the repetition frequency of which is determined by the series combination of two capacitors one of which is shunted by the collector-emitter path of a transistor adapted to be rendered either conductive so that the pulse source operates in the said first mode or non-conductive so that the pulse source operates in the said second mode, and further includes pulse source control means for rendering the transistor conductive when the output of said override circuit is in said one output state or conductive in response to the said programme information when the output of said override circuit is in the said other output state.

5. A switching device as claimed in claim 4 further including switching means for switching said override circuit into or out of a non-override condition in which the output of the override circuit is in the said other output state and transition of the output state is inhibited.

6. A switching device as claimed in claim 5 wherein a programme selection means for providing selection information and comparison means for comparing selection information thus provided with actuation information present at the said respective control points of the plurality produces said programme information.

7. A switching device as claimed in claim 6 wherein said programme override circuit is a triggerable bistable device to which the said actuation information produced at said predetermined control points is supplied to trigger the bistable device into an opposite state and thereby change the output state of the bistable device.

8. A switching device as claimed in claim 6 having said shift register arranged to be arrested at the completion of a cycle of the register states and in which the said programme override circuit is a triggerable multistable device having more than two stable states, one stable state producing information at an auxiliary output of the multistable device which prevents the said shift register from being arrested at the completion of a cycle of the register states, the said actuation information produced at the said predetermined control points being supplied to trigger the multistable device.

9. An electronically programable switching system comprising:

a plurality of control points;

a plurality of switching elements, each said switching element being operatively responsive to actuation information on at least one predetermined control point;

A shift register supplying actuation information to said plurality of control points in a predetermined sequence in response to timing pulses which advance the states of said register, said shift register being responsive to the intervals between the occurrence of consecutive timing pulses to vary the period of time for which actuation information is present at said plurality of control points;

pulse supply means for supplying to the shift register timing pulses at relatively short intervals and also at relatively long intervals;

means for varying the interval between occurrence of consecutive timing pulses responsive to the state of said control points.