U.S. patent number 3,818,483 [Application Number 05/294,636] was granted by the patent office on 1974-06-18 for graphic display system.
This patent grant is currently assigned to Ricoh Co., Ltd.. Invention is credited to Takashi Inoue, Satoshi Yamauchi.
United States Patent |
3,818,483 |
Yamauchi , et al. |
June 18, 1974 |
GRAPHIC DISPLAY SYSTEM
Abstract
Graphic display system for graphically indicating the responses
from a number of students to a question wherein the sampling cycle
for displaying the answers to each question is based on the time
that a certain percentage of the students take to answer that
question.
Inventors: |
Yamauchi; Satoshi (Tokyo,
JA), Inoue; Takashi (Asaka, JA) |
Assignee: |
Ricoh Co., Ltd. (Tokyo,
JA)
|
Family
ID: |
13639698 |
Appl.
No.: |
05/294,636 |
Filed: |
October 3, 1972 |
Foreign Application Priority Data
|
|
|
|
|
Oct 4, 1971 [JA] |
|
|
46-77648 |
|
Current U.S.
Class: |
434/323; 377/20;
377/112; 434/350; 434/353; 345/60; 345/82; 345/24 |
Current CPC
Class: |
G09B
5/00 (20130101); G06F 17/18 (20130101) |
Current International
Class: |
G09B
5/00 (20060101); G06F 17/18 (20060101); G08b
005/36 () |
Field of
Search: |
;340/324A,324AD,212,324R
;346/37 ;235/52 ;35/48R |
References Cited
[Referenced By]
U.S. Patent Documents
Primary Examiner: Trafton; David L.
Attorney, Agent or Firm: Cooper, Dunham, Clark, Griffin
& Moran
Claims
What is claimed is:
1. A graphic display system for indicating the dynamic answer
response of a set of answerers to a question comprising:
means for detecting the time lag between the posing of a question
and the response thereto by a defined subset of said answerers;
means for providing a timing signal having a cycle which is a
defined function of said time lag;
means for detecting the total number of responses to the question
at each of a plurality of sample times occurring at a frequency
which is a defined function of the cycle of said timing signal;
and
means for displaying the detected total number of responses for
each of said sample times on uniformly spaced consecutive portions
of an indicating surface to provide a representation of a curve
showing the dynamic answer response of the answerers to the
question, wherein the spacing between said consecutive portions is
a function of said time lag.
2. A graphic display system as in claim 1 wherein the displaying
means comprise a two-dimensional indicating surface, an X-drive and
a Y-drive each indicating a position along one of said dimensions,
means for providing a display point at the intersection of the
Y-axis indicated by the Y-drive and the X-axis indicated by the
X-drive, and wherein the means for detecting the total number of
responses at sample times occurring as a defined function of said
timing signal comprise a current response register for storing a
count of the total number of answer responses that have occurred, a
timing signals counter for storing the current count of the timing
signals that have occurred, means for transferring a decoded
representation of the contents of the current responses counter to
the Y-drive of the display means, and means for transferring a
decoded representation of the contents of the timing signals
counter to the X-drive of the display means, whereby the display
means displays a decoded representation of the total number of
answer responses at each occurrence of a timing signal, at an
X-position defined by the current number of timing signals.
3. A graphic display system as in claim 2 wherein the display means
include a matrix of luminescent diodes.
4. A graphic display system as in claim 1 wherein the display means
comprise a cathode ray tube and wherein the means for detecting the
total number of answer responses at sample times occurring as a
defined function of said timing signals comprise a register storing
the total current count of answer responses, a counter storing the
total number of timing signals that have occurred, means for
driving a first axis of the cathode ray tube as a function of the
contents of said register, and means for driving a second axis of
said cathode ray tube as a function of the contents of said
counter.
5. A graphic display system as in claim 1 wherein the display means
comprise a matrix of gas discharge tubes.
6. A graphic display system as in claim 1 wherein the display means
comprise a matrix of luminescent diodes.
7. A graphic display system as in claim 1 wherein the display means
comprise a cathode ray tube.
Description
BACKGROUND OF THE INVENTION
The present invention relates to the graphic display system and
more in particular, the present invention relates to the graphic
display adopted for indicating dynamic phenomenon.
The so called teaching machine for giving questions to a large
number of students and for finding the total of the answers from
the students, is generally known to those skilled in the art. In
the conventional teaching machine, the periodically changing
answering phenomena of students to a certain question, are recorded
in penrecorder in most cases. The above mentioned penrecorder
system is adopted for carrying out the analysis and analytical
research of the answering phenomena thereafter, but it is not
adopted for instantaneously observing the periodically changing
answering phenomena.
In order to overcome the above mentioned drawback of the
conventional penrecorder system, those skilled in the art can
easily think of the employment of graphic display for graphically
indicating various kinds of phenomena electro-optically, in place
of penrecorder. However, in accordance with the conventional
display devices, the following problems are brought about because
the sampling cycle, i.e., the time corresponding to the unit scale
width in the direction of time axis on the indication surface. For
example, when a certain question is given to students, the time
required for the answers of the students to the question, is
greatly varied by the ease or difficulty of the question or the
abilities of the students. Therefore, when all the answering
phenomena ranging from the case where the answering time is short,
to the case where the answering time is long, are to be displayed
on the same display indication surface, it is necessary to extend
the time axis on the indication surface, and the size of the
display device is excessively increased. On the contrary, when the
time axis on the display surface is made short, it is impossible to
sufficiently indicate the answers in the case of a question that
takes a long time to answer.
The object of this invention is to provide a graphic display system
which overcomes the above mentioned problems of the conventional
devices.
Another object of the present invention is to provide a graphic
display system capable of automatically changing the sampling cycle
in accordance with the change of the speed with which the questions
are answered.
In accordance with an embodiment of the present invention, when a
certain question is given to a number of students, the time rate of
the answers of the students to the question can be graphically
indicated on the indication surface by luminescent diodes,
discharge tubes on a CRT. First, the time (.tau.) required from the
presentation of a question to the response of, for instance, 5
percent of the students, is measured. Next, the repetitive cycle of
the sampling pulse for displaying the answers is determined on the
basis of the time (.tau.), and thereafter, the student answers are
displayed on the indication surface. At the same time, the scale in
the direction of time axis on the indication surface is determined
on the basis of said time (.tau.).
The details of the present invention are explained in accordance
with the attached drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a diagram showing the rate at which the students provide
answers to a typical question;
FIG. 2 is a block diagram showing a sampling pulse generating
circuit as the main portion of the graphic display device of the
present invention;
FIG. 3 is a diagram showing the circuit of a display panel
utilizing a number of discharge tubes;
FIG. 4 is a diagram showing the circuit of a display panel
utilizing a plural number of luminescent diodes;
FIGS. 5A and 5B, when fitted together as shown in FIG. 5, are a
block diagram showing an embodiment of this invention utilizing the
luminescent diode display panel;
FIGS. 6A and 6B, when fitted together as shown in FIG. 6, are a
block diagram showing another embodiment of this invention
utilizing a CRT.
DESCRIPTION OF THE PREFERRED EMBODIMENT
FIG. 1 shows the diagram showing how the rate of response from the
students to a typical question. In FIG. 1, the abscissa shows time,
and the ordinate indicates answer-rate.
What is meant by "answer-rate" in this specification is defined by
the following formula;
FORMULA
Answer-rate = Number of students who have answered/Total number of
students .times. 100 (1)
From FIG. 1, it is seen that the answer rate of the students is
extremely low till a certain period of time has passed from the
time when the question is given to the students (the time is shown
by .tau.) and when the time .tau. has passed, it is a logarithmical
curve. And, for example, when the 3.tau. time has passed, the
answer rate arrives at certain level. The time .tau. is greatly
varied by the ease or difficulty of the question, or by the ability
of students. In the same manner, the gradient of the curve after
having passed the time .tau. is closely related to the time .tau..
In other words, when the time .tau. is large, the gradient of the
curve becomes "dull," and when the time .tau. is small, the
gradient becomes "sharp."
Therefore, in accordance with the present invention, the time till
the answer rate becomes such as 5 percent is measured, this time is
defined as the time .tau., and from the time .tau., the time, i.e.,
the sampling cycle of the display curve is determined. In other
words, the unit time (t) showing one unit of the time axis of the
display is changed in correspondence to the time (.tau.).
Therefore, in accordance with the present invention, it becomes
possible to accurately and conveniently indicate the student
answers on the same display surface even when the answer time
varies greatly from question to question the answer time.
In the following paragraphs, the method for generating the sampling
pulse, which is the essence of the present invention, is explained
in accordance with FIG. 2.
In FIG. 2, A-Counter 1 is a binary counter for counting a first
pulse train P.sub.1, and B-Counter 2 is also a binary counter for
counting a second pulse train P.sub.2. A start signal P.sub.s
changes to a high level at the time when a question is given to the
students. On the other hand, a stop signal P.sub.t changes to a
high level when the rate of the answer to the question reaches 5
percent. The stop signal P.sub.t may be provided, for example, by a
counter 2a which receives as an input answer responses over a line
l and provides and output when its count reaches a predetermined
number corresponding to 5 percent of all answerers. Namely, the
time ranging from the time when the start signal P.sub.s has become
high, to the time when the stop signal P.sub.t becomes high,
corresponds to the time (.tau.). When the start signal P.sub.s
becomes high a flipflop F.sub.1 takes its set state, and the set
output of flipflop F.sub.1 is supplied to an AND Gate G.sub.1.
Therefore, when the flipflop F.sub.1 is set, the first pulse train
P.sub.1 passes through the AND Gate G.sub.1 and is supplied to
A-Counter 1, and is counted. Thereafter, the student answers start
and are suitably counted, and when the answer-rate reaches 5
percent, the flipflop F.sub.1 is reset by the stop signal P.sub.t.
Thereby the counting operation of A-Counter 1 stops. In this case,
a value corresponding to the time (.tau.) till the answer rate has
reached 5 percent is set in A-Counter 1.
The reset output of flipflop F.sub.1 is supplied to the AND Gate
G'.sub.2, and therefore when the flipflop F.sub.1 is reset, the
second pulse train P.sub.2 passes through the AND Gate G'.sub.2 and
is supplied to B-Counter 2 to be counted.
When the count in B-Counter 2 agrees with the contents of A-Counter
1, a coincidence output is emitted from a coincidence circuit 3, to
drive a mono-multi-vibrator 4. P.sub.c is the output pulse from the
mono-multi-vibrator 4. B-Counter 2 is cleared by this pulse
P.sub.c, and thereafter, when pulse P.sub.c is eliminated,
B-Counter 2 starts counting again, and the content thereof is
compared with the content of A-Counter 1. Thereafter, the above
mentioned operation is repeated, and the pulse P.sub.c having the
predetermined repetitive cycle is emitted from the
mono-multi-vibrator 4.
Suppose that the repetitive cycles (the periods) of the first pulse
train P.sub.1 and the second pulse train P.sub.2 are respectively
set to be T.sub.1 and T.sub.2, and that the two repetitive cycles
are interrelated by the below given formula;
Formula:
t.sub.1 = n.sup.. T.sub.2 (2)
when the counting of A-Counter 1 is set to be n.sub.1, the time
(.tau.) is obtained by the following formula;
Formula:
.tau. = n.sub.1.sup.. n.sup.. T.sub.1 (3)
when the formula (2) is substituted in the formula (3), the
following formula can be obtained;
Formula:
.tau. = n.sub.1.sup.. n.sup.. T.sub.2 (4)
on the other hand, when the counting of B-Counter 2 is supposed to
be n.sub.2, the cycle T.sub.c of the pulse P.sub.c can be obtained
by the following formula;
Formula:
t.sub.c = n.sub.2.sup.. T.sub.2 (5)
therefore, from the formulae (4) and (5), the below given formula
(6) can be obtained;
Formula:
.tau. = n.sub.1 /n.sub.2.sup.. n.sup.. T.sub.c (6)
When the contents of the two counters 1 and 2 coincide, n.sub.1
becomes equal to n.sub.2, and therefore, the formula (6) becomes as
follows;
Formula:
.tau. = n.sup.. T.sub.c (7)
From the above given formula (7), when it is presumed that one
graduation of the display surface time axis corresponds to the
pulse P.sub.c, the time .tau. is always represented by the (n)
number of graduations. In other words, the repetitive cycle (i.e.
the period) of the pulse P.sub.c is changed in correspondence to
the way the time (.tau.) changes. In the present invention, the
pulse P.sub.c is utilized as the sampling pulse. The cycle T.sub.1
represents the fineness of the divisions of the unit time t, and is
the factor for determining the precision of the cycle T.sub.c, and
therefore, it is preferable that T.sub.1 is smaller. On the other
hand, the integer n stands for the number of the graduations
dividing the time (.tau.), and determines the fineness of the
reproduced graph, and therefore it is better when the value of n is
greater. When the graduations are determined as mentioned above,
the counting (n) of A-Counter 1 is indicated on the position of
graduations corresponding to the time (.tau.) on the time axis of
the indication surface, and the values of 2n or 3n are indicated on
the graduations corresponding to 2.tau. and 3.tau..
FIG. 3 is a diagram showing an embodiment of the graphic display
panel in which indicating discharge tubes are used.
As shown in FIG. 3, X drive lines X.sub.1 -X.sub.n are extended
from the stages of a counter 6, which is an X drive circuit and Y
drive lines Y.sub.1 -Y.sub.m are extended through transistors
TR.sub.yl -TR.sub.ym, which are an Y drive circuit 7. A decoder 5
is connected with the Y drive circuit 7. Indicating lamps L.sub.ll
-L.sub.mn are disposed at the points of intersection between the X
and Y drive lines and the voltages V.sub.1 and V.sub.2 are applied
to the terminals of the indicating lamps L.sub.ll -L.sub.mn through
resistors.
The answer indicating data arrives on the input lines l. The number
of answers generally increases as time elapses and converges toward
a certain value after a predetermined time. A low-level signal
appears on the Y drive line of the stage which corresponds to the
decode output of the decoder 5. In response to the timming pulses
P.sub.s illustrated in FIG. 2 a time axis counter in the x-drive
circuit 6 steps so that low-level signals appear on the X drive
lines sequentially. As a result the indicating lamps L at the
points of intersection of the X and Y drive lines with the
low-level signals are turned on sequentially. Once the indicating
lamps are turned on, they may remains turned on even after the
drive signals on the X and Y drive lines have returned to the high
level. The above described graphic display device is of a
conventional type, for example disclosed in U.S. Pat. application
Ser. No. 256,373, filed May 24, 1972 by Takashi Inoue. It is seen
that the segment connecting the adjacent turned-on indicating lamps
L indicates the input data on the line l, for example, the rate of
change in response ratio with respect to time.
FIG. 4 is a diagram showing a graphic display panel in which
luminescent diodes are used. In the embodiment of FIG. 4, an X
driver circuit 8 is composed of transistors TR.sub.x1, TR.sub.x2, .
. . , TR.sub.xn, X driver lines X.sub.1, X.sub.2, . . . , X.sub.n
are connected to the respective collectors of the transistors
TR.sub.xl .about. TR.sub.xn, and in the same manner Y driver lines
Y.sub.1, Y.sub.2, . . . , Y.sub.m are connected to the respective
collectors of transistors TR.sub.yl .about. TR.sub.ym which form a
Y driver circuit 9. Luminescent diodes D.sub.l .sub.l .about.
D.sub.m .sub.n are respectively connected to the respective
crossing points on the X driver lines and Y driver lines X.sub.l
.about. X.sub.n, Y.sub.l .about. Y.sub.m. The respective emitters
of the transistors TR.sub.yl .about. TR.sub.ym composing the Y
driver circuit 9 are connected to a common power source +V, and
current controlling resistances R are connected to the Y driver
lines Y.sub.l .about. Y.sub.m.
For example, when X driver pulse P.sub.xl and Y driver pulse
P.sub.yl have arrived, the transistor TR.sub.xl of X driver circuit
8 and the transistor TR.sub.yl of Y driver circuit 9 are put on,
and X driver lines X.sub.l and Y driver lines Y.sub.l are selected.
As a result, current is passed through the luminescent diode
D.sub.l .sub.l, and said diode luminesces. Next, when the driver
pulse P.sub.x2 and P.sub.x1 have arrived, X driver circuit L.sub.x2
and L.sub.y1 are selected, and the diode D.sub.1 .sub.2 luminesces.
Thus, in the the same manner, the desired diodes luminesce in turn.
Luminescent diodes do not remain on after the energizing current is
removed. Therefore, for statically indicating a desired curve on
the display panel, it is necessary to repeat the above-stated
action at a pre-set cycle in a conventional manner.
FIG. 5, which comprises 5A and 5B, is a block-diagram of an
embodiment of the invention in which produced when the display
panel FIG. 4 is used.
In the block diagram of FIG. J, block 10 is a sampling pulse
generating circuit as is explained in accordance with FIG. 2, and
block 11 is the display unit in which the luminescent diodes are
used, as is explained in accordance with FIG. 4. The indication
surface 12 of the display unit 11, is composed of 400 luminescent
diodes (20 .times. 20) arranged in the form of matrix. For the sake
of convenience, the explanation here is given on the presumption
that the abscissa (X-axis) X.sub.1 .about. X.sub.20, and the
ordinate (Y-axis) Y.sub.1 .about. Y.sub.20 on the indication
surface 12, are both designated by 5 bits binary code. 15 is a
recirculating type shift register of 100 bit structure storing
binary code signals of the ordinate (Y-axis) corresponding to each
of the respective X.sub.1, X.sub.2, . . . , X.sub.20 signals in the
direction of the abscissa (X-axis) on the indication surface
12.
Suppose that the Y-axis codes Y.sub.j (j = 1, 2, . . . , 20)
corresponding to position X.sub.1 are stored in the bit positions
99 to 95 of the register 15, and that Y-axis codes Y'.sub.j
corresponding to X.sub.2 position are stored on the following bit
positions 94 to 90 of the register 15, and in the same manner
Y-axis codes corresponding to X.sub.20 position are stored in bit
positions 4 to 0. Every time a clock pulse P.sub.l is given on the
line l.sub.1, the shift register 15 is read out serially by being
shifted to the right by one bit, and then the bit that has been
shifted out is transferred to the register 16 through the line
l.sub.2. At the same time, the read out bit is circulated through
the line l.sub.3, AND Gate G.sub.3, OR Gate G.sub.4, and is
re-stored into the register 15. The register 16 is 5 bit shift
register having the memory capacity sufficient for storing one
Y-axis code. Therefore, when the first 5 pulses are given to the
line l.sub.1, an Y-axis code Y.sub.j corresponding to X.sub.1
position is stored in the register 16.
The counter 19 counts the clock pulse P.sub.l on the line l.sub.1,
and emits a 1 signal per 5 counts. The above mentioned 1 signal is
supplied to the AND Gates G.sub.5 -1 .about. G.sub.5 -5, through
l.sub.4. As a result, the gates G.sub.5 -1 .about. G.sub.5 -5 are
energized, and the content of the register 16 are parallelly read
out. As is apparent from the above given description, when the
first 5 clock pulses P.sub.l have arrived at the line l.sub.1, the
Y-axis code stored in the register 16 corresponding to the X.sub.1
position is parallelly read out, and the is transferred to the
buffer register 17 through the gates G.sub.5 -1 .about. G.sub.5 -5.
Thereafter, the content of the buffer register 17 is decoded by Y
decoder 18, and one Y-drive signal P.sub.yj corresponding to the
above mentioned Y-axis code Y.sub.j is emitted.
The 1 signal emitted from the Counter 19 is supplied to Counter 20
through the line l.sub.5. The counter 20 is 5 bit binary counter,
and is a stepped forward by the 1 signal emitted from the Counter
19. In other words, every time the shift register 15 is shifted to
the right by 5 bits, the Counter 20 is stepped by one count. As is
apparent from the above description, the Counter 20 designates the
X positions corresponding to the respective Y-axis codes stored the
register 16. The content of the counter 20 is decoded by an
X-decoder 21.
When the first 5 clock pulses have arrived at the line l.sub.1 ,
the counter 20 counts 1 and an X-drive signal P.sub.x1 for
selecting X.sub.l position is emitted from the X-decoder 21. The X
and Y driver circuits 8, 9 are driven by said Y-drive signal
P.sub.yj and said X-drive signal P.sub.xl, and the luminescent
diode on the coordinates (X.sub.l, Y.sub.j) luminesces. The
operation of the display unit 11 was explained before in accordance
with FIG. 3, and it is omitted here. Y-axis codes (Y'.sub.j,
Y".sub.j, . . .) are stored in the shift register 16 every time 5
clock pulses P.sub.l arrive, and the X positions (X.sub.2, X.sub.3,
. . .) corresponding to the respective Y-axis codes, are designated
by Counter 20. The contents of the shift register 16 and Counter 20
are decoded by the decoders 18 and 21, respectively and a result,
the luminescent diodes on the coordinates (X.sub.2, Y'.sub.j),
(X.sub.3, Y".sub.j) . . . are selected and luminesce. Thus, when a
luminescent diode on the final position along the X-axis, i.e., on
X.sub.20, the above mentioned operation is repeated. The content of
the shift register 15 is visually indicated on the indication
surface 12 in the form of curve.
In this case, the indication surface 12 shows the student response
to a question. The code signals designated the answer-rate are
transmitted, after the 5 percent point, into the answer-rate
register 13 through the input line l.sub.6. The answer-rate
register 13 is 5 bit register as in the case of the shift register
16. The 1 signal from the Counter 19 is supplied into the AND Gates
G.sub.1 -1 .about. G.sub.1 -5 through the line l.sub.7 and
therefore, the content of the answer-rate register 13 is parallelly
sent into the shift register 14 every time the five clock pulses
P.sub.l have arrived, and thereafter, the content of the shift
register 14 is serially read out on the line l.sub.8 by the clock
pulse P.sub.l but Gate G.sub.2 is in its off state, and therefore
it is not sent to the register 15.
In this case, the 5 percent answer-rate corresponds to the
graduation Y.sub.1 of Y-axis, and the 10 percent answer-rate
correspondes to the graduation Y.sub.2.
In the same manner 100 percent correct answer rate corresponds to
Y.sub.20 axis. As explained in FIG. 2, when the time from the
presentation of a question to the time when 5 percent answer rate
is obtained, is set to be (.tau.), the repetitive cycle T.sub.c of
the timing pulse P.sub.c emitted from the timing pulse generating
circuit 10 is represented by the formula given below;
Formula:
t.sub.c = .tau./n
In the above given formula n is presumed to be 5. And, the
repetitive cycle of clock pulse P.sub.l is remarkably quick when
compared with that of the timing pulse P.sub.c.
The timing pulse P.sub.c emitted from the timing pulse generating
circuit 10 is counted by Counter 22. The Counter 22 is a 5 bit
binary counter as in the case of the Counter 20. The comparator
circuit 23 compares the countings of Counter 20 and Counter 22, and
when the two countings coincide, 1 a signal is emitted to the line
l.sub.9. AND Gate G.sub.2 is put on ON state by 1 signal on the
line l.sub.9, and AND Gate G.sub.3 becomes in the OFF state. Here,
N is an inverter circuit. Therefore, the answer-rate data read out
on the line l.sub.8 are written into the shift register 15 through
the AND Gate G.sub.2 and OR Gate G.sub.4. Thus, the above mentioned
operation is repeated every time 1 signal is emitted onto the line
l.sub.9 from the comparator circuit 23, and the answer-rate data
are written into the shift register 15. The content of the Counter
20 indicates the respective positions X.sub.1, X.sub.2, . . . on
X-axis, and therefore, the data to be written into the shift
register 15 correspond to the respective X positions. The positions
X.sub.1, X.sub.5, X.sub.15, and X.sub.20 in the direction of X-axis
correspond to 2.tau., 3.tau., and 4.tau.. Thus, the time
graduations in X-axis are changed in correspondence to the change
of time .tau..
It should be understood that the system shown in FIG. 5 can be
applied to a display panel provided with discharge tubes.
FIG. 6, consisting of FIGS. 6A and 6B, is a diagram showing another
embodiment in which a CRT is used. In FIG. 6, block 10 is a
sampling pulse generating circuit, and 100 is an indicating CRT. In
this embodiment the indication surface of the CRT 100 is divided
into a total of 20 .times. 20 = 400 dots. A circulation type shift
register 104 stores 400 bits, and the respective bit positions
correspond to the dot positions on the CRT 100. The content of the
shift register 104 is supplied to the amplifier 105 by right hand
serial shifting on the clock pulse P.sub.l, and at the same time,
the content of the shift register 104 is rewritten through AND Gate
G.sub.2 and an OR Gate G.sub.4. An amplifier 105 gives a
predetermined brightness signal to the CRT 100 when a signal is
given thereto from the register 104.
A Y-Counter 106 is a 5-bit binary counter for counting the dot
positions in Y-axis (the perpendicular direction) while being
supplied with clock signal P.sub.l. The content of said Y-Counter
106 is converted into the corresponding analogue voltage with D-A
converter 107. The analogue voltage of the converter 107 is
amplified with the amplifier 108, and it is supplied to CRT 100 as
the perpendicular deflection signal. In the same manner, X-Counter
109 is a 5 bit binary counter stepped forward by one every time the
Y-Counter 106 makes 20 counts. As is apparent from the above
description, X-Counter 109 determines the respective graduation
positions of the electron beam on the X-axis. The content of the
X-Counter 109 is converted into the corresponding voltage analogue
by D-A converter 110, and then amplified with the amplifier 111,
and is supplied as the horizontal deflection signal to the CRT 100.
The above mentioned structure is the same as the structure of the
conventional CRT display device, and therefore the explanations of
the details of the conventional CRT display device are omitted
here.
The indication data are supplied into the register 101 from the
input line l.sub.10, and are decoded by the decoder 102. The output
line of the decoder 102 is composed of 20 lines in correspondence
to the number of the dot positions in the direction of Y-axis on
the indication surface, and the 1 signal from the Counter 106 is
supplied also to AND Gates G.sub.1 -1 .about. G.sub.1 -20.
Therefore, every time 20 clock pulses P.sub.l have arrived, the
output of the decoder 102 is transferred parallelly to the shift
register 103 through the Gates G.sub.1 -1 .about. G.sub.1 -20. The
content of the shift register 103 is serially read out on the line
l.sub.ll by being right hand shifted under the control of the clock
pulse P.sub.l. The AND Gate G.sub.3 is in the OFF state normally,
and therefore the data on the line l.sub.11 are not written in the
shift register 104.
In the same manner as in FIG. 5, the timing signal emitted from the
block 10 is counted by Counter 112. The comparator circuit 113
compares the counting of Counters 109 and 112, and when the
countings of the two counters are the same, a 1 signal is emitted
onto the line l.sub.12. Thereby, AND Gate G.sub.2 is turned into
OFF state, and AND Gate G.sub.3 is turned into ON state, and the 20
bit data on the line l.sub.ll are written into the shift register
104 through the gates G.sub.3 and G.sub.4. As can be easily
understood, the position of the data in the direction of X-axis
written in said shift register 104, is designated by the counting
of X-Counter 109.
The embodiments shown in the attached diagrams are mere examples,
and various kinds of embodiments other than those given in the
attached diagrams, can be thought of.
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