U.S. patent number 3,797,307 [Application Number 05/219,327] was granted by the patent office on 1974-03-19 for coin discriminator.
This patent grant is currently assigned to Arthur D. Little, Inc.. Invention is credited to Reed H. Johnston.
United States Patent |
3,797,307 |
Johnston |
March 19, 1974 |
**Please see images for:
( Certificate of Correction ) ** |
COIN DISCRIMINATOR
Abstract
A method and apparatus for discriminating between coins with
respect to denomination and authenticity, employing means for
performing two or more coin tests, means for storing a value
dependent upon the results of the first coin test, and means for
evaluating the results of the second coin test in a manner
dependent upon the results of the first coin test.
Inventors: |
Johnston; Reed H. (Wellesley,
MA) |
Assignee: |
Arthur D. Little, Inc.
(Cambridge, MA)
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Family
ID: |
22818844 |
Appl.
No.: |
05/219,327 |
Filed: |
January 20, 1972 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
Issue Date |
|
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172096 |
Aug 16, 1971 |
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Current U.S.
Class: |
73/163;
194/325 |
Current CPC
Class: |
G07D
5/02 (20130101); G07D 5/08 (20130101) |
Current International
Class: |
G07D
5/02 (20060101); G07D 5/08 (20060101); G07D
5/00 (20060101); G07f 003/02 () |
Field of
Search: |
;73/432R,163
;194/9,1A,101 ;209/82 |
References Cited
[Referenced By]
U.S. Patent Documents
Primary Examiner: Swisher; S. Clement
Attorney, Agent or Firm: Davis, Hoxie, Faithful &
Hapgood
Parent Case Text
This application is a continuation-in-part of my application Ser.
No. 172,096, filed Aug. 16, 1971 now abandoned.
Claims
I claim:
1. A method of discriminating among coins with respect to
denomination, authenticity and the like comprising the steps of
examining a first characteristic of a coin and producing a first
value which is a quantitative function of said first
characteristic,
examining a second characteristic of the coin and producing a
second value which is a quantitative function of said second
characteristic,
comparing the first value with the second value, and
producing an output signal indicating whether the difference
between the compared values is within a predetermined range.
2. The method of claim 1 wherein first and second values are each
represented by a first and a second electrical pulse signal,
respectively.
3. The method of claim 2 which includes the steps of counting the
pulses comprising the first pulse signal and establishing the pulse
rate of the second signal as a function of the total count of the
first pulse signal.
4. The method of claim 3 which includes the steps of counting the
pulses of one pulse signal in a first counter, counting the pulses
of another pulse signal in a second counter, and comparing totals
of the counters.
5. The method of claim 3 which includes the steps of counting the
pulses of the first pulse signal in one direction into an up-down
counter, counting the pulses of the second pulse signal in the
opposite direction into that counter, and comparing the remainder
in the counter with a predetermined range.
6. The method of claim 3 wherein the second signal is produced by
the steps of presetting a counter, counting the pulses from a pulse
source into the counter, and producing a pulse each time the
counter reaches a predetermined number.
7. The method of claim 3 which includes the steps of preloading a
first counter to a predetermined number, counting the pulses from a
pluse source into the first counter, producing an output pulse from
the first counter each time it is filled, and counting the output
pulses of the first counter with a further counter.
8. The method of claim 7 in which a first counter produces pulses
comprising the first pulse signal during one period of time and
pulses comprising the second pulse signal during another period of
time, and in which the first counter is preloaded during counting
of the pulses of the first pulse signal with a first predetermined
number and preloaded during counting of the pulses of the second
pulse signal with a second predetermined number which is dependent
upon the total count of the first pulse signal in the second
counter.
9. The method of claim 2 which includes the steps of counting the
pulses comprising the first pulse signal and counting the pulses
comprising the second pulse signal in accordance with a weight
dependent upon the total count of the first signal.
10. The method of claim 9 wherein the weights accorded the pulses
in counting are each powers of two.
11. A method of discriminating among coins with respect to
denomination and authenticity comprising the steps of
causing a coin to move at a velocity dependent upon the interaction
of the coin with a relatively moving magnetic field,
producing at least two values derived from at least two signals,
each signal being representative of a time necessary for the coin
to move a distance, at least one of the distances being dependent
upon the diameter of the coin being examiner,
comparing the values with each other, and
producing an output signal if the difference between the compared
values is within a predetermined range.
12. The method of claim 11 wherein first and second values are each
represented by first and a second electrical pulse signal,
respectively.
13. The method of claim 12 which includes the steps of counting the
pulses comprising the first pulse signal and establishing the pulse
rate of the second signal as a function of the total count of the
first signal.
14. The method of claim 13 which includes the steps of counting the
pulses of one pulse signal in a first counter, counting the pulses
of another pulse signal in a second counter, and comparing totals
of the counters.
15. The method of claim 13 which includes the steps of counting the
pulses of the first pulse signal in one direction into an up-down
counter, counting the pulses of the second pulse signal in the
opposite direction into that counter, and comparing the remainder
in the counter with a predetermined range.
16. The method of claim 13 wherein the second signal is produced by
the steps of presetting a counter, counting the pulses from a pulse
source into the counter, and producing a pulse each time the
counter reaches a predetermined number.
17. The method of claim 13 which includes the steps of preloading a
first counter to a prdetermined number, counting the pulses from a
pulse source into the first counter, producing an output pulse from
the first counter each time it is filled, and counting the output
pulses of the first counter with a further counter.
18. The method of claim 17 in which a first counter produces pulses
comprising the first pulse signal during one period of time and
pulses comprising the second pulse signal during another period of
time, and in which the first counter is preloaded during counting
of the pulses of the first pulse signal with a first predetermined
number and preloaded during counting of the pulses of the second
pulse signal with a second predetermined number which is dependent
upon the total count of the first signal in the second counter.
19. The method of claim 12 which includes the steps of counting the
pulses comprising the first pulse signal and counting the pulses
comprising the second pulse signal in accordance with a weight
dependent upon the total count of the first signal.
20. The method of claim 19 wherein the weights accorded the pulses
in counting are each powers of two.
21. The method of claim 11 which includes the steps of producing a
signal representing the duration of coin presence sensing by a
single sensor, and producing another signal representing the
duration of concurrent coin presence sensing by at least two
sensors.
22. The methodof claim 21 wherein first and second values are each
represented by a first and a second electrical pulse signal,
respectively.
23. The method of claim 22 which includes the steps of counting the
pulses comprising the first pulse signal and establishing the pulse
rate of the second pulse signal as a function of the total count of
the first pulse signal.
24. The method of claim 23 which includes the steps of counting the
pulses of one pulse signal in a first counter, counting the pulses
of another pulse signal in a second counter, and comparing totals
of the counters.
25. The method of claim 23 which includes the steps of counting the
pulses of the first pulse signal in one direction into an up-down
counter, counting the pulses of the second pulse signal in the
opposite direction into that counter, and comparing the remainder
in the counter with a predetermined range.
26. The method of claim 23 wherein the second pulse signal is
produced by the steps of presetting a counter, and producing a
pulse each time the counter reaches a predetermined number.
27. The method of claim 23 which includes the steps of preloading a
first counter to a predetermined number, counting the pulses from a
pulse source into the first counter, producing an output pulse from
the first counter each time it is filled, and counting the output
pulses of the first counter with a further counter.
28. The method of claim 27 in which a first counter produces pulses
comprising the first pulse signal during one period of time and
pulses comprising the second pulse signal during another period of
time, and in which the first counter is preloaded during counting
of the pulses of the first pulse signal with a first predetermined
number and preloaded during counting of the pulses of the second
pulse signal with a second predetermined number which is dependent
upon the total count of the first pulse signal by the second
counter.
29. The method of claim 22 which includes the steps of counting the
pulses comprising the first pulse signal and counting the pulses
comprising the second pulse signal in accordance with a weight
dependent upon the total count of the first pulse signal.
30. The method of claim 29 wherein the weights accorded the pulses
in counting are each powers of two.
31. The method of claim 11 which includes the steps of producing
one signal representing the duration of a period following the
sensing of coin presence by one sensor, during which neither that
sensor or a second sensor senses the presense of a coin and
producing another signal representing the duration of sensing of
coin presence by a single sensor.
32. The method of claim 31 wherein first and second values are each
represented by a first and a second electrical pulse signal,
respectively.
33. The method of claim 32 which includes the steps of counting the
pulses comprising the first pulse signal and establishing the pulse
rate of the the pulses pulse signal as a function of the total
count of the first pulse signal.
34. The method of claim 33 which includes the steps of counting the
pulses of one pulse signal in a first counter, counting the pulses
of another pulse signal in a second counter, and comparing totals
of the counters.
35. The method of claim 33 which includes the steps of counting the
pulses of the first pulse signal in one direction into an up-down
counter, counting the pulses of the second pulse signal in the
opposite direction into that counter, and comparing the remainder
in the counter with a predetermined range of values.
36. The method of claim 33 wherein the second pulse signal is
produced by the steps of presetting a counter, counting the pulses
from a pulse source into the counter, and producing a pulse each
time the counter reaches a predetermined number.
37. The method of claim 33 which includes the steps of preloading a
first counter to a predetermined number, counting the pulses from a
pulse source into the first counter, producing an output pulse from
the first counter each time it is filled, and counting the output
pulses of the first counter with a further counter.
38. The method of claim 37 in which a first counter produces pulses
comprising the first pulse signal during one period of time and
pulses comprising the second pulse signal during another period of
time, and in which the first counter is preloaded during counting
of the pulses of the first pulse signal with a first predetermined
number and preloaded during counting of the pulses of the second
pulse signal with a second predetermined number which is dependent
upon the total count of the first pulse signal in the second
counter.
39. The method of claim 32 which includes the steps of counting the
pulses comprising the first pulse signal and counting the pulses
comprising the second pulse signal in accordance with a weight
dependent upon the total count of the first pulse signal.
40. The method of claim 39 wherein the weights accorded the pulses
in counting are each powers of two.
41. A device for discriminating among coins with respect to
denomination, authenticity and the like comprising
means for examining a first characteristic of a coin, and
means for producing a first value which is a function of said first
characteristic,
means for examining a second characteristic of the coin, and
means for producing a second value which is a function of said
second characteristic,
a comparator connected to the means for producing the first value
and the means for producing the second value, which compares the
first value with the second value and produces an output signal
indicating whether the difference between the compared values is
within a predetermined range.
42. A device for discriminating among coins with respect to
denomination, authenticity and the like comprising
a pulse generator,
first means for examining a characteristic of a coin,
a first gate having inputs connected to receive signals from the
pulse generator and the first examining means,
second means for examining another characteristic of the coin,
a second gate having inputs connected to receive signals from the
pulse generator and the second examining means,
a first pulse counter connected to receive signals from the first
gate,
a second pulse counter connected to receive signals from the second
gate,
means for comparing the outputs of the first and second
counters.
43. The device of claim 42 wherein a single updown counter
comprises the first and second counters and the remainder is
compared with a predetermined tolerable range.
44. The device of claim 43 further comprising a logic circuit
connecting the inputs of two or more stages of the up-down counter
are each connected to an output of the third counter.
45. The device of claim 42 further comprising a third counter
interposed between one of the gates and the counter receiving
signals from that gate.
46. The device of claim 43 further comprising a third counter
interposed between one of the gates and the up-down counter.
47. The device of claim 46 further comprising a logic circuit
connecting the output of the third counter to an input of the
up-down counter.
48. The device of claim 45 further comprising a logic circuit
connecting an output of the third counter to an input of another
counter.
49. The device of claim 42 further comprising a logic circuit
connecting two or more inputs of the second counter are each
connected to an output of the third counter.
50. A device for discriminating among coins with respect to
denomination, authenticity and the like comprising
a coin passageway along which coins can pass,
a magnetic field generator producing a magnetic field in a region
of the passageway,
at least two coin presence sensors responsive to the passage of
coins in the passageway,
a pulse generator,
a logic circuit connected to two sensors and the pulse generator,
and
means for comparing two values produced by the logic circuit with
each other comprising
two pulse counters each connected to receive signals from an output
of the logic circuit.
51. The device of claim 50 wherein the two counters comprise a
single up-down counter and the value comparing means further
comprise a comparator for comparing the remainder in the up-down
counter with a predetermined range.
52. The device of claim 50 further comprising a further counter
interposed between the logic circuit and a counter.
53. The device of claim 52 further comprising a furthe logic
circuit connecting an output of the further counter to an input of
the counter.
54. The device of claim 52 wherein the inputs of two or more stages
of the counter are each connected to the output of the further
counter.
55. The device of claim 50 wherein the logic circuit comprises a
first subcircuit arranged to produce a signal representing the
duration of coin presence sensing by a single sensor, and a second
subcircuit arranged to produce a signal representing the concurrent
coin presence sensing by at least two sensors.
56. The device of claim 55 wherein the two counters comprise a
single up-down counter and further comprising a comparator for
comparing the remainder in the up-down counter with a predetermined
range.
57. The device of claim 55 further comprising a further counter
interposed between the logic circuit and a counter.
58. The device of claim 57 further comprising a further logic
circuit connecting an output of the further counter to an input of
the counter.
59. The device of claim 57 wherein the inputs of two or more stages
of the counter are each connected to the output of the further
counter.
60. The device of claim 50 wherein the logic circuit comprises
a first subcircuit arranged to produce a signal representing the
duration of a period in which neither of two sensors senses the
presence of a coin following the sensing of the presence of a coin
by one of the sensors; and
a second subcircuit arranged to produce another signal representing
the duration of coin presence sensing by a sensor.
61. The device of claim 60 wherein the two counters comprise a
single up-down counter and further comprising a comparator for
comparing the remainder in the up-down counter with a predetermined
range.
62. The device of claim 60 further comprising a further counter
interposed between the logic circuit and a counter.
63. The device of claim 62 further comprising a further logic
circuit connecting an output of the further counter to an input of
the counter.
64. The device of claim 62 wherein the inputs of two or more stages
of the counter are each connected to the output of the further
counter.
65. The method of claim 11 which includes the steps of producing a
signal representing the duration of coin presence sensing by a
single sensor, and producing another signal representing the
duration of coin presence sensing by at least one sensor while
another sensor is not sensing the presence of a coin.
66. The method of claim 65 wherein first and second values are each
represented by a first and a second electrical pulse signal,
respectively.
67. The method of claim 66 which includes the steps of counting the
pulses comprising the first pulse signal and establishing the pulse
rate of the second pulse signal as a function of the total count of
the first pulse signal.
68. The method of claim 67 which includes the steps of counting the
pulses of one pulse signal in a first counter, counting the pulses
of another pulse signal in a second counter, and comparing totals
of the counters.
69. The method of claim 67 which includes the steps of counting the
pulses of the first pulse signal in one direction into an up-down
counter, counting the pulses of the second pulse signal in the
opposite direction into that counter, and comparing the remainder
in the counter with a predetermined range.
70. The method of claim 67 wherein the second pulse signal is
produced by the steps of presetting a counter, and producing a
pulse each time the counter reaches a predetermined number.
71. The method of claim 67 which includes the steps of preloading a
first counter to a predetermined number, counting the pulses from a
pulse source into the first counter, producing an output pulse from
the first counter each time it is filled, and counting the output
pulses of the first counter with a further counter.
72. The methodof claim 71 in which a first counter produces pulses
comprising the first pulse signal during one period of time and
pulses comprising the second pulse signal during another period of
time, and in which the first counter is preloaded during counting
of the pulses of the first pulse signal with a first predetermined
number and preloaded during counting of the pulses of the second
pulse signal with a second predetermined number which is dependent
upon the total count of the first pulse signal by the second
counter.
73. The method of claim 66 which includes the steps of counting the
pulses comprising the first pulse signal and counting the pulses
comprising the second pulse signal in accordance with a weight
dependent upon the total count of the first pulse signal.
74. The method of claim 73 wherein the weights accorded the pulses
in counting are each powers of two.
75. The device of claim 50 wherein the logic circuit comprises a
first subcircuit arranged to produce a signal representing the
duration of coin presence sensing by a single sensor, and a second
subcircuit arranged to produce a signal representing the duration
of coin presence sensing by one sensor while another sensor does
not sense the presence of a coin.
76. The device of claim 75 wherein the two counters comprise a
single up-down counter and further comprising a comparator for
comparing the remainder in the up-down counter with a predetermined
range.
77. The device of claim 75 further comprising a further counter
interposed between the logic circuit and a counter.
78. The device of claim 77 further comprising a further logic
circuit connecting an output of the further counter to an input of
the counter.
79. The device of claim 77 wherein the inputs of two or more stages
of the counter are each connected to the output of the further
counter.
80. The method of claim 11 which includes the steps of producing a
signal representing the duration of concurrent coin presence
sensing by at least two sensors, and producing another signal
representing the duration of coin presence sensing by at least one
sensor while another sensor is not sensing the presence of a
coin.
81. The method of claim 80 wherein first and second values are each
represented by a first and a second electrical pulse signal,
respectively.
82. The method of claim 81 which includes the steps of counting the
pulses comprising the first pulse signal and establishing the pulse
rate of the second pulse signal as a function of the total count of
the first pulse signal.
83. The method of claim 82 which includes the steps of counting the
pulses of one pulse signal in a first counter, counting thepulses
of another pulse signal in a second counter, and comparing totals
of the counters.
84. The method of claim 82 which includes the steps of counting the
pulses of the first pulse signal in one direction into an up-down
counter, counting the pulses of the second pulse signal in the
opposite direction into that counter, and comparing the remainder
in the counter with a predetermined range.
85. The method of claim 82 wherein the second pulse signal is
produced by the steps of presetting a counter, and producing a
pulse each time the counter reaches a predetermined number.
86. The method of claim 82 which includes the steps of preloading a
first counter to a predetermined number, counting the pulses from a
pluse source into the first counter, producing an output pulse from
the first counter each time it is filled, and counting the output
pulses of the first counter with a further counter.
87. The method of claim 86 in which a first counter produces pulses
comprising the first pulse signal during one period of time and
pulses comprising the second pulse signal during another period of
time, and in which the first counter is preloaded during counting
of the pulses of the first pulse signal with a first predetermined
number and preloaded during counting of the pulses of the second
pulse signal with a second predetermined number which is dependent
upon the total count of the first pulse signal by the second
counter.
88. The method of claim 81 which includes the steps of counting the
pulses comprising the first pulse signal and counting the pulses
comprising the second pulse signal in accordance with a weight
dependent upon the total count of the first pulse signal.
89. The method of claim 88 wherein the weights accorded the pulses
in counting are each powers of two.
90. The device of claim 50 wherein the logic circuit comprises a
first subcircuit arranged to produce a signal representing the
concurrent coin presence sensing by at least two sensors, and a
second subcircuit arranged to produce a signal representing the
duration of coin presence sensing by one sensor while another
sensor does not sense the presence of a coin.
91. The device of claim 90 wherein the two counters comprise a
single up-down counter and further comprising a comparator for
comparing the remainder in the up-down counter with a predetermined
range.
92. The device of claim 90 further comprising a further counter
interposed between the logic circuit and a counter.
93. The device of claim 92 further comprising a further logic
circuit connecting an output of the further counter to an input of
the counter.
94. The device of claim 92 wherein the inputs of two or more stages
of the counter are each connected to the output of the further
counter.
Description
This invention relates to coin discrimination devices and, more
particularly, to a system for determining the denomination of coins
and for rejecting undesired coins, counterfeit coins and non-coin
objects.
Throughout this specification and in the appended claims, the term
"coin" is intended to mean genuine coins, tokens, counterfeit
coins, slugs, washers, and any other item which may be used by
persons in an attempt to use coin-operated devices. An acceptable
coin is an authentic coin of the monetary system in which the
device is intended to operate and of a denomination which the
device is intended selectively to receive for value.
It is one objective of this invention to provide a coin
discrimination device which will accurately and reliably
distinguish different denominations and which will reject
unacceptable coins.
Another object of this invention is to provide a coin
discrimination device having the capability of accepting a large
number of coin denominations.
Another objective of this invention is to reduce the number of
sensor device required in a coin discrimination device.
Another objective of this invention is to provide an electrical
signal representative of the denomination of each acceptable coin
for summation or actuation purposes.
SUMMARY
This invention is made in the context of the known concepts of
distinguishing among differing coins by measuring characteristics
dependent upon their physical dimensions, such as diameter, and
their acceptance ratios. The acceptance ratio is defined as the
ratio of the coin's electrical conductivity to its density.
This invention, in one form, utilizes the properties of the
diameter of a coin and the velocity of the coin, after it has been
subjected to a magnetic field, to determine its acceptability and
denomination. When an electrically conductive coin enters the
device, it is subjected to a relatively moving primary magnetic
field. The coin's motion relative to the primary magnetic field
induces eddy currents within the coin. The eddy currents produce
secondary magnetic fields which interact with the primary magnetic
field, producing a force on the coin. The effect of an electrically
conductive non-ferromagnetic coin passing through a stationary
magnetic field is the retardation of the velocity of the coin in an
amount primarily dependent upon the acceptance ratio of the coin. A
moving magnetic field, such as the impeller described below, may
accelerate or regulate the velocity of a coin. The coin's velocity,
when sensed downstream of the magnetic field, is a measure of coin
authenticity and denomination. One means of examination of the coin
velocity is a measurement dependent upon the time required for an
edge of the coin to pass between two points at which detectors or
sensors are located.
On means of measuring the diameter of a moving round or regular
polygonal coin is to measure the time required for the coin to pass
by a single sensor, providing a velocity dependent measurement of
the chord of the coin at the height of the sensor above the coin
support track. The chord of a coin can be measured in several other
velocity dependent ways described below, all of which are referred
to as chordal-velocity functions.
In one form of the present invention two signals are produced, each
the result of one of two measurements. One signal is representative
of a chordal-velocity function of the coin and one is
representative of coin velocity. During the time period of the
first measurement, a time dependent electrical signal such as
pulses from a pulse source or clock is accumulated in a register.
Based on a comparison of the number or value stored in the register
following the first measurement with ranges of values representing
various acceptable coin denominations a tentative determination can
be made regarding which, if any, denomination of acceptable coin is
being tested. During the time period of the second measurement,
pulses or values are counted or accumulated and stored in a second
register; the rate of change of the value of count stored in the
second register being dependent upon the result of the tentative
determination of coin denomination and instructions which are
programmed or built into the coin discriminator. If the coin is an
acceptable coin of the anticipated denomination, the total in that
second register after the second measurement will be within an
allowable range of the total stored in the first register. A signal
is then provided to accept the coin.
Comparison of the result of the first and second measurements in
this fashion in many cases permits the use of a more discriminating
range of tolerance for acceptable coins than other techniques.
An advantageous way of storing the count numbers is to use a single
up-down counter into which the number representative of the first
measurement is counted and stored. The pulses representative of the
second measurement are then used to reduce the number stored in the
up-down counter. When an acceptable coin of the denomination
indicated by the first measurement is tested, the number in the
counter following both measurements will be within the
predetermined acceptable tolerance of the starting value stored in
the counter, e.g.: zero plus or minus some tolerance number.
In the drawings:
FIG. 1 is a front elevational and schematic block diagram of a coin
discrimination device including a sensor array and electronic
circuit in accordance with the first embodiment of this
invention.
FIG. 2 is a front elevational diagram of the track and sensor array
of the coin discrimination device of FIG. 1, indicating the outline
of a typical coin at several positions.
FIG. 3a is a schematic block diagram of the two-bit counter and
logic circuit of the first embodiment.
FIG. 3b is a schematic block diagram of the lower stages of the
counter of the first embodiment.
FIG. 4 is a front elevational and schematic block diagram of a coin
discrimination device including a sensor array and electronic
circuit in accordance with the second embodiment.
FIG. 5 is a schematic block diagram of the divider and logic
circuit of the second embodiment.
FIG. 6 is a schematic illustration of a linear motor coin impeller
and coin sensors in accordance with the third embodiment.
FIG. 7 is a front elevational and schematic block diagram of a coin
discrimination device including a sensor array, electronic circuit
and a coin impeller in accordance with the third embodiment.
FIG. 8 is a schematic block diagram of an embodiment of a coin
discrimination device which provides a predicted ratio to be used
in determining coin authenticity and denomination.
It should be noted that the drawings are not intended to be
dimensionally proportionate or scale representations of the devices
illustrated. It will be clear to those skilled in the art, that,
whereas the invention has been described in terms of AND and OR
logic elements, alternative logical elements may be used without
departing from the invention. Similarly, the word signal has been
used in most cases to represent the relatively high output voltage
of certain devices having two output voltages but the invention is
not limited to the disclosed use of such signals.
First Embodiment
The coin discrimination device 10 is provided with an entrance slot
for admitting coins, which fall to one end of the track 16 forming
the bottom of a coin passage 15. An arresting pin 18 transverse of
the coin passage 15 prevents coins from moving on through the coin
passage 15 until it is removed.
It is often desirable to remove highly ferro-magnetic coins and
objects, not part of the monetary system, before they go further.
There are many coin scavengers known to the art which may be
located in the path of coin travel for this purpose, for example
the magnetic coin scavengers described in U. S. Pat. Nos. 1,956,066
and 3,168,180.
A coin presence sensor 21 is located in the vicinity of the
arresting pin 18 in a position to sense the presence of any
potentially acceptable coins stopped at the arresting pin. A
suitable coin presence sensor 21 is a phototransistor placed on the
one side of coin passage 15 opposite a source of light (not shown)
on the other side of the passage; so positioned that any coin 20 to
be further examined by the device will prevent light from passing
from the light source to the sensor 21, i.e.: the sensor 21 will be
obscured. An electrical signal from the sensor 21, representative
of whether or not the sensor 21 is obscured, is transmitted to the
start control 42. When the signal from the sensor 21 indicates that
a coin is present, the start control 42 activates a solenoid (not
shown) which retracts arrest pin 18 out of the way of the coin 20.
At the same time a signal is sent from the start control 42 on lead
174 to reset the counter 160 to its starting condition.
In the present embodiment, the track 16 is sloped approximately
5.degree. downwardly from horizontal in the direction away from the
entrance end having arrest pin 18. When the arrest pin 18 is moved
aside, the electrically conductive non-ferromagnetic coin 20 moves
down the track 16 under the force of gravity. A magnet 23 is
located at a point further down the coin passage 15 than the arrest
pin 18. Magnet 23 may be either a permanent magnet or an
electromagnet, having a magnetic field component transverse to coin
passage 15. As the coin 20 passes through the field from the magnet
23, the field induces eddy currents in a conductive coin which
currents in turn produce a magnetic force. The action of the
magnetic force between the coin 20 and the magnet 23 tends to slow
the coin in an amount dependent upon the acceptance ratio of the
coin. The velocity of a particular coin 20, having started from
rest at the arresting pin 18, as it leaves the influence of the
magnet 23 is primarily dependent upon the coin's acceptance
ratio.
In order to determine the authenticity and denomination of coins,
this embodiment relies upon two time related measurements,
correlation of the data for the two measurements and comparison
with data representative of the range of acceptable coins. While
this description speaks of measuring time, I prefer to indirectly
measure time by using electrical circuits which count pulses
emitted from pulse sources at known time intervals.
The acceptance ratio of the coin and the diameter or a chord of the
coin are two physical characteristics of the coin upon which the
time measured in this embodiment depend. The velocity of a
particular coin which has passed through the field magnet 23 is
dependent upon the acceptance ratio. The time measurements desired
are derived in coin discriminator 10 by occluding two coin presence
sensors 66 and 67 spaced apart and located along the coin passage
at a position where the coin velocity has been affected by coaction
of the field of magnet 23 and the secondary magnetic field
generated by eddy currents in the coin induced by motion in the
field of magnet 23. Since the position of the two coin presence
sensors 66 and 67 is fixed and known, the time between an event at
the first sensor 66 and an event at the second sensor 67 has a
linear dependence upon the average velocity of the coin during its
passage between them and is, therefore, a function of the coin's
acceptance ratio. For the purpose of this embodiment of the
invention, the coin presence sensors 66 and 67 are phototransistors
spaced apart in the direction of coin movement by a small enough
distance so that both sensors 66 and 67 can be in an occluded state
at the time (i.e.: concurrently occluded) from a light source (not
shown) on the other side of the coin passage 15 during the passage
of the smallest acceptable coin. A measurement of a function of the
acceptance ratio can then be made by measuring the length of time
that either one of the two sensors is occluded while the other
sensor is not occluded (AB or AB). A measurement of a function of
both acceptance ratio and chordal dimension of the coin can be made
either (1) by measuring the total time that either one of the
sensors is obscured (A or B) or (2) by measuring the total time
that both of the sensors are obscured (AB). Since there are but two
unknown variables, chordal dimension and velocity, any two of these
three measurements will provide sufficient data to determine the
characteristics of the coin. We prefer in this embodiment to first
measure the time AB during which both sensors are occluded and then
measure the period of time AB during which the second sensor 67(B)
is occluded while the first sensor 66(A) is not. Coin
discriminators may also be constructed in which the sensors are
located so that one or more acceptable coins can not concurrently
occlude both sensors, for which coins the duration of the time (AB
after A) in which neither sensor is occluded, after the first
sensor has been occluded and before the second sensor is occluded,
may be employed for the first measurement.
Assuming the sensors 66 and 67 are at the same height h above the
track 16, time AB is equal to the separation between the sensors
divided by the average velocity of the trailing edge of a coin
moving in the direction from sensor 66(A) to sensor 67(B). Time AB
is equal to the difference between a chord across the coin at the
height h of the sensors 66 and 67 above the track 16 and the
separation between the sensors, divided by the average velocity V
of the coin during the measurement period. Mathematically, these
two times may be expressed:
AB = (C-S)/V and AB =S/V,
where S is the sensor spacing in the direction parallel to coin
track 16, V is the coin's velocity and C is the chord length of the
coin at the height h of the sensors 66 and 67 above the track, as
indicated in FIG. 2. Sensors at two different heights can also be
employed, in which case the time expressions can be easily
calculated; for example AB = (C.sub.1 + C.sub.2 - 2S)/2V where
C.sub.1 and C.sub.2 are the lengths of chords parallel to the track
at sensor heights h.sub.1 and h.sub.2 respectively.
In FIG. 2, a coin moving toward the right in the figure on the
track 16 past sensors 66 and 67 is shown by dashed outlines. The
first coin outline 1 indicates the position of the coin at the
beginning of period AB, the second outline 2 at the end of period
AB, which is also the beginning of period AB, and the third outline
3 at the end of period AB.
When the first test or measurement of AB is completed, a tentative
determination of the coin's denomination and authenticity is made.
Subsequent tests then can be limited to the verification of
authenticity and denomination with respect to the tentatively
determined coin denomination or denominations.
If the result of the two tests are represented as quanta, such as
numbers which can be stored in a counter; then the authenticity of
a given denomination coin can be represented by a number, e.g.: the
result of the first test, and a ratio of the two test results. In
this embodiment, an up-down counter with provision for counting
down at any of several powers of 2 is used. During the first time
period AB, the amount in the counter is counted in one direction,
up, at a fixed power of 2 as each pulse is received by the counter.
During the second time period AB, the amount in the counter is
counted in the other direction, down, as each pulse is received at
a cyclical power of two, i.e. a predetermined sequence or cycle of
powers of two as described below. The particular cycle of powers of
two on successive counts is selected at the end of the first test
with the expectation of producing a negligible positive or negative
remainder for an authentic coin of the tentatively determined
denomination.
The chord C along the line between the sensors is given by
C = .sqroot.4(D-h)h
where D is the coin diameter and h is the height of sensors 66 and
67 above the track 16. The several coin diameters are dictated by
the currency, but the choice of appropriate sensor height h is of
the device designer's chosing. For a three- or four-coin set it is
possible to select a height h such that the chord lengths for the
various coins will be nearly in an integral ratio to each other;
the work "nearly" being used to indicate that most of the deviation
from an exact integral ratio is attributable to the range of coin
diameters which must be accepted to accommodate coin wear.
To ensure that success of the up-down counting technique, the
spacing S between sensors 66 and 67 and the rate at which the
number in the counter is increased during time period AB should be
chosen so that the separations between sensors can be chosen to be
multiples of 16 units on the scale of units in which the chord
lengths of the several denominations are expressible as near
integers.
If the sensor spacing S is taken as 16 units, and the chord length
C of three coin denominations X, Y and Z are 32, 37 and 45 units
respectively; then the chord length less sensor spacing (C-S) for
coins X, Y and Z will be 16, 21 and 29 respectively and the ratios
between first and second tests at a constant velocity V will be
16/16 = 1, 21/16 and 29/16 respectively. If in each given equal
unit of time during the time period AB of the first test, the
number in the counter is increased by 2.sup.4 = 16, then the cycle
of powers of two for counting down during each such unit of time
may be as follows:
AMOUNT COUNTED DOWN Tentatively Identified Cycle Step Number
Denomination 1 2 3 4 Total Count X 2.sup.2 2.sup.2 2.sup.2 2.sup.2
16 Y 2.sup.3 2.sup.2 2.sup.3 2.sup.0 21 Z 2.sup.4 2.sup.0 2.sup.3
2.sup.2 29
when the coin being examined has been tentatively identified at the
conclusion of the first test as a coin of denomination X; each time
a pusle is received during the period of the second test, the
amount in the counter is counted down by 2.sup.2 or four units
since each of the cycle steps are the same. When the coin is
tentatively identified as being of denomination Y, the amount in
the counter is reduced by 2.sup.3 or eight units for the first
pulse received, then four, then eight and then one unit for
successive pulses. The cycle is then repeated for succeeding
pulses. The effect of this four-step cycle of varying powers of two
is to apply an average weight, dependent upon the result of the
first test, to the pulses counted in the second test.
Referring to the diagram of FIGS. 1 and 3a, either when both
sensors 66 and 67 are not obscured, or when only sensor 66 is not
obscured, AND gates 33 and 34 do not produce any output signal.
When both sensors 66 and 67 are obscured, however, signals for
inverters 31 and 32 are applied to both inputs of AND gate 33 which
therefore provides an output signal, identified here as AB. This
output is applied to the one input of AND gate 35 and clock pulses
from clock 40 are applied to the other input of AND gate 35. The
output of AND gate 35 on lead 45 is a stream of clock pulses,
identified here as ab, continuing for the entire period that both
sensors 66 and 67 are occluded. These pulses ab are applied
directly to the 2.sup.2 stage 163 of the binary up-down counter 160
through OR gate 132. Signal AB is simultaneously applied to the "up
count" input lead 175 of the counter 160. As a result, each clock
pulse during the period when both sensors 66 and 67 are obscured
causes the number stored in the counter to increase by a factor
2.sup.2.
Each of the upper stages 166 through 171 of the counter is
connected to both of the decoders 180 and 190. The first decoder
180 is used in connection with the measurement of the duration of
occlusion of both sensors 66 and 67. Whenever the number stored in
the upper stages 166 through 171 of the counter 160 is equal to the
number for an acceptable coin of given denomination X, Y and Z
within the prescribed tolerance, flip-flops 182, 184 or 186 is set
respectively. The corresponding flip-flop 183, 185 or 187, however,
is not set unless signal AB from AND gate 33 is removed from the
reset inputs of flip-flops 183, 185 and 187 while the associated
flip-flops 182, 184 and 186 is producing an output signal. When the
signal AB is removed from the reset of the flip-flops 183, 185 and
187 while a signal is applied to the set input of one of those
flip-flops, that flip-flop is set thereby recording that the coin
tested has satisfied the first test for its associated denomination
coin.
As soon as sensor 66 is no longer occluded, AND gate 33 is no
longer activated and signals AB and ab cease. AT the same time, AND
gate 34 is activated by the application to its inputs of the signal
from sensor 66 and the signal from sensor 67 which has been
inverted by inverter 32. The output signal AB from AND gate 34 and
the output signal of clock 40 are applied to the inputs of AND gate
36 which then delivers a stream of clock pulses ab on lead 46 for
the entire period when sensor 66 is not occluded and sensor 67 is
occluded.
The pulses ab from AND gate 36 are applied to the input of the
two-bit counter 100, which is described in greater detail below.
The two-bit counter 100 is one which directs one of the pulses ab
to each of the four output leads 111, 112, 113 and 114 in
succession. These leads 111 through 114 are connected to logic
circuit 120. The outputs of flip-flops 183, 185 and 187 are also
connected to logic circuit 120 by leads 181, 188 and 189,
respectively. The logic circuit is composed of AND and OR gates
which direct the pulses from the two-bit counter to one or another
of the lower stages 161 through 165 of counter 160, the particular
scheme for directing the pulses depending on which of the
flip-flops 183, 185 or 187 is supplying a signal to the logic
circuit 120. Details of the logic circuit 120 are described
below.
Signal AB is applied to the "down-count" input lead 176 of the
counter 160 simultaneously with the pulses from logic circuit 120.
As a result, the pulses from the logic circuit 120 reduce the
number stored in the counter 160. The logic circuit 120 is designed
so that when the coin tested in an acceptable coin of the
denomination indicated by the output of one of flip-flops 183, 185
and 187, set at the conclusion of the first test; at the conclusion
of the second test the remainder stored in the counter 160 for an
acceptable coin will be within a relatively small tolerance of the
number stored at the start, zero in this example, Decoder 190
decodes the output of the upper stages 166 through 171 of the
counter 160, and produces an output signal when the binary numbers
stored in all of those stages is the same -- either all 0's or all
1's. In that case, of course, the number stored in the counter is
zero within the tolerance of the maximum number, here 31 counts,
which can be stored in the lower stages 161 and 165 of the counter
160. Different tolerances can be obtained by changes in which are
decoded. For example, if stage 165 is also decoded the tolerance
would be 15 counts, or alternatively if stage 166 is not decoded
the tolerance would be 63 counts. By suitable arrangements of gates
between outputs of the counter 160 and the second decoder 190, it
is possible to obtain intermediate tolerances. Similar means may be
employed in conjunction with the output signals from the flip-flops
183, 185 and 187 to provide for different tolerances for different
denomination coins.
When decoder 190 produces an output signal setting flip-flop 191
which applies a signal to the input of AND gates 192, 194 and 196.
One of these gates is also receiving an input signal from its
respective flip-flop 183, 185 and 187. That AND gate will then
produce an output signal. The outputs of the AND gates 192, 194 and
196 are connected respectively to the set inputs of flip-flops 193,
195 and 197. The reset input of these flip-flops is connected to
the output of AND gate 34 which supplies signal AB the duration of
the period when sensor 66 is not occluded while sensor 67 is
occluded. If signal AB is applied to the reset input of the
flip-flops 193, 195 and 197 when one of those flip-flops receives a
set input signal from its respective AND gate 192, 194 and 196
respectively, the flip-flop will not be set. If, however, signal AB
is not being applied to the reset input when such a signal is
applied to the set input, the flip-flop will be set, indicating
that the coin tested has passed both tests for a coin of the
denomination associated with the flip-flop.
The outputs of flip-flops 193, 195 and 197 actuate the accumulator
circuit 200, which accounts for the value of the coin examined and
actuates the coin operated device 210 when coins summing to a
predetermined total value have been examined and found
acceptable
FIG. 3a shows details of a two-bit counter 100 and a logic circuit
120 for this embodiment of the invention. Two-bit counter receives
pulses ab on lead 46 from AND gate 36 at the input of the flip-flop
101. When the first pulse is received after the flip-flop has been
reset, a pulse is produced at the output terminal connected to the
inputs of flip-flop 102 and AND gates 105 and 106. Similarly,
flip-flop 102 produces an pulse at the output terminal connected to
AND gate 106. The coincidence of pulses on the two inputs of AND
gate 106 activates the gate and a pulse appears at its output. The
next pulse received by flip-flop 101 causes a pulse to appear on
its other output, which is connected to AND gates 103 and 104.
Flip-flop 102 remains set a before, therefore a coincidence occurs
on the inputs of AND gate 104. The third pulse received by
flip-flop 101, causes a pulse to appear again on the first output
terminal. Flip-flop 102 is thereby caused to produce a pulse on its
output terminal connected to AND gates 105 and 103. Since a
coincidence occurs on the input terminals of AND gate 105, a pulse
appears at its output. When the fourth pulse appears at the input
of flip-flop 101, an output pulse is produced at its second output
terminal. Flip-flop 102 remains in the same state as on the
previous pulse. There being a coincidence at the inputs of AND gate
103, a pulse appears at its output. The fifth input pulse restarts
the cycle, and therefore causes a pulse to appear at the output of
AND gate 106.
Logic circuit 120 "weights" the pulses during the period of the
second measurement by directing them to the various stages of the
up-down counter 160. One of the leads 181, 188 and 189 brings to
the logic circuit 120 the signal identifying the possible
denomination of the coin being tested from flip-flops 183, 185 and
187. When, for example, a signal appears on lead 189, AND gates
126, 127, 128 and 129 can pass pulses coming from AND gates 106,
104, 105 and 103 respectively of two bit counter 100. AND gates
126, 127, 128 and 129 are connected with OR gates 134, 130, 133 and
132 respectively, in accordance with a scheme which will produce a
total change of 29 in the number stored in the counter 160 during
the period of four input pulses to the two-bit counter 100. The
output of AND gate 126 is connected to an input of OR gate 134,
which in turn is connected to the 2.sup.4 stage 165 of the counter
160. The output of AND gate 127 is connected to the input of OR
gate 130 which in turn is connected to the 2.sup.0 stage 161. The
output of AND gate 128 is connected to the input of OR gate 133
which in turn is connected to 2.sup.3 stage 164. The output of AND
gate 129 is connected to the input of OR gate 132, which in turn is
connected to 2.sup.2 stage 163.
Similarly, when lead 188 carries a signal from the output of
flip-flop 185, AND gates 122, 123, 124 and 125 can be activated by
pulses from the two-bit counter 100. These gates will then direct
the pulses to OR gates 133, 132, 133 and 130 respectively; which in
turn transmit the pulses to counter lower stages 164, 163, 164 and
161 respectively, changing the number stored in the counter by a
total of 21 for every four pulses applied to the input of the
two-bit counter 100.
In the event that the desired countdown number is the same as the
count-up number, the two-bit counter may be bypassed and a single
AND gate 121 will suffice to connect the ab pulses to the
appropriate OR gate 132, when a signal appears on lead 181, and
thence to the corresponding stage 163 of the counter 160.
The lower stages 161, 162, 163 and part of 164 of counter 160 are
shown in greater detail in FIG. 3b, to illustrate up-down counter
means having stages with parallel inputs. Assume that initially all
of the flip-flops 411 421, 431 and 441 shown here have been reset
to the "zero" state, i.e.: that output leads 417, 427, 437 and 447
each has a relatively high voltage relative to the other output
leads 416, 426, 436 and 446 of the same flip-flops; in other words,
that the counter has stored the binary number 0000. When a
continuous signal is applied to the up-lead 175 and concurrently a
pulse is applied to logic circuit output lead 135, the state of
flip-flop 411 changes to a "one" and its output signal now appears
on lead 416. Since none of the up AND gates 422, 432 and 442 or the
down AND gates 423, 433 and 443 is activated, none of the other
flip-flops 421, 431 and 441 is activated and able to be triggered;
although the pulse is applied to the trigger input of each via OR
gates 420, 430 and 440. The simultaneous application of signals
from leads 175 and 416 on the inputs to AND gate 422 causes it to
transmit a signal to AND gate 432 and via OR gate 424 to the
activating gates of flip-flop 421 in the next higher counter stage
162. If another pulse then appeared on lead 135, it would trigger
flip-flop 411 directly and be able to trigger flip-flop 421 via OR
gate 420. AND gate 422 would no longer be activated and therefore
flip-flop 421 would not be triggered by the next subsequent pulse
on lead 135. It will be clear to those skilled in the art that
during up-counting each higher stage is activated by AND gates in
the group of gates 422, 432 and 442 so as to be triggered by the
next pulse when all lower stages are in the "one" state; and that
downcounting operates in a similar fashion, utilizing the downcount
signal on lead 176, the down AND gates 423, 433 and 443, and the
flip-flop output leads 417, 427 and 437. It will also be readily
apparent from FIG. 5 that signals applied to lead 136 operate in
the same fashion as signals applied to lead 135; however, signals
on lead 136 can affect only the state of stage 162 and higher
stages, and that the same holds true for leads 137 and 138 with
respect to stages 163 and 164, respectively, as a result of the
series of OR gates 420, 430 and 440.
Second Embodiment (FIGS. 4 and 5)
The coin discriminator 300 comprising a second embodiment of this
invention is similar to the coin discriminator 10 of the first
embodiment described above in that the criteria used for accepting
and categorizing coins of predetermined denomination are the same
and a related combinatorial circuit is utilized. The movements of
the coin being examined by the coin discriminator 300 of this
embodiment are the same as in the case of the coin discriminator 10
of the first embodiment, and the operation and location of the
sensors 66 and 67 of the coin discriminator are also the same.
Where the same number is employed to describe an element of two
different embodiments of this invention, the element described is
the same in both embodiments.
When either both sensors 66 and 67 are not obscured, or when only
sensor 66 is not obscured, AND gates 33 and 34 do not produce any
output signal. When both sensors 66 and 67 are obscured, however,
signals from inverters 31 and 32 are applied to both inputs of AND
gate 33 which therefore provides an output signal on lead 37,
identified here as AB.
As soon as sensor 66 is no longer occluded, AND gate 33 is no
longer activated and signal AB ceases. At the same time, AND gate
34 is activated by the application to its inputs of the signal from
sensor 66 and the signal from sensor 67 which has been inverted by
inverter 32. The output signal AB on lead 38 from AND gate 34 is
then produced for the entire period when sensor 66 is not occluded
and sensor 67 is occluded.
Referring now to FIG. 5, throughout the period of coin examination
clock pulses flow at a predetermined, fixed rate through lead 341
from the pulse generator or clock 340 (shown in FIG. 4) to the
divider 310. A divider 310 suitable for this embodiment is a chain
of flip-flops 321, 322, 323, 324 and 325. Clock pulses from lead
341 are applied to the input of the first flip-flop 321, producing
pulses alternatively on its two outputs. One output of flip-flop
321 is connected to divider output lead 311 and the other to the
input of flip-flop 322. Similarly, the one output of flip-flop 322
is connected to the output lead 312 and the other to the input of
flip-flop 323; one output of flip-flop 323 is connected to output
lead 313 and the other to the input of flip-flop 324; and one
output of flip-flop 324 is connected to output lead 314 and the
other to the input of flip-flop 325. One output of flip-flop 325 is
connected to output lead 315 and the other is unused. As a result
2.sup.4, 2.sup.3, 2.sup.2, 2.sup.1 and 2.sup.0 non-coincident
pulses appear on divider output leads 311, 312, 313, 314 and 315,
respectively, for every 2.sup.5 pulses applied to the input of
flip-flop 311.
The output signal AB on lead 37 is applied to an input of OR gate
350 of the logic circuit 320. The AND gates 331 through 338 of the
logic circuit 320 comprise a matrix for gating on pulses from the
divider 310 when signals are received at the output of OR gate 350
or on lead 188 or lead 189. The outputs of AND gates 331 through
338 are all connected to the inputs of OR gate 355.
The signal at the output of OR gate 350 is applied to the one input
and pulses from divider output lead 311 are applied to the other
input of AND gate 331. The output of AND gate 331 is a stream of
2.sup.4 pulses (16 in decimal notation) for every 2.sup.5 clock
pulses for the duration of signal AB. Since there are no input
signals on lead 188 and 189, as will later be apparent, the pulses
on logic circuit output lead 356 from OR gate 355 appear at the
same rate as the pulses from AND gate 331. These pulses are applied
directly to the pulse input of the binary up-down counter 360.
Signal AB is simultaneously applied to the "up count" input lead
175 of the counter 360. As a result, for every 2.sup.5 clock pulses
during the period when both sensors 66 and 67 are obscured causes
the number stored in the counter to increase by 2.sup.4.
Each of the upper stages 366 through 371 of the counter is
connected to both of the decoders 180 and 190. The first decoder
180 is used in connection with the measurement of the duration of
occlusion of both sensors 66 and 67. Whenever the number stored in
the upper stages 366 through 371 of the counter 360 is equal to the
number for an acceptable coin of given denomination X, Y or Z
within the prescribed tolerance, flip-flops 182, 184 or 186 is set
respectively. The corresponding flip-flop 183, 185 or 187, however,
is not set unless signal AB from AND gate 33 is removed from the
reset inputs of flip-flops 183, 185 and 187 while its associated
flip-flop 182, 184 or 186 is producing an output signal. When the
signal AB is removed from the reset of the flip-flops 183, 185 and
187 while a signal is applied to the set input of one of those
flip-flops, that flip-flop is set thereby recording that the coin
tested has satisfied the first test for the indicated denomination
coin.
When AND gate 34 is activated by the application to its inputs of
the signal from sensor 66 and the signal from sensor 67 which has
been inverted by inverter 32; the output signal AB on lead 38 is
applied via lead 176 to the down-count terminal of up-down counter
360, causing the counter 360 to count down on subsequent pulses
received from logic circuit 320 on lead 356.
In the event that the first measurement was acceptable for one of
the coins X,Y or Z, one of the leads 181, 188 or 189 will carry a
signal indicative of potential acceptability of a coin of the type
which it is associated.
The signals on each of the leads 181, 188 and 189 is connected to
certain of the AND gates 331 through 338, directly in the case of
leads 188 and 189 and indirectly via OR gate 350 in the case of
lead 181; the particular locations of the AND gates in the matrix
having been chosen to produce the desired ratio of pulses per unit
time during the second measurement to those during the second
measurement to those during the first measurement. When a signal
indicative of coin X appears on lead 181, AND gate 331 is activated
and 2.sup.4 pulses (16 pulses) for every unit of time represented
by 2.sup.5 clock pulses appear at its output and are directed via
OR gate 355 and lead 356 to the pulse input of up-down counter 360.
When a signal indicative of coin Y appears on lead 188, AND gates
332, 333 and 334 are activated, gating on non-coincident pulses at
rates of 2.sup.4, 2.sup.2 and 2.sup.0 per unit time respectively;
producing 21 pulses per unit time which are similarly directed to
counter 360. When a signal indicative of coin Z appears on lead
189, AND gates 335, 336, 337 and 338 are activated, gating on
non-coincident pulses at rates of 2.sup.4, 2.sup.3, 2.sup.2 and
2.sup.0 respectively; producing 29 pulses per unit time which are
similarly directed to counter 360. In the event that no signal is
applied to leads 181, 188 and 189 during the period of signal AB,
indicating that the coin being examined was not determined to be
potentially of denomination X, Y or Z in the first measurement; no
pulses are directed to counter 360 by logic circuit 320 during this
period.
The logic circuit 320 is designed so that at the conclusion of the
second test the remainder stored in the counter 360 will be within
a relatively small tolerance of the number stored at the start of
the first test, zero in this example, when the coin tested is an
acceptable coin of the denomination indicated by the output of one
of flip-flops 183, 184, and 185 which was set at the conclusion of
the first test. The decoder 190 and subsequent stages of the coin
discriminator 300 of this embodiment are the same as the
corresponding elements of the coin sensor 10 of the first
embodiment, and their operation is the same.
Third Embodiment
The coin discrimination device of this invention places coin
sensors in or following a region of coin acceleration or
deceleration. This third embodiment employs a linear motor or
impeller 480 to produce an apparently moving magnetic field which
is used to accelerate the non-magnetic, electrically conductive
coins with which the device is used. The linear motor or impeller
480 is similar to a stator of a conventional cylindrical electric
motor which has been cut along a radial plane and rolled out flat.
As is illustrated in FIG. 6, such an impeller 480 comprises two
series of coils, a first series including coils 482 and 484 and a
second series including coils 486 and 488. While only two coils per
series are illustrated, a greater number of coils is preferred, for
example, about four per series. The coils are wound around a low
carbon steel impeller core 490 having projecting pole pieces or
core fingers 492 through 495 spaced longitudinally along the
desired direction of coin travel. A low reluctance magnetic shunt
or magnetic return path 498 is placed at the side of the coin track
499 opposite the impeller 480 to provide a uniform magnetic field
across the coin passageway. The magnetic shunt may be made of a low
carbon steel plate.
In order to produce a traveling magnetic field, it is necessary for
adjacent fields to have a phase shift relationship. FIG. 6
illustrates a circuit which is suitable for providing approximately
a 90.degree. phase shift between adjacent core fingers. It can be
seen that the first series of coils 482, 484 is wound in
alternating fashion, in other words, coil 482 is wound in a
counterclockwise direction about core finger 492 while coil 484 is
wound clockwise about core finger 494. The second series of coils
486, 488 similarly is wound in alternating fashion, namely coil 486
is wound counterclockwise about core finger 495.
Either the first series or the second series of coils can be
individually selectively connected directly to a source of
cyclically varying current, for example, chopped D.C. or single
phase sinusoidal A.C. current source 500, such as by AND gate 502
and AND gate 504 respectively, which are controlled by signals from
start control circuit 506. The two series are connected in parallel
through a capacitor 508 thus placing the capacitor in series with
the coil series not directly gated on. The capacitor 508 provides a
90.degree. phase shift between the two series of coils. Because of
the reversed direction of windings of adjacent coils within a
series and the phase shift between the coil series provided by the
capacitor 508, the magnetic field is effectively traveling in one
direction. For example, at one instant of time assuming the
polarity of the first coil 482 is north, the polarity of coil 486
is north plus 90.degree., the polarity of coil 484 is south and the
polarity of coil 488 is south plus 90.degree.. The thrust direction
of impeller 480 is reversed by merely enabling the presently
disabled AND gate and vice versa. This permits selection of a
desired thrust direction for purposes described below.
To provide consistent coin tests, it is preferable to activate the
impeller 480 each time at the same fixed point in the impeller
current wave form. In this way the resultant coil acceleration and
velocity is not dependent upon the particular moment of time when
the coin is first exposed to the magnetic field of the impeller.
The zero crossing detector 509 is designed to detect the zero
crossing of the impeller current in the direction providing desired
initial polarity. The zero crossing detector 509 includes a
saturation amplifier, a diode and differentiator to select the
desired direction of transition and a latching relay operated by
the output of the differentiator.
Turning now to FIG. 7, a coin selector system 510 particularly
suitable for electrically conductive, nonferromagnetic coins,
utilizing a linear motor impeller 480, is schematically
illustrated. A coin entering the system through an entrance slot
512 drops vertically downward through an entrance meander section
514 which slows the coin and removes most of its energy. The coin
passes an arrival sensor 516 such as a photocell which senses the
presence of the coin in the system and, through an amplifier 518,
energizes a start control system 520 which, in turn, energizes the
impeller 480 after a slight delay. After passing the arrival sensor
516 the coin drops onto a coin support track 522. The support track
is designated with an initial short section 524 having an inclined
slope of between 0.5.degree. - 5.0.degree., preferably
approximately 1.5.degree., followed by a declining longer portion
having a declination of approximately the same slope. The coin
drops onto the initial portion 524 and, due to the inclination,
rolls rearwardly (toward the left in FIG. 7) until it comes to rest
against a wall 528. The system is designed with a delay in
energizing the impeller such that the impeller is energized after
sufficient time has elapsed for the coin to come to rest against
the wall 528. The impeller is located with respect to the track 522
such that portions of at least two pole faces are adjacent the
resting place of the smallest coin desired to be accepted by the
coin selector. Once the impeller is energized, the coin, if
electrically conductive and nonferromagnetic, will be caused to
move along the track 522 by rolling up the inclining portion 524
and then down the declining portion 526. The coin movement is
produced by eddy current induced in the coin which produces an
associated magnetic field. The induced coin voltage is time
derivative which causes the coin's magnetic field to have
approximately a 90.degree. lagging phase shift resulting in an
attraction between the forwardly adjacent coil and the coin which
causes the coin to move toward that coil. The rate of acceleration
of the coin and its velocity as it leaves the impeller 480 is
determined by the coin's acceptance ratio for the reasons discussed
above.
While a suitable application for the coin discrimination device of
this invention would be to use it with sensors positioned to sense
coins after leaving the impeller 480, in this embodiment the
sensors are located within the accelerating region of the impeller
480. In this discussion two spaced photosensitive devices 532 and
533 are used as sensors. A single source of collimated light (not
shown) is located on the opposite side of the track 522 from the
sensors 532 and 533, which are located within pole pieces 494 and
495 of the impeller 480. The sensors 532 and 533 are connected to
electronic circuit 550, which may be the circuitry following the
sensors other than the arrival sensors disclosed in any of the
previous embodiments.
This embodiment applies the same sensing and counting techniques
and devices as the first two embodiments; however, when the sensors
532 and 533 are located within the region of acceleration or
deceleration, the simpler formulae described with respect to the
earlier embodiments are not applicable. The optimum sensor
positions and ratios between the count numbers of the first and
second tests are, therefore, most easily determined
empirically.
A useful variation of the coin selector employing means to
accelerate coins, such as an impeller, can be constructed with only
one sensor in the coin examining system. The impeller accelerates
the coin in a manner deendent upon the coin's properties from a
known velocity at a known position, for example, resting against a
wall on a track, similar to wall 528 and track 522 in FIG. 7, so
that the coin moves along the track and past a sensor which, for
example, may be located in the position of sensor 532 or sensor
533. The duration of two periods, the one dependent at least upon
the coin's average velocity between the starting point and the
sensor and the other dependent upon a chordal velocity function may
be employed with any of the circuit techniques previously described
to identify genuine coins of permissible denominations. The period
of time from the start of acceleration of the coin from rest to the
first occlusion of the sensor and the period of occlusion of the
sensor are particularly suitable for this purpose.
As an alternative to turning off the impeller after a given number
of cycles, the impeller force can be reversed at that time to apply
a decelerating force on the coin for a further fixed period of
time. This latter technique can be used to provide an even greater
separation between coins of differing characteristics, such as
denomination and authenticity.
Fourth Embodiment
The coin discriminator 600 comprising a fourth embodiment of the
present invention is illustrated in FIG. 8. Where the same number
is employed to describe an element of this embodiment as was used
with a previous embodiment, the element is the same in both
embodiments.
Throughout the period of coin examination clock pulses flow at a
predetermined, fixed rate, e.g., at a frequency of 3 MHz, from the
pulse generator or clock 640 through lead 641 to a counter, six-bit
counter 610, i.e., a counter having a capacity of six-bits which is
equivalent to a count of 64 in decimal notation. The output pulses
which are produced by the six-bit counter 610 when it is filled to
its capacity are applied to the unit input 661 of an up-down
counter 660.
During the time period when the up-down counter 660 is counting up,
the six-bit counter 610 is initially preset to a predetermined
number, in this example 30, by conventional logic circuitry 620. 34
additional clock pulses can then be counted by the counter before
an output pulse is produced. The output pulse or overflow from the
six-bit counter 610 is the input to the up-down counter 660. At
overflow the six-bit counter 610 is automatically cleared and is
preset to 30 by signals on leads 611-616 from logic circuitry 620
and further counting proceeds. Thus, the content of the up-down
counter 660 at the end of the counting up period will be 1/(64-30)
or 1/34 of the number of 3 MHz pulses fed to the six-bit counter
610.
The content or count in the up-down counter 660 at the end of the
counting up period tentatively identifies the coin and thus
establishes the predicted ratio of the section time interval
T.sub.2 (counting down) to the first time interval T.sub.1
(counting up). This predicted ratio for the coin determines the
quantity with which the six-bit counter 610 is preset or preloaded
by logic circuitry 620 each time it overflows during the period of
counting down. For example, if the nominal value of T.sub.1 for a
given coin denomination is 0.68 second and T.sub.2 is 0.90 second,
and the preset during up counting is 30; then the expected ratio
for that denomination is T.sub.1 /T.sub.2 = 34/45. Since
approximately the same number of pulses must be supplied to the
up-down counter during up and down counting if the coin is to be
accepted, the preset or preload of the six-bit counter is used to
compensate for the difference in the number of pulses supplied by
the clock 640 in the two periods. Since the preload during the
period of counting up was 64-34=30; the preload during counting
down should be 64-45=19. The authenticity and denomination of the
coin is established if the content of the up-down counter 660 is at
or near the value at the start of counting up, typically zero, at
the end of the counting down period.
The signals for clearing the up-down counter 660 and defining the
counting up period and the counting down period are fed into the
up-down counter 660 by lead lines 37, 178 and 38, 176 as previously
described. Lead 37a feeds a signal to logic circuitry 620 to cause
presetting of the six-bit counter 610 to the desired preset during
the first time interval or counting up period, e.g.: 32. During the
second time interval or counting-down period, a signal on one of
leads 181, 188 or 189 causes presetting of the six-bit counter to
the desired preset for that period; the particular lead 181, 188 or
189 which is activated and the preset thereby established depending
on the tentative determination at the end of the counting-up
period.
At the conclusion of each counting period, the content of the
up-down counter 660 is transmitted to the decoders 180 and 190
where the content is compared with expected values. The operation
and construction of decoders 180 and 190 and the following
circuitry is as previously described in connection with FIGS. 1 and
4.
* * * * *