U.S. patent number 3,731,271 [Application Number 05/202,536] was granted by the patent office on 1973-05-01 for traffic signal control system.
This patent grant is currently assigned to Omron Tateisi. Invention is credited to Tadao Endo, Akira Muramatu.
United States Patent |
3,731,271 |
Muramatu , et al. |
May 1, 1973 |
**Please see images for:
( Certificate of Correction ) ** |
TRAFFIC SIGNAL CONTROL SYSTEM
Abstract
A relatively wide area in which the traffic signals are to be
controlled is divided into a plurality of local areas each having a
local signal controller. There are provided a plurality of
different cycle signals and a plurality of different synchronizing
signals paired with the cycle signals. A master controller always
watches the traffic condition in each of the local areas and causes
each local controller to select that one of the pairs of cycle
signals and synchronizing signals which is most suitable for
control of the traffic signals in each local area under the present
traffic conditions. In turn, each local controller uses the
selected cycle and synchronizing signal to control a plurality of
intersection controllers in the local area, each intersection
controller being associated with an intersection traffic
signal.
Inventors: |
Muramatu; Akira (Osaka,
JA), Endo; Tadao (Kyoto, JA) |
Assignee: |
Omron Tateisi (Kyoto,
JA)
|
Family
ID: |
22750295 |
Appl.
No.: |
05/202,536 |
Filed: |
November 26, 1971 |
Related U.S. Patent Documents
|
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
Issue Date |
|
|
828645 |
May 28, 1969 |
|
|
|
|
Current U.S.
Class: |
340/913;
340/914 |
Current CPC
Class: |
G08G
1/081 (20130101) |
Current International
Class: |
G08G
1/081 (20060101); G08G 1/07 (20060101); G08g
001/07 () |
Field of
Search: |
;340/35,40,41,37 |
References Cited
[Referenced By]
U.S. Patent Documents
|
|
|
3482208 |
December 1969 |
Auer, Jr. et al. |
3252133 |
May 1966 |
Auer, Jr. et al. |
3506808 |
April 1970 |
Riddle, Jr. et al. |
3500308 |
March 1970 |
Riddle, Jr. et al. |
3423733 |
January 1969 |
Auer, Jr. et al. |
3652983 |
March 1972 |
Endo et al. |
|
Primary Examiner: Claffy; Kathleen H.
Assistant Examiner: Myers; Randall P.
Parent Case Text
CROSS-REFERENCE TO RELATED APPLICATION
This application is a continuation-in-part of copending application
Ser. No. 828,645, filed May 28, 1969, "Traffic Signal Control
System", Muramatu et al., now abandoned which is also assigned to
the assignee of the present invention.
Claims
We claim:
1. A system for controlling the traffic signals within a wide area
divided into a plurality of local areas, comprising: a master
controller, a local controller provided for each said local area,
said local controllers having respective addresses, said master
controller including a first pulse register for calling one of said
addresses; means for providing a plurality of different cycle
signals and a plurality of different synchronizing signals to each
of said local controllers, each of said synchronizing signals
paired with one of said cycle signals; means included in each said
local controller and operable in response to a command signal
produced by said master controller to select one of said pairs of
cycle signals and synchronizing signals; said master controller
including a second pulse register for storing said command signal;
means included in said local controller for obtaining from said
selected cycle signal a plurality of cycle signals of different
lengths; and means for applying said command signal to that one of
said local controllers whose address has been called, so that the
traffic signals in each said local area are controlled by the
selected cycle signal and synchronizing signal.
2. The system of claim 1, wherein each said local controller
further includes means for obtaining from said selected cycle
signal and synchronizing signal a plurality of synchronizing
signals indicating the lapse of times of different lengths within
one signal cycle.
Description
This invention relates to a traffic signal control system, and more
particularly to a system which controls traffic signals within a
relatively wide area.
In traffic signal control, it is generally required to control the
traffic signals at various intersections within a considerably wide
area in a more or less correlated manner. Traffic conditions,
however, differ locally at different places or intersections within
the wide area. If the same type of control is employed at all the
intersections within the wide area, it will become impossible to
control the traffic signals at different places or intersections
properly in accordance with the actual local traffic
conditions.
As is usual, traffic is relatively heavy at one place while it is
not so at another. In such a case, if the same signal cycle is used
for controlling the traffic signals at these different
intersections, the signal control cannot be conducted properly in
such a manner as to meet different local traffic conditions, with
resulting confusion to traffic in the area.
Accordingly, it is one object of the invention to provide a traffic
signal control system which controls the traffic signals at various
intersections over a considerably wide area in such a manner as to
effect a smooth traffic flow throughout the area.
Another object of the invention is to provide a traffic signal
control system in which a wide area in which the traffic signals
are to be controlled is divided into a plurality of local areas,
the traffic signals in each of which are controlled
identically.
Another object of the invention is to provide a traffic signal
control system in which a wide area in which the traffic signals
are to be controlled is divided into a plurality of local areas
each having a local controller to be controlled by a master
controller, and wherein there are provided a plurality of different
cycle signals and a plurality of different synchronizing signals
each paired with one of the cycle signals, so that the master
controller gives instructions to each local controller to select
that one of the pairs of cycle signals and synchronizing signals
which is most suitable for control of the traffic signals in each
local area under the present traffic condition in that area, and to
control the traffic signals in the local area by the selected cycle
signal and synchronizing signal.
The term "cycle signal", as hereinafter used, denotes a plurality
of clock pulses supplied by the master controller to each of the
local controllers whose periodicity or frequency is fixed. The
master controller includes means producing a plurality of cycle
signals, each having a different frequency or periodicity. The term
"synchronizing signal", as hereinafter used, denotes a signal whose
periodicity or cycle length determines the length of the traffic
signal cycle provided by each local controller. One synchronizing
signal may be produced for a predetermined number of clock pulses
of a corresponding cycle signal. A plurality of synchronizing
signals are provided by the master controller which correspond to
different cycle signals and thus to different predetermined numbers
of clock pulses thereof. The term "offset signal", as hereinafter
used, denotes the signal produced by a local controller coupled to
the master controller whose periodicity is normally the same as the
synchronizing signal being used by the local controller, and thus
normally having a cycle length equal to the traffic signal cycle
produced by that local controller. One offset signal is produced
for every traffic signal cycle to terminate the green period
thereof.
In accordance with the invention, the master controller always
watches the traffic conditions in each local area and gives
instructions (a cycle signal selection command signal) to the local
controller to select that one of the pairs of cycle signals and
synchronizing signals which is most suitable for control of the
traffic signals in each local area under the existing traffic
condition in the local area. As a result, each local controller
controls the traffic signals in the area by the selected cycle
signal and synchronizing signal so that an effective and smooth
traffic control can be performed throughout the wide area.
FIG. 1 is a diagram of a traffic control system embodying the
invention showing the interconnections between the master
controller, local controllers and intersection controllers
thereof;
FIG. 2 is a diagram of a portion of the system of FIG. 1, showing a
portion of the master controller and portions of the local
controllers thereof;
FIG. 3 is another diagram of a portion of the system of FIG. 1,
showing other portions of the master controller and local
controllers;
FIG. 4 is a diagram explaining the logic symbols used in FIGS. 1-3
and 5; and
FIG. 5 is a diagram of yet another portion of the system of FIG. 1,
showing a portion of one local controller and portions of its
corresponding intersection controllers.
With reference now to FIG. 1, a single master controller 100 is
used for controlling the traffic signals within thirty local areas
301, 302 . . . 330. In order to provide this control, master
controller 100 receives information as to traffic conditions within
each of the local areas from a plurality of vehicle detectors D
located therein. In order to effect coordinated traffic control
throughout the local areas 301--330, master controller 100 includes
means for converting the information as to traffic conditions into
corresponding traffic information parameters, such traffic volume,
traffic congestion, and the like. In addition, the master
controller 100 includes means providing a plurality of cycle
signals and a plurality of synchronizing signals, as heretofore
defined. In order to be uniquely related to the cycle signals, each
of the synchronizing signals must be paired with and derived from a
corresponding cycle signal. In accordance with calculations made
from the traffic information parameters, the master controller 100
then includes means for selecting one of the pairs of cycle signals
and synchronizing signals that is most suitable for control of
traffic signals in each local area. As a result of this selection,
a cycle signal selection command signal is applied from the master
controller 100 to each of the local controllers 201, 202 . . . 230.
In addition, the plurality of cycle signals and synchronizing
signals are also supplied from master controller 100 to each of the
local controllers 201, 202 . . . 230.
Each local controller has associated therewith a plurality of
intersection controllers. In FIG. 1, local controller 201 provides
appropriate control signals to a plurality of intersection
controllers 401, 402 and 403 in local area 301. Similar
arrangements are provided for areas 302-330, but are not
illustrated.
Each local controller includes means for coupling a pair of the
cycle signals and synchronizing signals to the intersection
controllers associated therewith in accordance with the cycle
signal selection command signal that has been coupled thereto from
the master controller 100. Means are also provided within each
local controller for producing an offset signal whose periodicity
is normally the same as the synchronizing signal that has been
selected by the local controller. This offset signal, and signals
derived from the selected pair of synchronizing and cycle signals,
are coupled to the intersection controllers which in turn control
the traffic signals at the intersections within the local area.
In the illustrated embodiment, it is assumed that the traffic
signals in one light area controlled by master controller 100 are
located in thirty local areas 301-330, and that there are provided
10 different pairs of cycle signals and synchronizing signals.
In FIG. 2, master controller 100 is provided with an address
register CA and a register CB. The address register operates to
call the addresses No. 1 to No. 30 of the 30 areas 301-330. The
addresses are expressed in binary code. A suitable computer CM
receives traffic information from vehicle detectors D, calculates,
if necessary, traffic information parameters such as traffic
density, traffic volume, etc., in each local area and selects that
one of the 10 pairs of cycle signals and synchronizing signals
which is most suitable for control of the traffic signals in each
local area under the present traffic condition, and applies a
corresponding signal (the cycle signal selection command signal) to
the register CB to be stored therein. The stored contents of the
register CB are also in binary code.
Corresponding to the 30 local areas 301-330, there are thirty local
controllers 201-230 which are provided with shift registers CR1 to
CR30, respectively. To that one of the shift registers CR1 to CR30
which has been selected by the address register CA, the register CB
transfers its stored contents in the following manner. The address
register is provided with eight output lines 2, 2, 4, 4, 8, 8, 16
and 16. When a signal "1" is produced on the line 2, 4, 8, or 16, a
signal "0" is produced on the line designated by the same reference
numeral with a bar on top thereof; and when a signal "0" is
produced on the former line, a signal "1" is produced on the latter
line. The signal "1" is a positive voltage. To the output lines of
the address register CA there is connected a diode matrix DM1
having 30 output lines L1 to L30 corresponding to the 30 local
areas, respectively. An output appears on that one of the lines
which corresponds to that one of the local areas that has been
selected. Each of the output lines L1 to L30 is connected as one
input to one of AND elements A1 to A30. A line LC is connected to
the other input of each of the AND elements A1 to A30. A suitable
pulse generator PG1 applies clock pulses to the line LC. The
outputs from the AND elements A1-A30 are applied to the shift
registers CR1-CR30, respectively, to cause them to store therein
the contents transferred thereto from the storage register CB
through a line LB.
Suppose that the register CA has selected, say, address No. 2 area.
Then an output appears on the line L2, and whenever a clock pulse
on the line LC coincides with the output on line L2, the AND
element A2 produces an output in the form of clock pulses. As the
clock pulses are applied to the register CR2, the stored contents
of the register CB are transferred through the line LB to the
register CR2 to be stored therein. Since no operating clock pulses
are applied to the other shift registers CR1, CR3-CR30, the
contents of the register CB are not transferred to these shift
registers. Thus, in that one of the registers CR1-CR30 which
corresponds to that one of the local areas that has been selected
by the address register CA there have been stored the instructions
to cause the local controller to effect the type of traffic signal
control selected by the master controller 100, that is, to select
that one of the 10 pairs of cycle signals and synchronizing signals
which is most suitable for signal control under the present traffic
condition in that local area.
This selection is effected in each local controller by a circuit as
shown in FIG. 3, in the following manner. Only local controller 201
is discussed. The register CR1 is capable of storing in binary code
10 numbers No. 1-No. 10 as the above-mentioned selection command
signal and is provided with eight output terminals 1, 1, 2, 2, 4,
4, 8 and 8. Just like the register CA in FIG. 2, in the register
CR1 when a signal "1" is produced on the line 1, 2, 4, or 8, a
signal "0" is produced on the line 1, 2, 4 or 8; and when a signal
"0" is produced on the former line, a signal "1" is produced on the
latter line.
A diode matrix DM2 is connected to the eight output lines of the
register CR1 and has 10 output lines L41-L50. The outputs on these
lines are applied as one input to AND elements A41-A50 and at the
same time to AND elements A51-A60, respectively.
Ten predetermined different cycle signals (which may be designated
by reference Nos. 1-10) are applied to terminals C1-C10,
respectively, and 10 predetermined different synchronizing signals
to be paired with the cycle signals are applied to terminals
R1-R10, respectively. The cycle signals comprise pulses and have
different frequencies.
To generate the cycle signals and the synchronizing signals, the
master controller 100 includes a source of clock pulses comprising
a pulse generator PG2, whose output is applied to a counter CC1.
The outputs from the counter CC1 comprise the ten cycle signals.
Generally, the frequency of the cycle signals is variable within
the range of 40-120 HZ. For example, the first cycle signal
supplied to terminal C1 may have a frequency of 40 HZ. The cycle
signal supplied to terminal C2 may have a frequency of 50 HZ, and
so forth. In order to be uniquely related to these cycle signals,
each of the signals on terminals R1-R10 must be paired with and
derived from its corresponding cycle signal on terminals C1-C10. To
this end, the outputs from the counter CC1 are also applied to a
plurality of frequency dividers CC2-1, CC2-2 . . . CC2-10, whose
outputs serve as the synchronizing signals on terminals R1-R10. In
one embodiment, each of the frequency dividers CC2-1, etc.,
comprise a counter providing an output pulse for every 800 input
pulses thereto. Therefore, one synchronizing signal is produced for
every 800 pulses of the cycle signal associated therewith. For
example, for the pair of signals on terminals C1-R1, the
synchronizing signals on terminal R1 occur every 800/40 HZ, or 20
seconds. For the combination of signals on terminals C2-R2, the
synchronizing signals on terminal R2 are produced for every 800/50
HZ, or 16 seconds.
The cycle signals on the terminals C1-C10 are applied as the other
input to the AND elements A41-A50, respectively, and the
synchronizing signals on the terminals R1-R10 are applied as the
other input to the AND elements A51-A60, respectively.
Suppose that the register CR1 has received from the register CB a
selection command signal to select cycle signal No. 2. Then, the
AND element A42 receives one input from the register CR1. On the
other hand, the cycle signal No. 2 applied to the terminal C2 is
applied as the other input to the AND element A42. As a result, the
cycle signal No. 2 is obtained as the output from the AND element
A42. In like manner, the synchronizing signal applied to the
terminal R2 appears as the output from the AND element A52. Thus,
the cycle signal No. 2 and the synchronizing signal paired
therewith appear at terminals SC and SR through OR elements 01 and
02, respectively, and will be used to control the traffic signals
within the local area. Thus, in the local area selected by the
master controller, the traffic signal is controlled by the cycle
signal and the synchronizing signal paired therewith as selected by
the master controller 100 to best meet the traffic condition in
that area.
If the synchronizing and cycle signals were not so paired, and each
local controller were free to count a predetermined number of clock
pulses of the cycle signal to determine the duration of the local
traffic signal's cycle, loss of synchronism between the local areas
would result.
FIG. 5 includes means to obtain from the cycle signal so selected,
a reference cycle signal, a cycle signal having a period 12.5
percent longer than that of the reference cycle signal, and a cycle
signal having a period 12.5 percent shorter than that of the
reference cycle signal, and, from the synchronizing signal so
selected, signals which show the lapse of times equal to 0, 4, 50
and 90 percent, respectively, of one signal cycle.
The pulses applied to the terminal SC are counted by heptal, octal
and nonary pulse counters PC1, PC2 and PC3 at the same time. When
seven, eight and nine pulses have been counted by the counters PC1,
PC2 and PC3, respectively, they produce one output pulse at their
respective output terminals T1, T2 and T3. Suppose that one signal
cycle length consists of 100 pulses at any of the terminals T1, T2
and T3. It is easily seen that 700, 800 and 900 pulses must be
applied to the counters PC1, PC2 and PC3, respectively, to produce
100 pulses at the terminals T1, T2 and T3. This means that one
signal cycle length as determined by the output pulses at the
terminal T1 is 12.5 percent shorter than the reference signal cycle
length as determined by the output pulses at the terminal T2, and
that one signal cycle length as determined by the output pulses at
the terminal T3 is 12.5 percent longer than the reference signal
cycle length.
The output pulses from the counter PC2 are counted by a counter PC4
having four output lines 00, 04, 50 and 90, on which an output
appears when the counter PC4 has counted 0, 40, 50 and 90 pulses,
respectively. The output is taken out from terminals T00, T04, T50
and T90. The counter PC4 is reset by the synchronizing signal from
the terminal SR. It will be seen that the signals at T00, T04, T50
and T90 appear upon lapse of times equal to 0, 4, 50 and 90 percent
of one cycle length of the synchronizing signal, respectively.
The 12.5 percent shorter cycle signal, the reference cycle signal,
and the 12.5 percent longer cycle signal on terminals T1, T2 and T3
are coupled to corresponding terminals C1, C2 and C3 in each of the
intersection controllers 401, 402 and 403. In a similar manner, the
signals on terminals T00, T04, T50 and T90 are supplied to
corresponding terminals M0, M04, M50 and M90 of each intersection
controller 401, 402 and 403.
The signals on terminals C1, C2 and C3 are applied as one input to
AND elements 411, 412 and 413, respectively. A tristable circuit
425 applies its three outputs B1, B2 and B3 to the other input of
the AND elements 411, 412 and 413, respectively, as will be
described in more detail later.
The output pulses from the AND elements 411-413 are applied through
an OR element 414 to a pulse counter 415. This counter is designed
so that whenever it has counted 100 pulses applied thereto, it is
reset. During its counting cycle, pulse counter 415 provides a
plurality of successive outputs which are applied in turn to a
signal light controller 426, which in turn uses these signals to
control the traffic signal light 427 at an intersection.
Each local controller, such as local controller 201, includes
means, not illustrated, for producing an offset signal, which
determines the offset of each of the intersection controllers, such
as intersection controllers 401, 402 and 403, associated therewith.
This offset signal comprises a binary coded decimal number which is
applied to terminal SO in FIG. 5. Terminal SO is in turn coupled to
the input of a register 416 which comprises a 7-bit register
capable of storing decimal numbers up to 100. In this regard, pulse
counter 415 is of a construction similar to register 416 and
additionally has seven output lines, which are applied to a
coincidence circuit 417 together with the seven outputs from
register 416.
The signal on terminal M04 is applied as a set input to a flip-flop
418, to which the signal on terminal M90 is applied as a reset
input. Therefore, the flip-flop 418 is kept set during the period
of time from 4 percent to 90 percent of one signal cycle length.
The signal M50 is applied as a set input to a flip-flop 419, to
which the signal M00 is applied as a reset input. Therefore, the
flip-flop 419 is kept set during the period of time from 50 percent
to 100 percent of one signal cycle.
The circuit 417 compares the values stored in the register 416 and
the counter 415 and produces an output on the line OS when the two
values coincide. This signal on line OS is supplied as one input to
four AND elements 421, 422, 423 and 424.
The set output from the flip-flop 418 is applied as a second input
to the AND element 421, to which the set output from the flip-flop
419 is applied as a third input. Therefore, the AND element 421
produces an output only when the signal OS is produced by the
coincidence circuit 417 during the period of time from 50 percent
to 90 percent of one signal cycle length. In the following
description, the expression such as "the period of time for 50
percent to 90 percent of one signal cycle length" will be expressed
simply as "the 50-90 percent period of time". The reset output from
the flip-flop 418 is applied as the other input to the AND element
422. Therefore, the element 422 produces an output only when the
signal OS is produced during the 90-100 percent period of time, or
the 0-4 percent period of time, of one signal cycle. The set output
from the flip-flop 418 is applied as a second input to the AND
element 423, to which the reset output from the flip-flop 419 is
applied as a third input. Therefore, the AND element 423 produces
an output only when the signal OS is produced during the 4-50
percent period of time of one signal cycle. Finally, the reset
output of the flip-flop 418 is applied as a second input to the AND
element 424, to which the set output from the flip-flop 419 is
applied as the third input. Therefore, the AND element 424 produces
an output only when the signal OS is produced during the 90-100
percent period of time of one signal cycle.
The outputs from the AND elements 421-423 are applied as three
inputs to the tri-stable circuit 425. When the output from the AND
element 421 is applied to the input F of the circuit 425, it
produces an output signal on the line B1; when the output from the
AND element 422 is applied to an input S of the circuit 425, it
produces an output signal on the line B2; and, when the output from
the AND element 423 is applied to an input T of the circuit 425, it
produces an output signal on the line B3.
The output ST from the AND element 424 is applied as one input to
the OR element 414. Therefore, so long as the output ST continues
to be applied to the OR element 414, the counter 415 does not step
forward even when any of the AND elements 411-413 apply pulses
thereto.
Suppose that on the basis of the traffic information received from
the vehicle detectors D, master controller 100 has decided that it
is necessary to change the offset in the local areas. Accordingly,
this offset change is provided to the local controller 201 and
transmitted therethrough to each of the intersection controllers
401, 402 and 403, as an offset signal on the line SO. The signal on
SO is stored in register 416 as previously described. At this time,
the counter 415 is stepping forward during the reference cycle
pulses on terminal C2, as applied through AND element 412 and OR
element 414. When the counter 415 has reached a count which
coincides with the new offset value stored in the register 416, the
coincidence circuit 417 produces an output on the line OS.
Naturally, the relation between the signal OS and the synchronizing
pulses being applied to the terminals MO4, M50, M90 and M00 now
becomes different from the relation existing before the new offset
was stored in the register 416.
Suppose that the signal OS has been produced during the 50-90
percent period of time of the signal cycle. The moment the signal
OS has been produced, the AND element 421 produces an output to be
applied to the input F of the tri-stable circuit 425, so that an
output signal is produced on line B1 and applied to the AND element
411. Then, the counter 415 begins to count the cycle pulses thereto
appearing on terminal C1, whose frequency is lower by 12.5 percent
than that of the reference cycle pulses on terminal C2. Therefore,
the time required for the counter 415 to count 100 pulses applied
through the terminal C1 becomes 12.5 percent longer than the time
required for the counter to count 100 pulses applied through the
terminal C2. In other words, one signal cycle length has now become
12.5 percent longer than the normal signal cycle. It will be easily
seen that as this length in signal cycle is repeated three or four
times at most, the signal OS comes to appear within the 90-100
percent, or 0-4 percent period of time of the normal signal cycle
length, as defined by the synchronizing pulses applied to the
terminals M00-M90.
In the case that the signal OS has appeared within the 90-100
percent period of time, the AND element 424 produces an output on
the line ST to be applied through the OR element 414 to the counter
415. So long as this signal ST is being applied to the counter 415,
it does not step forward. During the 90-100 percent period of time,
the AND element 422 produces an output so that an output signal is
produced on terminal B2 from the circuit 425 and applied to the AND
element 412. This causes the pulses on terminal C2 to be applied
through the AND element 412 and the OR element 414 through the
counter 415. However, the continuous application of the signal ST
to the counter 415 prevents the pulses on terminal C2 from stepping
the counter 415. When the 90-100 percent period of time has
elapsed, however, the signal M00 causes the signal ST to disappear,
whereupon the counter 415 begins counting the cycle pulses on
terminal C2. Since 100 pulses on the terminal are produced for
every reference cycle length, the counter 415 is returned to zero
count upon lapse of every reference cycle. Thus, the discrepancy
between the synchronizing pulse M00 and the output pulses from the
pulse counter 415 becomes equal to the new offset as stored in the
register 416. From this time on, the counter 415 produces output
pulses which are supplied to controller 426 on the basis of the new
offset until the offset is again changed.
In the case that the signal ST has appeared within the 0-4 percent
period of time, the AND element 422 produces an output on the line
B2, whereupon the counter 415 begins counting the pulses on
terminal C2.
Suppose that the signal OS from the coincidence circuit 17 is
produced within the 4-50 percent period of time of the signal
cycle. Then the AND element 423 produces an output to be applied to
the input T of the tri-stable circuit 425, so that circuit 425
produces an output on the line B3 to be applied to the AND element
413. This causes the counter 415 to count the cycle pulses on
terminal C3 applied thereto through the OR element 414 and AND
element 413. Since the frequency of the signal on terminal C3 is
higher by 12.5 percent than that of the reference signal on
terminal C2, the time required for counter 415 to count 100 pulses
of the cycle signal on terminal C3 becomes shorter by 12.5 percent
than the reference signal cycle length. Therefore, while the
shortened signal cycle is repeated three times at most, the signal
OS comes to appear within the 0-4 percent period of time of the
signal cycle as defined by the synchronizing pulses M00-M90, or,
while the shortened signal cycle is repeated four times at most,
the signal OS comes to appear within the 90-100 percent period of
time of the normal or reference signal cycle. Then, the output
pulses from the counter 415 are forwardly displaced from the signal
M00-M90 by the new offset as stored in the register 416. In other
words, the counter 415 now produces pulses for control of the
signal controller 426 on the basis of the new offset.
* * * * *