Speech Unscrambler

Abstract

A digital device to make speech in a helium atmosphere more intelligible includes a recirculating storage and an analog to digital converter which periodically samples the speech and the digital samples are loaded into the storage at a rate determined by a load counter. An unload counter continuously operating at a predetermined slower rate than the load counter unloads the stored digital representations of the speech and a digital to analog converter converts it back to an analog signal. The analog signal is utilized by an output means such as a loudspeaker and is an intelligible translation of the input speech. Since the storage is loaded at a faster rate than it is unloaded, it will periodically fill up, and no more digital samples are loaded, until such time as the storage is again emptied.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention in general relates to frequency conversion or compression and more particularly to converter apparatus for converting a shifted frequency speech which is relatively unintelligible to an intelligible output speech.

2. Description of the Prior Art

Due to certain physiological problems divers breathing an air mixture are limited to depths around 200 feet or less. Even where operations are carried out at shallower depths, divers breathe a mixture of helium-oxygen or helium-nitrogen-oxygen in place of air to eliminate, or reduce the effects of nitrogen narcosis. The helium mixture however creates a serious problem in communications in that the diver's speech in the helium atmosphere is high pitched and under some conditions can be completely unintelligible. This distortion of the voice is sometimes called "helium speech" and is basically due to an increase in the frequency or pitch of the voice. Although the fundamental voice pitch (about 100 hertz) remains unaffected the voice harmonics, known as formants, to a good approximation are shifted upward by a common factor which may be as high as 2.8 to 3.0 and is determined by the gas mixture actually used, its pressure, and the length of time the speaker has been in the helium atmosphere.

The helium speech could be "unscrambled" by first recording at one speed on a magnetic tape and then playing the tape back at a second and slower speed proportional the frequency shift. With this scheme however if it took 15 minutes to record a conversation and if it took 30 minutes to play back that conversation it would take a total of 45 minutes to assimilate the entire message. There is accordingly a need for a real time "translation" or unscrambling of the helium speech.

One method of providing a real time unscrambling of helium speech involves the use of magnetic tape with a rotating head whereby portions of the helium speech are eliminated. The intelligibility does not suffer greatly since the message can still be understood even though small fractions are missing. For deep-sea mobile use however it is the primary objectives that a helium speech unscrambler be lightweight, compact and rugged and have no moving parts such as magnetic tape arrangement with rotating heads.

accordingly it is an object of the present invention to provide a helium speech unscrambler which meets all of the above recited primary objectives.

Accordingly is another object of the present invention to provide a digital helium speech unscrambler utilizing state-of the-art engineering such that the unscrambler may be microminiaturized to be conveniently carried by a diver.

SUMMARY OF THE INVENTION

Basically, there is provided frequency conversion apparatus operable to receive a speech signal shifted in frequency by some multiple S.sub.H. The signal is periodically sampled, converted to digital form and placed into storage at a rate f.sub.i. The samples are read out of storage in the same sequence as they were read in, at a rate f.sub.o, with the ratio of f .sub.i /f.sub. o being approximately equal to S.sub.H. The samples unloaded from storage are converted back to analog form for use with suitable output means.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1a to 1c are speech waveforms to aid in an understanding of the present invention;

FIG. 2 illustrates in block diagram from a preferred embodiment of the present invention;

FIG. 3 illustrates some of the components of FIG. 2 in somewhat more detail; and

FIG. 4 illustrates a time sequence applicable to the operation of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

In FIG. 1a there is illustrated a typical speech signal with the speaker talking in an air atmosphere. The speech signal includes a fundamental 10 at the frequency f.sub.f and a plurality of formants 12, 14 and 16 each at a respective frequency f.sub. i, f.sub. 2 and f.sub.3.

FIG. 1b illustrates the same signal as FIG. 1a, except that the speaker is in a helium-oxygen atmosphere. The fundamental 10 remains unaffected however, formants 12', 14' and 16', constituting a shifted frequency speech signal have all been shifted by a multiple S.sub.H of 2 and are positioned at respective frequencies of f.sub. 2, f.sub. 4 and f.sub. 6.

The present apparatus processes the shifted frequency speech signal of FIG. 1b to provide an output signal as illustrated in FIG. 1c which includes the formants 12, 14 and 16 shifted back to their proper respective frequencies f.sub. 1, f.sub. 2 and f.sub. 3.

The means by which this apparent downward shift in frequency occurs is illustrated in FIG. 2 to which reference is now made.

A speech signal such as in FIG. 1b is applied to input terminal 20 and may emanate from a source such as a tape recorder or preferably, as contemplated by the present invention, from a microphone arrangement 21 carried by a diver, or located in a helium (or other light gas) atmosphere chamber.

By comparing FIGS. 1a and 1b it is seen that the fundamental 10 is not shifted in frequency as are the formants. Accordingly only the formants need be processed and there is provided a band-pass filter 24 operable to pass frequencies in the range of for example 600 hertz to 9.5 kilohertz such that the fundamental is filtered out. It is a recognized fact even with the fundamental removed the intelligence contained in a shifted frequency speech signal may be recovered, although the inclusion of the fundamental in the output frequency signal would provide a somewhat better degree of intelligibility. The filter 25 therefore may be provided and is a low-pass filter operable to pass only the fundamental for subsequent inclusion in the processing.

An amplifier 27 couples the output of filter 24 to an analog to digital converter means 29 operable to convert the shifted frequency signal from the filter 24 from an analog signal to a digital equivalent upon command of control circuit 31. Such analog to digital converters are well known to those skilled in the art. Consecutive samples, in digital form, of the shifted frequency speech signal are loaded into storage 37 at a rate governed by the control circuit 31. The stored digital numbers are read out of storage 37 in the same sequence as they were loaded at an unloading rate governed by the control circuit 31 and are converted back to an analog signal by the digital to analog converter means 40.

With the shift in frequency of the shifted frequency speech signal being equaled to S.sub.H, the ratio of the rate of loading into storage to the rate of reading out of storage is made approximately equal to S.sub.H. The output of the digital to analog converter 40 is coupled through amplifier 43 to a smoothing filter 45 which supplies an intelligible and unscrambled speech signal (such as 12, 14, 16 in FIG. 1c ) to the output means 48 which may be any utilization device such as magnetic tape, earphones, loudspeaker, etc. With the inclusion of filter 25 there is provided a summation circuit 50 which adds the fundamental (10 of FIG. 1c ) to the formants.

FIG. 3 illustrates by way of example one type of storage which may be utilized in practicing the invention and further illustrates an example of a control circuit 31 which may be utilized to control the loading and unloading of the storage 37 in accordance with the present teachings.

In general, if the analog to digital converter provides a digital output of n binary bits, there may be provided n individual storage devices. By way of example in FIG. 3 the analog to digital converter 29 provides a five-bit output, one bit on each of lines 53 to 57, and therefore the storage 37 may be comprised of five recirculating delay line means in the form of shift registers 60 to 64 each for receiving a respective bit output from the analog to digital converter 29. A typical shift register such as 60 includes a plurality of flip-flops each for storing one bit of information. Register 60 includes 49 flip-flops designated ff1, ff2,... ff The following explanation with respect to shift register 60 is equally applicable to all the other shift registers 61 to 64. Initially one bit of information on line 53 is set into flip-flop ff1. Thereafter with the provision of clock pulses on line c, that bit of information will be transferred to a subsequent flip-flop. When the bit of information is set into the last flip-flop ff49 it may be read out on line 67 if the digital to analog converter 40 is ready to receive the information or it may be fed back to the first flip-flop ff1 via line 68 to be recirculated in the shift register.

During the recirculation process a subsequent bit from a subsequent sample is read into flip-flop ff1 and it is recirculated as was the first bit. Subsequent samples are read in at a certain predetermined rate. At some point in the recirculation process the very first bit of information that was read out of flip-flop ff49 and thereafter subsequent bits are read out in the same order as they were read in at a predetermined rate slower than the reading in rate. Accordingly, since the bits are being read out at a rate slower than they are read in the register 60 will become filled. At such time no more samples are read into the registers until the they are completely unloaded.

The control circuitry 31 for controlling these various functions include by way of example a master synchronizing or timing clock 70 operable to provide clock pulses on line c at a rate of f.sub.c.

A load counter 72 is operable to count up a predetermined number of clock pulses and is operable to provide an output pulse on line 73 when that number is attained. If the predetermined number of clock pulses is S.sub.i then the load counter 72 will provide an output signal at a rate f.sub. i = (f.sub.c /S.sub. l ).

With the provision of each output pulse on line 73 the analog to digital converter 29 will function to provide a new sample in digital form to the storage 37, and more particularly will operate to provide on each of its output lines 53 to 57 one bit of information to the first flip-flop ff1 of respective storage register 60 to 64.

In order to unload the information from storage there is provided an unload counter 76 which is operable to count up the clock pulses from the clock 70 to provide an output pulse when a predetermined number, S.sub. o, of clock pulses have been provided. Accordingly the unload counter 76 will provide an output pulse signal on line 77 at a rate f.sub. o = (f.sub. c /S.sub. o.

The ratio of f.sub. i to f.sub. o and the ratio of S.sub. o to S.sub. i are chosen to be approximately equal to the frequency shift S.sub. H.

Since the read out rate is slower than the read in rate, means are provided to sense when the storage becomes filled to capacity. The sensing means includes the up/down counter 80 which is operable to receive the output signal from the load counter 72 and the output signal from the unload counter 76. When the up/down counter 80 has not attained its maximum count, that count being equal to the number of flip-flops in a shift register, an enabling signal is provided on line 81 to AND-gate 83 which is thereby enabled to past the clock pulses from clock 70 to the load counter 72. The provision of an output pulse from the load counter 72 not only effects a read in to storage 37 but also causes the up/down counter 80 to advance one count. Similarly the provision of an output pulse from the unload counter 76 not only causes a read out from storage 37 but also subtracts a count from the up/down counter 80. Since the up pulses are provided at the load rate and the down pulses at the unload rate the up/down counter 80 when the counter 49 is reached is indicative of the fact that the storage registers are filled to capacity and the enabling signal on line 81 is removed such that the load counter 72 does not receive clock pulses and accordingly no information is read into storage 37. The unload counter 76 however still continues to receive the clock pulses and read out of the stored information continues until the storage 37 is emptied. While the information is being read out the previously filled up/down counter 80 is being counted down and when it reaches zero the enabling signal will again be provided on line 81 whereby information is thereafter read into storage 37 in the manner previously described. When a new bit of information is to be entered into flip-flop ff1 it is important that the bit in flip-flop ff1 via link 68. Accordingly, an AND-gate 85 is provided for receiving the output of flip-flop ff49 and an enabling signal from the load counter 72. Basically, when the load counter 72 does not provide an output signal, recirculation is to take place. An inverter circuit 87 provides an enabling signal to AND-gate 85 when the load counter 72 does not provide an output signal. For a load operation, a pulse is provided by load counter 72 and is inverted by inverted 87 such that the enabling signal is removed from AND-gate 85 and the bit in flip-flop ff49 is prevented from recirculating.

Although the shifted frequency signal is continuously being supplied, small portions of it are not being sampled and read into storage since the command to load is not being provided by the load counter 72 for a period of time beginning when the up/down counter 80 is full (and accordingly the storage 37 is full) to the time that the up/down counter 80 has been counted down to zero (and accordingly when the previously filled storage 37 has been emptied).

Although portions of the speech are not being sampled, they are extremely small portions and an intelligible signal may still reconstructed. The proportion of speech not sampled, the loading rate, and the unloading rate are determined by the amount of frequency shift of the speech and the clock rate f .sub.c.

By way of example, for 49 bit shift registers the following is a chart illustrating various settings to be made for various frequency shifts with a typical clock frequency f.sub. c. of 2 megahertz, that is, every 0.5 microseconds a clock pulse is provided. ---------------------------------------------------------------------------

1 2 3 1 2 3 Frequency Frequency Shift Load Unload Shift Load Unload S.sub.H S.sub.i S.sub.o S.sub.H S.sub.i S.sub.o __________________________________________________________________________ 1.0 100 100 2.2 83 181 124 271 164 360 1.3 164 213 2.3 114 261 1.4 124 173 152 348 1.5 99 148 2.4 106 253 197 295 141 337 1.6 83 132 2.5 66 164 164 262 99 246 132 328 1.7 71 120 141 239 2.6 93 240 124 320 1.8 124 222 185 332 2.7 87 234 116 312 145 390 1.9 55 104 110 208 164 311 2.8 83 230 110 306 137 382 2.0 99 197 148 295 2.9 78 225 104 300 2.1 90 188 130 375 135 282 3.0 75 222 99 295 124 369 __________________________________________________________________________

Column 1 sets forth various frequency shifts S.sub.H ranging in value from 1.0 to 3.0. Column 2 sets forth the number of clock pulses S.sub.i that the load counter 72 counts up before providing an output pulse and column 3 sets forth the number of clock pulses S.sub.o that the unload counter 76 counts up before providing an output pulse. By way of example, for a frequency shift of 2.0 the load counter 72 may be set to provide an output pulse for every 99 clock pulses it receives while the unload counter 76 is set to provide an output pulse for every 197 clock pulses it receives (a second set of values S.sub.i = 148 and S.sub.o = 295 may also be utilized). After the load counter 72 receives 99 clock pulses a first bit of information is read into each first flip-flop ff1 of the storage registers 60 to 64. After the 100 th clock pulse the information in first flip-flop ff1 is transferred to the second flip-flop ff2. After the 101st clock pulse the information in flip-flop ff2 is transferred to a subsequent flip-flop. Subsequent clock pulses will bring the bit of information to the last flip-flop ff49 and thereafter back to flip-flop ff1. On the 197th clock pulse the bit will be in flip-flop ff49 and the unload counter 76 will provide its first output pulse to effect a read out from flip-flop ff49 into the digital to analog converter 40. After the very next clock pulse, the 198th, the load counter 72 will provide its second output pulse to read in a second value. After the 296th clock pulse another value will be read in and the previously written second value will not be read out until the 394th clock pulse. In general the ratio of S.sub.o /S.sub. i is approximately equal to S.sub.H and to insure that a bit read into ff1 is read out of the last flip-flop, S.sub. o- S.sub.i = aN, where a is an interger and N is the number of bits of storage in each shift register.

The shifted frequency speech signal is sampled every 49.5 microseconds (99 clock pulses x 0.5 microseconds per clock pulse) for a period of time T.sub. L until the storage is filled to capacity. Since unloading occurs simultaneously with the loading operation, T.sub. L = (N/ f.sub.i -f.sub.o). After the storage 37 is full the time required for unloading T.sub.U = (N/ f.sub.o). The operation is such that the shifted frequency speech signal is sampled for the period T.sub. L and the sampled values are read out in the same sequence as they were read in over a time period equal to T.sub. L +T.sub.U.

For the example under discussion, the following is a summary of chosen and calculated values (circulations have been carried out to the nearest 10 ):

Frequency Shift S.sub.H 2 Number of bits N in shift register 49 Clock frequency f.sub.c 2 megahertz Clock period 0.5 microseconds S.sub. i 99 S.sub. o 197 Loading rate f.sub..sub.i =f.sub.c /S.sub.i 20.2 kilohertz Unloading rate f.sub. o =f.sub. c /S.sub. o 10.1 kilohertz 1 Load every 49.5 microseconds one Unload every 98.5 microseconds Time to fill storage T.sub.L 4.8 milliseconds Time to unload full storage T.sub. U 4.8 milliseconds

The input speech is sampled for the period of time T.sub..sub.L and the consecutive samples are spread out over the period of time T.sub. L + T.sub. U . This operation is graphically illustrated in FIG. 4 in curve A. Block 90 extending from time T.sub. 0 to T.sub. 1 represents a set of consecutive samples of the speech waveform which is read into storage. At time T.sub. 1 the storage is filled to capacity and the input is shut off for a period T.sub. U . .delta. microseconds after T.sub. 0, reading out of the samples represented by block 90' in curve B continuing past the time when the memory is filled (T.sub. 1) until the last value in the first set is read out. It is seen therefore that the set of values read into storage from time T.sub. O to T.sub. 1 is read out in the time period from T.sub.0 +.delta. (.delta. being insignificant) to T.sub. 2, at which time the previous operation repeats so that there are substantially no discontinuities in the output signal. The time delay .delta. may if desired be eliminated by for example the provision of additional logic circuitry which starts loading the storage 37 prior to its being completely emptied.

From curve A it is seen that there are periods T.sub. U during which the shifted frequency speech signal is unsampled. Although the resolution of the output is somewhat degraded, a comprehendable translation of the original shifted speech still results. The operating frequencies are chosen such that the discarded or unsampled portions of the shifted frequency speech signal are not long enough to contain syllables and that each set of samples is long enough to contain several cycles of the speech frequencies.

Accordingly there has been described apparatus which may be utilized as a helium speech unscrambler and incorporating state-of-the-art circuitry which may be fabricated in integrated circuit form to provide a compact device that a diver may carry on his person. A shifted frequency speech signal is sampled and consecutive samplings are read into a storage at one rate and are read out of that storage in the same sequence as they were read in, and at a second rate with the ratio of reading in to reading out being in the order of the amount of frequency shift.

Although the present invention has been described with a certain degree of particularity it should be understood that the present disclosure has been made by way of example and that various types of storage may be utilized as well as different arrangements of control circuitry and it is apparent that numerous other modifications and variations of the present invention are made possible in the light of what has been disclosed.

Claims

We claim:

1. Speech converter apparatus comprising:

a. input means for receiving a speech signal shifted in frequency by a multiple, S.sub. H ;

b. a control circuit

c. storage means for storing digital information;

d. analog to digital converter means for converting said speech signal to digital form and responsive to said control circuit for loading said storage means with consecutive samples of said speech signal at a first rate f i;

e. digital to analog converter means responsive to said control circuit for unloading at a second rate f.sub. o, said consecutive samples in the same sequence as they were loaded and converting said samples back to an analog signal;

f. the valve of f.sub. i and f.sub. o being chosen such that the ratio of f.sub. i / f.sub. o is approximately equal to S.sub. H ; and

g. output means responsive to said digital to analog converter means for utilization of said analog signal.

2. Apparatus according to claim 1 wherein:

a. the input means receives a speech signal wherein S.sub. H is greater than one and

b. the first rate f.sub. i is greater than the second rate f.sub. o.

3. Apparatus according to claim 1 wherein:

a. the storage means includes recirculating delay line means; and wherein

b. the control circuit loads a first digital number from the analog to digital converter means into said recirculating delay line means and unloads said first digital number after it has recirculated a predetermined amount.

4. Apparatus according to claim 3 wherein:

a. the digital number has n binary bits; and

b. the recirculating delay line means includes n individual recirculating delay lines each for receipt of a respective one of said binary bits.

5. Apparatus according to claim 4 wherein:

a. the individual recirculating delay lines are shift registers.

6. Apparatus according to claim 1 wherein:

a. the analog to digital converter means provides, for each sample, a digital output having n binary bits;

b. the storage means includes n shift registers each for receipt of a respective one of said binary bits.

7. Apparatus according to claim 3 wherein:

a. the control circuit loads a subsequent digital number during the time that the first digital number is recirculating.

8. Apparatus according to claim 1 wherein:

a. the control circuit includes

i. a master clock operable to provide clock pulses;

ii. a load counter responsive to said master clock for providing an output load signal every S.sub.i clock pulses,

iii. an unload counter responsive to said master clock for providing an output unload signal every S.sub. o clock pulses;

b. S.sub. i and S.sub. o being integers and the ratio of S.sub. o /S.sub. i being approximately equal to S.sub. H.

9. Apparatus according to claim 8 which additionally includes:

a. circuit means for sensing when the storage means is full for preventing the load counter from providing an output load signal until the storage means is again empty.

10. Apparatus according to claim 9 wherein:

a. the circuit means includes

i. an up/down counter responsive to the load counter for advancing one count each time a load signal is provided and responsive to the unload counter for subtracting one count each time and unload signal is provided and operable to provide an output enabling signal when less than full, and

ii. gating means responsive to said enabling signal for gating the clock pulses to the load counter when said enabling signal is provided.

11. Apparatus according to claim 1 wherein:

a. the input means includes filter means for filtering out the fundamental of the input speech.

12. According to claim 11 which additionally includes:

a summation means for adding the filtered out fundamental to the output of the digital to analog converter means.