U.S. patent number 3,628,099 [Application Number 05/046,984] was granted by the patent office on 1971-12-14 for resistance-responsive control circuit.
This patent grant is currently assigned to Wagner Electric Corporation. Invention is credited to Carl E. Atkins, Arthur F. Cake.
United States Patent |
3,628,099 |
Atkins , et al. |
December 14, 1971 |
**Please see images for:
( Certificate of Correction ) ** |
RESISTANCE-RESPONSIVE CONTROL CIRCUIT
Abstract
A circuit for controlling energization and deenergization of a
load only in response to a value of resistance falling within a
narrow predetermined range of resistances. The circuit has the
capability of preventing unlocking by the insertion of a variable
resistor between the terminals provided for sensing the keying
resistance and hunting for the proper value of resistance.
Inventors: |
Atkins; Carl E. (Montclair,
NJ), Cake; Arthur F. (Smithtown, Long Island, NY) |
Assignee: |
Wagner Electric Corporation
(N/A)
|
Family
ID: |
21946426 |
Appl.
No.: |
05/046,984 |
Filed: |
June 17, 1970 |
Current U.S.
Class: |
361/172;
70/DIG.46; 361/188 |
Current CPC
Class: |
G07C
9/00714 (20130101); B60R 25/04 (20130101); Y10S
70/46 (20130101) |
Current International
Class: |
B60R
25/04 (20060101); G07C 9/00 (20060101); E05b
049/00 () |
Field of
Search: |
;317/134,DIG.5
;340/147R,147A,149A ;70/278,DIG.46 ;324/62R,62C ;307/218,235 |
References Cited
[Referenced By]
U.S. Patent Documents
Primary Examiner: Miller; J. D.
Assistant Examiner: Moose, Jr.; Harry E.
Claims
What is claimed is;
1. A resistance-responsive circuit for controlling the energization
and deenergization of a load comprising:
1. sensing circuit means having a pair of input terminals and
operative to generate a predetermined output voltage in response to
the connection of a keying resistance between said input
terminals;
2. first, second and third signal-generating circuit means, each
operative in response to said predetermined output voltage to
generate first, second and third predetermined output signals,
respectively; and
3. signal-responsive circuit means having first, second and third
input channels and being operative to alter the energization state
of a load only in response to the coincident application of said
first, second and third predetermined output signals to said first,
second and third input channels, respectively.
2. A resistance-responsive circuit according to claim 1 wherein
said signal-responsive circuit means comprises:
1. a first AND gate having first, second and third input channels
connected to the outputs of said first, second and third
signal-generating means, respectively;
2. charging circuit means comprising a resistance and a first
capacitance connected in series, said first capacitance being
dischargeable by said first AND gate when coincident signals are
provided to said first, second and third input channels; and
3. semiconductor switching means operative to control the
energization state of a load, being maintained normally
nonconductive by the voltage developed across said capacitance of
said charging circuit means.
3. A resistance-responsive circuit according to claim 2 including
antitamper circuit means coupled to each of said first, second and
third signal-generating circuit means and operative for a
predetermined period of time after actuation by connecting of a
nonkeying resistance between said input terminals to prevent said
signal-responsive circuit means from changing the energization
state of a load when a keying resistance is connected between said
input terminals.
4. A resistance-responsive control circuit according to claim 3
wherein said antitamper circuit means comprises:
1. a second AND gate controlled by said first and second
signal-generating circuit means;
2. a third AND gate controlled by said first AND gate and by said
third signal-generating circuit means;
3. relaxation oscillator circuit means comprising a normally
discharged during periods of oscillation of said relaxation
oscillator circuit means, charging being controlled by said third
signal-generating circuit means; and
4. a normally charged third capacitance connected in a parallel
charging current path with said second capacitance and to a
normally open discharge current path controlled by said second AND
gate which is operative to close said discharging current path when
a nonkeying resistance is connected between said input
terminals.
5. A resistance-responsive circuit according to claim 1 wherein
said sensing circuit means consists of a two-stage emitter-follower
amplifier having a high input impedance at said input
terminals.
6. A resistance-responsive circuit according to claim 1 wherein
each of said signal-generating means includes a normally conducting
output transistor which provides said predetermined output signal
by becoming nonconductive in response to said predetermined output
voltage of said sensing circuit means.
7. A resistance-responsive circuit according to claim 1 wherein
each of said signal-generating circuit means comprises:
1. threshold circuit means operative to generate a predetermined
intermediate output in response to said predetermined output
voltage of said sensing circuit means; and
2. output switching means operative to change its conductivity
state in response to said intermediate output of said threshold
circuit means.
8. A resistance-responsive circuit according to claim 7
wherein:
1 . said threshold circuit means of said first signal-generating
circuit means includes variable bias means set to maintain said
threshold circuit means normally nonconducting;
2. said threshold circuit means of said second signal-generating
circuit means includes variable bias means set to maintain said
threshold circuit means normally conducting; and
3. said threshold circuit means of said third signal-generating
circuit means includes bias circuit means operative to maintain
said threshold circuit means nonconductive and to enable said
threshold circuit means to be rendered conductive by virtually any
decrease in the normal output of said sensing circuit means.
9. A control circuit for controlling the energization and
deenergization of a load comprising;
1. first signal-generating circuit means operative in response to a
first predetermined minimum input voltage to generate a first
predetermined output signal;
2. second signal-generating circuit means normally operative to
generate a second predetermined output signal, and further
operative in response to a second predetermined minimum input
voltage greater than said first predetermined minimum input voltage
to cease generation of said second predetermined output signal;
and
3. signal-responsive circuit means having first and second input
channels and being operative to alter the energization state of a
load only in response to the coincident application of said first
and second predetermined output signals to said first and second
input channels, respectively.
10. A control circuit according to claim 9 and further including a
voltage divider circuit comprising a fixedly connected resistor and
a selectively connectable keying resistor operative in combination
to provide at their junction an input voltage falling between said
first and second predetermined minimum input voltages.
Description
The present invention relates to a resistance-responsive control
circuit including discrimination and antitamper features.
Specifically, this circuit is designed to control the energization
state of a load, e.g., a solenoid-controlled door lock of an
automobile, by connecting a predetermined keying resistance falling
within a narrow range of resistances across a pair of terminals.
Preferably, the location of these terminals will not be readily
determinable by an unauthorized person. In any event, the anti
tamper feature will deter unlocking by connecting a variable
resistor across the terminals and hunting for the proper value of
resistance. Of course, the control circuit disclosed herein is
readily adaptable to a wide variety of applications, which include
controlling the closing of the ignition circuit of an automobile,
and controlling a lock on a garage door or on one or more doors
providing ingress to a house or a room within a house.
A better understanding of the present invention may be had by
reference to the drawing, which illustrates the preferred
embodiment of the present invention. The control circuit shown in
the drawing is constantly energized by a 12-volt direct current
source of electromotive force, the positive terminal of which is
connected to the circuit terminal T-1. The predetermined keying
resistance R-1 is connectable across terminals T-2 and T-3, thereby
forming a voltage divider circuit comprising resistances R-1 and
R-2 connected in series between ground and the line voltage applied
at terminal T-1. Terminals T-2 and T-3 are the input terminals of
the two-stage emitter-follower amplifier comprising transistors Q-1
and Q-2 and resistance R-3, the latter being connected in series
between the emitter of transistor Q-2 and ground. This amplifier
has a high input impedance between terminals T-2 and T-3 in order
to minimize the effects of current loading on the voltage developed
at the junction of resistances R-1 and R-2. The output of this
amplifier is derived at the junction of resistance R-3 and the
emitter of transistor Q-2.
When a keying resistance R-1 is connected across T-2 and T-3, a
predetermined input voltage is applied to the base of transistor
Q-1 which causes the positive output voltage of the
emitter-follower amplifier to decrease to a predetermined output
voltage. This output voltage controls the intermediate circuitry
controlling the state of the collector-emitter junctions of
transistors Q-6, Q-12 and Q-15, which are respectively connected in
series with the first, second and third input channels of AND-Gate
I comprising diodes D-1, D-2 and D-3, respectively. Transistors Q-6
and Q-15 are normally conductive to close shunt paths around the
bias current path formed by diode D-4 and resistance R-11 of
AND-Gate I. The state of transistor Q-6 is controlled by a first
amplifier consisting of transistors Q-3 and Q-4 and resistors R-4,
R-5 and R-6 and by a second amplifier consisting of transistor Q-5
and resistors R-7 and R-8. Resistance R-6 is connected to the base
of transistor Q-4 by a slidable tap, which enables the voltage at
the base of transistor Q-4 to be set so that the predetermined
output voltage generated by the emitter-follower amplifier in
response to insertion of a keying resistance R-1 between terminals
T-2 and T-3 will cause normally nonconductive transistors Q-3 and
Q-4 to become conductive. Current will then flow across resistance
R-5 to cause a positive voltage to be applied to the base of
transistor Q-5 through resistance R-7. Transistor Q-5 is thus
rendered conductive, and the voltage at the junction of resistance
R-8 and the collector of transistor Q-5 drops from essentially line
voltage to near ground potential, thereby causing transistor Q-6 to
become nonconductive. Thus, the current shunt path from the low
side of resistor R-10 through diode D-1 and the collector-emitter
junction of transistor Q-6 to ground is effectively opened, and no
longer shunts the current path from the low side of resistor R-10
through diode D-4 and resistor R-11 to ground.
The state of normally nonconductive transistor Q-12 is controlled
by the intermediate amplifier consisting of transistors Q-9 and
Q-10 and resistors R-16, R-20 and R-22. Resistance R-22 is
connected to the base of the transistor Q-10 by a slidable tap
which enables the voltage at the base of transistor Q-10 to be set
so that the predetermined output voltage generated by the
emitter-follower amplifier in response to insertion of a keying
resistance R-1 between terminals T-2 and T-3 will cause normally
nonconductive transistors Q-9 and Q-10 to remain nonconductive.
Under these conditions, no current flows across resistance R-20
which is connected between the collector of transistor Q-9 and
ground. Thus, the base of transistor Q-12 is at essentially ground
potential by virtue of the connection to ground through resistances
R-20 and R-21. Transistor Q-12 thus remains nonconductive, and the
bias current shunt path from the low side of resistor R-10 through
diode D-2 and the collector-emitter junction of transistor Q-12
remains open. Thus, the bias current path in AND-Gate I from the
low side of resistor R-10 through diode D-4 and resistor R-11 to
ground is not bypassed.
Transistor Q-15 and its biasing resistors R-31 and R-32 are
interconnected with a relaxation oscillator comprising unijunction
transistor (UJT) Q-16, resistances R-30, R-33 and R-34 and
capacitance C-3, the latter being connected between the emitter of
UJT Q-16 and the base of transistor Q-15. A third bias current
shunt path is formed by diode D-3 of AND-Gate I and the
collector-emitter junction of transistor Q-15, this path being in
parallel with the first and second bias current shunt paths formed
by diode D- 15, this path being in parallel with the first and
second bias current shunt paths formed by diode D-1 and the
collector-emitter junction of transistor Q-6 and by diode D-2 and
the collector-emitter junction of transistor Q-12, respectively.
The state of transistor Q-15 is controlled by an amplifier
comprising transistor Q-11 and biasing resistors R-15, R-17, R-18
and R-19. As with the other intermediate amplifiers controlling
transistors Q-6 and Q-12, this amplifier derives its input from the
emitter-follower amplifier whose output is controlled by the
resistance R-1 between terminals T-2 and T-3. Transistor Q-11 is
biased so that even a very small decrease in the positive output
voltage of the resistance sensing emitter-follower amplifier will
render the emitter-collector junction of transistor Q-11
conductive, thereby causing current flow through resistance R-18. A
positive voltage is thus applied to the cathode of diode D-15, the
anode of which is connected directly to the junction of capacitance
C-3 and the emitter of unijunction transistor Q-16. Thus, the shunt
path past capacitance C-3 through diode D-15 and resistance R-18 is
blocked, and since the parallel capacitance C-2 is normally charged
by current passing through resistance R-29, capacitance C-3 now
becomes charged by current flowing through variable resistance
R-30. The relaxation oscillator thus becomes oscillatory, with
capacitance C-3 periodically charging to the triggering voltage of
UJT Q-16 and discharging through the emitter and base No. 1 of UJT
Q-16 to ground. Consequently, the collector-emitter junction of
transistor Q-15 is periodically rendered nonconductive by the
negative voltage applied at the base of transistor Q-15 each time
capacitor C-3 charges.
Thus, with the first and second shunt paths being held constantly
open, positive voltage pulses will be applied to the base of
transistor Q-7 of N AND-Gate i each time the collector-emitter
junction of transistor Q-15 is rendered nonconductive, thereby
rendering the collector-emitter junction of transistor Q-7
conductive with the application of each positive voltage pulse to
its base. Thus, capacitance C-1 discharges rapidly to ground
through diode D-5 and the periodically conductive collector-emitter
junction of transistor Q-7. The voltage which was applied by
capacitor C-1 through resistor R-14 to the base of the
relay-controlling transistor Q-8 to become conductive. By adjusting
the value of variable resistor R-30 in the relaxation oscillator so
that capacitor C-3 charges more rapidly than capacitor C-1 is
charged through resistor R-13, transistor Q-7 is rendered
conductive with sufficient frequency to prevent capacitance C-1
from being charged to a level at which transistor Q-8 would become
nonconductive. The winding of the relay Re is thus constantly
energized, causing the relay contacts to close and energize the
load controlled thereby. Keying resistance R-1 may then be removed
from between the terminals T-2 and T-3, thereby causing transistors
Q-6 and Q-15 to return to their original state, i.e., having
constantly conductive collector-emitter junctions. Transistor Q-7
will consequently be rendered nonconductive, and capacitor C-1 will
be charged through resistance R-15 to turn off the
relay-controlling transistor Q-8.
The antitamper feature of the present invention resides in the
combination of AND-Gates II and III and the relaxation oscillator
comprising UJT Q-16. When the proper keying resistance R-1 is
connected between terminals T-2 and T-3, and transistors Q-6 and
Q-12 respectively become and remain nonconductive as described
earlier, the voltage at the junction of resistor R-26 and the
collector terminal of transistor Q-13 of AND-Gate II falls to
approximately ground potential in response to the coincident
positive voltages at the cathodes of diodes D-8 and D-9. Thus, a
bias current shunt path is closed through diode D-11 of AND-Gate
III and the collector-emitter junction of transistor Q-13 of
AND-Gate II. Thus, the collector-emitter junction of transistor
Q-14 of AND-Gate III is prevented from periodically being rendered
conductive by the periodic closing of the shunt path through diode
D-12 and the collector-emitter junction of transistor Q-15, since
the bias current path formed by diode D-13 and resistor R-28 is
shunted. Consequently, the normally charged capacitor C-2 connected
across the collector-emitter junction of transistor Q-14 will not
be able to discharge through that junction.
If the resistance R-1 were above the minimum value required to
effect unlocking, the decrease in the positive output voltage of
the emitter-follower amplifier will not be sufficient to cause
transistor Q-6 to become nonconductive. Consequently, the bias
current shunt path through diode D-1 and the collector-emitter
junction of transistor Q-6 remains closed and prevents transistor
Q-7 from becoming conductive. In addition, the shunt path through
diode D-8 of AND-Gate II and the collector-emitter junction of
transistor Q-6 remains closed, preventing transistor Q-13 from
becoming conductive.
A low value of resistance R-1 will result in an excessive decrease
in the positive output voltage of the emitter-follower, causing
transistor Q-12 to become conductive and thereby closing the bias
current shunt path through diode D-2 of AND-Gate I and the
collector-emitter junction of transistor Q-12. Thus, the shunt path
through diode D-9 of AND-Gate II and also closed. Consequently,
transistor Q-13 of AND-Gate II remains nonconductive, thereby
holding open the bias current shunt path through diode D-11 of
AND-Gate III and the collector-emitter junction of transistor
Q-13.
Under either of the foregoing conditions, i.e., whether resistance
R-1 is too high so as to cause the output voltage of the
emitter-follower amplifier to be higher than the predetermined
value and thereby maintain transistor Q-6 conductive, or whether
resistance R-1 is too low so as to cause the output voltage of the
emitter-follower amplifier to be lower than the predetermined value
and thereby cause transistor Q-12 to become conductive, only one of
the two required coincident inputs will be provided to AND-Gate II.
Consequently, the bias current path through diode D-10 and resistor
R-25 will remain shunted and transistor Q-13 will remain
nonconductive, thus providing one of the two required coincident
inputs to AND-Gate III by maintaining a high positive voltage at
the cathode of diode D-11. The second input to AND-Gate III is
provided by the periodically nonconductive transistor Q-15 which
causes transistor Q-14 to become periodically conductive each time
transistor Q-15 becomes nonconductive as a result of discharging of
capacitance C-3. It will be recalled that the bias voltages on
transistor Q-11 are such that virtually any decrease in the output
voltage of the emitter-follower amplifier will cause transistor
Q-11 to become conductive, thus placing the necessary positive
voltage on the cathode of diode D-15 to enable charging of
capacitance C-3 which in turn causes the relaxation oscillator to
become oscillatory. With transistor Q-14 now periodically
conductive, capacitor C-2 will discharge rapidly through the
collector-emitter junction of that transistor, the magnitude of
discharge current being limited only by the resistance of that
junction. Thus, capacitor C-2 becomes virtually completely
discharged very rapidly, and will shunt charging current from
capacitor C-3 during each hiatus between periods of conductivity of
transistor Q-14. Thus, the relaxation oscillator is rendered
nonoscillatory, and transistor Q-15 is again maintained
continuously conductive. Transistor Q-14 simultaneously becomes
nonconductive, since the bias current shunt path through diode D-12
and transistor Q-15 is again closed. Since capacitor C-2 is much
larger than capacitor C-3, it will continue to shunt most of the
charging current from C-3 after the discharge path through the
collector-emitter junction of transistor Q-14 is opened. The
relaxation oscillator is thereby disabled for a period of time on
the order of 40 seconds, during which the transistor Q-15 is
maintained constantly conductive. During this period of disability
of the relaxation oscillator, it is not possible to actuate the
load circuit even if the proper value of resistance R-1 is
connected between terminals T-2 and T-3. If a variable resistance
is connected between terminals T-2 and T-3 for the purpose of
hunting for the correct value of keying resistance R-1, and that
correct value is momentarily set, the period of time required for
the parallel-connected capacitors C-2 and C-3 to charge to a level
which will permit capacitor C-3 to render the relaxation oscillator
circuit oscillatory is sufficiently long that a different and
incorrect setting of the variable resistor will almost certainly be
reached before the end of that time period, resulting again in the
discharging of capacitor C-2 in the manner described above.
In the preferred embodiment of the invention shown in the drawing
and described herein, the values of the various circuit components
are as follows:
Resistances Capacitances R-1 50 k.OMEGA. C-1 10 microfarads R-2 50
k.OMEGA. C-2 100 microfarads R-3 1 k.OMEGA. C-3 5 microfarads R-4
100 k.OMEGA. R-5 100 k.OMEGA. R-6 1 k.OMEGA. R-6 10 k.OMEGA. NPN
Transistors R-8 10 k.OMEGA. R-9 10 k.OMEGA. 2N5135 R-10 10 k.OMEGA.
R-11 100 k.OMEGA. R-12 10 k.OMEGA. R-13 10 k.OMEGA. PNP-Transistors
R-14 10 k.OMEGA. R-15 100 k.OMEGA. 2N4248 R-16 100 k.OMEGA. R-17
1.5 k.OMEGA. R-18 R-26 k.OMEGA. R-19 4.7 k.OMEGA. Unijunction
Transistors R-20 100 k.OMEGA. R-21 10 k.OMEGA. 2N1671 R-22 1
k.OMEGA. R-23 10 k.OMEGA. R-24 k.OMEGA.10 k.OMEGA. R-25 100
k.OMEGA. Diodes R-26 10 k.OMEGA. R-27 10 k.OMEGA. 1N914 R-28 100
k.OMEGA. R-29 100 k.OMEGA. R-30 100 k.OMEGA. R-31 10 k.OMEGA. R-32
10 k.OMEGA. R-33 150 k.OMEGA. R-34 27 ohms
It will be readily appreciated that the disclosed circuit will
serve to perform a discrimination function with the third
signal-generating circuit and the antitamper circuitry omitted,
i.e., if transistors Q-11 and Q-15 and their bias circuitry were
eliminated along with AND-Gates II and III and the relaxation
oscillator, the remainder of the circuit will operate only in
response to the same predetermined range of keying resistances R-1.
In applications where the antitamper feature is not deemed
significant, this subcombination affords obvious economies. Certain
modifications of the disclosed circuit, e.g., the use of a latching
circuit with the relay Re, or connecting an alarm such as a buzzer
or a lamp in series with the collector-emitter junction of
transistor Q-14, may be desirable in diverse applications of the
disclosed circuit.
The advantages of the present invention, as well as certain changes
and modifications of the disclosed embodiment thereof, will be
readily apparent to those skilled in the art. It is the applicant's
intention to cover all those changes and modifications which could
be made to the embodiment of the invention herein chosen for the
purposes of the disclosure without departing from the spirit and
scope of the invention.
* * * * *