Fet Flip-flop Driving Circuit

Abstract

A driving circuit for driving a flip-flop comprising a pair of trigger circuits, each of which is composed of a gating insulated gate field effect transistor (referred to as IGFET hereinafter), memorizing IGFET and triggering one, said driving circuit comprising an inverter constituted by connecting first and second IGFET in series with each other, wherein the input of the inverter is connected in common with the inputs of said gating IGFET's, and the output of said inverter is connected in common with the inputs of said trigger IGFET's.

Description

This invention relates to a circuit for driving a flip-flop constituted by insulated gate field effect transistors.

It has been attempted to constitute a flip-flop circuit by the use of insulated gate field transistor devices such for example as metal-insulator-semiconductor field effect transistors (referred to as MIS transistor hereinafter). An example of such flip-flop circuit is disclosed in U.S. Pat. No. 3,363,115, for example. Advantageously, the MIS transistor can easily be integrated in a single semiconductor substrate, and the power consumption thereof is low because of the voltage-controlled type. Therefore, a flip-flop using such MIS transistors is also advantageous.

The inventor has observed the fact that erroneous operation id often caused when such a flip-flop as disclosed in the said patent is driven, and found that this is due to an undesirable timing relationship between a first pulse signal provided by a pulse source and a second pulse signal (inverted signal of said first signal). This will be more fully described hereinafter with reference to the drawings.

It is an object of the present invention to provide a driving circuit capable of preventing erroneous operation of a flip-flop constituted by insulated gate field effect transistors.

Another object of the present invention is to provide a transistorized flip-flop which can be operated with a low-voltage source.

A still another object of the present invention is to provide a flip-flop circuit arrangement which can easily be realized by the semiconductor integrated circuit technique.

Other objects, features and advantages of the present invention will become apparent from the following description taken in conjunction with the accompanying drawings, in which

FIGS. 1 and 10 are circuit diagrams showing flip-flop constituted by insulated gate-type field effect transistors, respectively;

FIG. 2 is a view showing input and output signal waveforms occuring in said flip-flops;

FIG. 3 and 4 are a schematic sectional view showing insulated gate-type field effect transistors incorporated in a semiconductor integrated circuit and an equivalent circuit diagram showing a trigger circuit including such portions (portions enclosed by dotted lines), respectively;

FIG. 5 is a view showing the operational range of a flip-flop with respect to a power supply;

FIG. 6 is a view showing a conventional flip-flop driving circuit;

FIG. 7 is a view showing input and output signal waveforms of the circuit shown in FIG. 6;

FIG. 8 is a circuit diagram showing the flip-flop driving circuit according to an embodiment of the present invention; and

FIG. 9 is a view showing input and output signal waveforms of the flip-flop shown in FIG. 8.

Referring to FIG. 1 of the drawings, there is shown a well-known flip-flop arrangement constituted by MIS transistors.

Such a flip-flop uses the gate capacitance of the MIS transistors as a temporary storage element so as to be able to produce binary counter action, and it is greatly advantageous over a binary counter flip-flop constituted by bipolar transistors in that the number of circuit elements can be remarkably reduced. A further advantage of such a flip-flop arrangement is that the manufacture thereof is facilitated in an attempt to assemble it in the form of a semiconductor integrated circuit since it is formed by MIS transistors.

In FIG. 1, T.sub.1 and T.sub.5 represent invertor MIS transistors, respectively, and T.sub.9 and T.sub.10 denote load MIS transistors of which the drains are connected with a DC power source terminal P, respectively. T.sub.4 and T.sub.8 indicate gate MIS transistors of which the gates are connected with a first pulse input terminal i, respectively. T.sub.3 and T.sub.7 represent memory MIS transistors adapted to produce a memory effect with the aid of gate capacitances C.sub.1 and C.sub.2 thereof, respectively, and T.sub.2 and T.sub.6 indicate trigger MIS transistors of which the gates are connected with a second pulse input terminal i', respectively.

By applying pulses which are 180.degree. out of phase with each other as shown at band ain FIG. 2 to the first and second pulse input terminals i and i' respectively, it is possible to obtain at output terminals 0 and 0' output pulse signals having a frequency which is one-half the frequency of the input pulse signals as shown at d and c in FIG. 2 respectively. Such a flip-flop is capable of producing binary counter action, and therefore it is possible to form any desired counter, shift register and so forth by cascading such flip-flops in the form of a flip-flop chain.

In an attempt to construct the foregoing flip-flop in the form of a semiconductor integrated circuit arrangement, however, it is essential that care be taken to minimize power consumption. That is, it is required that the operation be able to be performed even if the voltage of the power source V.sub.DD is low.

When the voltage of the power source V.sub.DD is low, "on" current flowing through the MIS transistors is decreased so that the power consumption in the flip-flop per se is reduced. This is advantageous in that a temperature rise can be prevented from occuring in the semiconductor integrated circuit device. When a chain of such flip-flops is integrated in a single semiconductor substrate, it is necessary to minimize power consumption so as to prevent heat generation, since MIS transistors are integrated in such a single substrate with a high density. To meet such a requirement, the flip-flop should be operated with a low-voltage source.

On the other hand, the above-described flip-flop has such a disadvantage that an input pulse signal voltage V.sub.IN for driving the gate MIS transistors T.sub.4 and T.sub.8 must be high.

That is, disadvantageously, that gate voltage of the gate MIS transistors T.sub.4 and T.sub.8 with respect to a reference potential which is needed to render these transistors conductive (such gate voltage will be referred to as threshold voltage) must be made higher (-13 V, for example) than twice the threshold voltage (-6 V, for example) of the memory MIS transistors T.sub.3 and T.sub.7, since the sources of the gate MIS transistors T.sub.4 and T.sub.8 are connected with the gates of the memory MIS transistors T.sub.3 and T.sub.7.

The reason is that since P-type regions 32 and 42 constituting the sources of a plurality of transistors T.sub.3 and T.sub.4 and P-type regions 33 and 43 forming the drains thereof are integrally formed in a single N-type silicon semiconductor substrate 31 and the semiconductor substrate 31 is connected with a reference potential source E through a terminal G.sub.2 as shown in FIG. 3, the threshold voltages of the transistors T.sub.4 (or T.sub.2) and T.sub.8 (or T.sub.6) of which the sources S are not connected directly with the reference potential source are influenced by the semiconductor substrate 31 so as to become higher than that of the transistor T.sub.3 (or T.sub.7), as shown in FIGS. 3 and 4. Empirically, a threshold voltage increases substantially in proportion to the square root of the reverse voltage between the substrate 31 and the source S. Therefore, the threshold voltages of the gate transistor T.sub.4 (or T.sub.8) is influenced by the substrate so as to become somewhat higher than twice the threshold voltage of the memory transistor T.sub.3 (or T.sub.7) having the source thereof connected directly with the reference potential source, as described above.

In contrast, the threshold voltages of the trigger MIS transistors T.sub.2 and T.sub.6 are not effected by the substrate 31 and assume a low value (-6V. for example) because the "on" operation of making the trigger transistor T.sub.2 or T.sub.6 conductive is limited to only when the memory MIS transistor T.sub.3 or T.sub.7 is rendered conductive, although the source of the MIS transistors T.sub.2 or T.sub.7 are connected to the potential source E through the path between the sources and the drains of the memory MIS transistors T.sub.2 and T.sub.6. Hence, the voltage required to obtain V.sub.IN becomes lower than V.sub.IN (1/2of V.sub.IN, for example).

From the foregoing, it will be seen that the above-described conventional flip-flop circuit is disadvantageous in that the input pulse signal voltage of V.sub.IN may be low but the input pulse signal voltage of V.sub.IN should be high.

Thus, in order to drive such a flip-flop with a low pulse signal voltage V.sub.IN, an attempt has conventionally been made to provide an inverter circuit 1 before a flip-flop 2 and drive gate MIS transistors T.sub.4 and T.sub.8 by the output of the inverter circuit, as shown in FIG. 6. The FIG. 6 arrangement is designed so that when a low pulse voltage V.sub.IN is applied as an input to the inverter circuit 1 having a high voltage source V.sub.GG, an inverted high voltage V.sub.IN is obtained at an output terminal O.sub.1 to drive the gate MIS transistors T.sub.4 and T.sub.8.

However, the inverter has found that in such a conventional flip-flop driving method, the possibility occurs that the following erroneous operation is performed by an inverter transistor T.sub.20.

By applying a pulse voltage V.sub.IN such as shown at a in FIG. 7 to the input terminal i.sub.1 of the inverter circuit, a inverted waveform V.sub.IN is produced in which a delay is caused in the rising and falling portions thereof as shown at b in FIG. 7. The rise time or period of time from a point of time t.sub.1 when the inverter transistor T.sub.20 is "off" to a point of time t2 when it is "on" depends upon the product of the "on" resistance on the inverter transistor T.sub.20 and input capacitance of the flip-flop 2 or the time constant. Such a rise time is so long that the gate MIS transistor T.sub.4 (or T.sub.8) tends to operate simultaneously with trigger MIS transistor T.sub.2 (or T.sub.6) during a time t.sub.off (see FIG. 7) when V.sub.IN is greater in the negative direction than the threshold voltage E.sub.th of the gate MIS transistor T.sub.4 (and T.sub.8) , thus resulting in erroneous operation. Such operation will be examined with reference to FIG. 7. It may be considered that at a point of time t.sub.1, the trigger transistors T.sub.2 and T.sub.6 are rendered conductive so that the states of the transistors T.sub.1 and T.sub.5 are reversed. Assume that the transistor T.sub.5 is switched from nonconducting state to conducting state, i.e., T.sub.1 is switched from conducting state to nonconducting state by the conduction of the trigger transistors T.sub.2 and T.sub.6 at the point of time t.sub.1. If the gate transistors T.sub.4 and T.sub.8 are turned off immediately at the point of time t.sub.1, then normal operation will be performed. However, since the transistors T.sub.4 and T.sub.8 are maintained in the "on" state due to the delay of the signal V.sub.IN during the time t.sub.off, the drain voltage ("off" level voltage) of the transistor T.sub.1 is applied to the gate of the memory transistor T.sub.3 through the gate transistor T.sub.4 during said time t .sub.off, so that the transistor T.sub.3 is immediately turned on. On the other hand, at this time, the transistor T.sub.2 is in the conducting state. Thus, the transistor is again returned from its "off" state to its "on" state. That is, the transistor is reversed from "on" state to its "off" state at the point of timet.sub.1, but it is again returned to its "on" state by a point of time t.sub.4, thus resulting in erroneous operation.

As a result of such erroneous operation, the operational range of the flip-flop with respect to the supply voltage is reduced. FIG. 5 shows the operational range 10 of the flip-flop 2 (operating portion is shown by oblique lines), with the supply voltage V.sub.DD for the flip-flop 2 indicated on the horizontal axis and the supply voltage V.sub.GG for the inverter circuit on the vertical axis.

As will be seen from FIG. 5, the range of V.sub.GG which can be selected is limited when V.sub.DD is lower than -25 V for example, and the flip-flop is stopped from operation when V.sub.GG, the level of the output voltage V.sub.IN of the inverter is increased up to -E' .sub.2 as show by a broken curve at b in FIG. 7, so that the time t.sub.off is extended as indicated by t'.sub.off (t.sub. t.sub.3), thus increasing the possibility of erroneous operation. Conversely, this means that the voltage V.sub.DD cannot be made lower than a certain limit determined from the relationship with V.sub.GG in case V.sub.GG is lower than -35 V for example.

The present invention has been made through experiments and research conducted in view of the fact that the period of time required for permitting the memory MIS transistor to switch from its "on" to its "off" state after applying a pulse voltage to the gate MIS transistor is longer than that for permitting the trigger transistor to switch from its "off" to its "on" space, and it is characterized in that the trigger MIS transistors are driven by the output of a inverter circuit constituted constituted by MIS transistors, and that the inputs of the gate MIS transistors are made common to that of the inverter circuit.

The present invention will be more fully understood from the following description.

FIG. 8 shows an embodiment of the present invention, wherein parts corresponding to those of FIG. 6 are indicated by similar symbols. An inverter circuit 3 provided in accordance with the present invention includes an invertor MIS transistor T.sub.30 and a load MIS transistor T.sub.31 therefor. Output terminal O.sub.2 of the inverter circuit 3 is connected with the gates of the trigger MIS transistors T.sub.2 and T.sub.6, and the gates of gate MIS transistor T.sub.4 and T.sub.8 are connected with input terminal 2.sub.2 of the inverter circuit 3.

Description will now be made of the operation of the present invention. For the simplicity of explanation, it is assumed that a perfect pulse voltage V.sub.IN such as shown at b in FIG. 9 is obtained at the input terminal i.sub.2 of the inverter circuit 3 in common with the input terminal i for the gate transistors T.sub.4 and T.sub.8. The pulse voltage is reversed and delayed by the inverter circuit 3 so that such a signal V.sub.IN as shown at a in FIG. 9 is obtained at the output terminal O.sub.2 of the inverter circuit 3. The inverted signal V.sub.IN is imparted to the input of the trigger transistor T.sub.2 and T.sub.6. Assume that the inverter MIS transistor T.sub.1 of the flip-flop 2 is turned on (hence T.sub.5 is turned off) between points of time t.sub.1 and t.sub.2 in FIG. 9. Then, a voltage V.sub.D is produced at the drain of T.sub.5, and the drain of T.sub.1 is maintained at a reference potential. At this point, since the gate MIS transistors T.sub.4 and T.sub.8 are conducting, the drain voltage V.sub.D of T.sub.5 is stored at gate capacitance C.sub.2 of the memory MIS transistor T.sub.7, whereby the latter is turned on. Further, the gate voltage of T.sub.3 is reduced to zero. After T.sub.4 and T.sub.8 are turned off at t.sub.2 T.sub.2 and T.sub.6 are turned on at t.sub.3. Thus, with this arrangement, there occurs no such inconvenience as involved in the conventional arrangement (see FIG. 7 a, b).

Between points of time t.sub.3 and t.sub.4, the trigger MIS transistors T.sub.2 and T.sub.6 are turned on, so that the inverter MIS transistor T.sub.5 is turned on while T.sub.1 is turned off by the conduction of T.sub.6 and T.sub.7. Thus, the states of T.sub.1 and T.sub.5 are reversed by the pulse voltage V.sub.IN applied to the trigger MIS transistors T.sub.2 and T.sub.6.

The trigger MIS transistors T.sub.2 and T.sub.6 are still conducting between points of time t.sub.4 and t.sub.5, and at the point of time t.sub.4, the pulse voltage V.sub.IN is applied to T.sub.4 (and T.sub.8) to turn of the latter. Therefore, it is considered that the possibility may occur that T.sub.3 is turned on while T.sub.7 is turned off. However, the period of time from when V.sub.IN is actually applied to the input terminal ito when T.sub.3 is turned on (the sum of the period of time required to turn on T.sub.4 and that required to turn on T.sub.3) becomes longer than the period of time t.sub.off indicated in FIG. 9, so that that memory MIS transistor T.sub.3 is turned on and T.sub.7 is turned off after the trigger MIS transistors T.sub.2 and T.sub.6 are turned off at the point of time t.sub.5. Consequently, there occurs no such erroneous operation that the trigger MIS transistor T.sub.2 and memory MIS transistor T.sub.3 are simultaneously turned on between the points of time t.sub.4 and t.sub.5.

In accordance with the present invention, it is possible to prevent such erroneous operation as with the conventional arrangements, since the flip-flop is reversed by rendering the trigger MIS transistor conductive after the gate MIS transistors have completely been turned off, subsequently the trigger MIS transistors are again turned off, and thereafter the gate MIS transistors are turned off, as described above.

The operational range 11 is indicated by the broken line in FIG. 5 corresponds to the case where the present invention is applied. From this, it will be seen that in accordance with this invention, the operational range with respect to the supply voltage can be made wider than that of the prior art arrangement, and that operation can be performed even with a low voltage. In this case, the lower limit of V.sub.DD corresponds to the minimum value at which the trigger MIS transistors of the succeeding flip-flop can be driven in the circuit arrangement of FIG. 8, and the lower limit of V.sub.GG corresponds to the minimum value at which the gate MIS transistors of the succeeding flip-flop can be operated in the circuit arrangement of FIG. 8.

Therefore, the present invention can be effectively applied to applications in which the flip-flop chain is constituted by the use of a multiplicity of flip-flops 2. With a flip-flop chain, it is required that the output pulse voltage V'.sub.IN available at the output terminal O' of a flip-flop 2 be converted to the high pulse voltage V.sub.IN between the flip-flop stages since the succeeding flip-flop should be driven by said output voltage. To meet this requirement, the inverter circuit 1 and the inverter circuit 3 according to the present invention are provided between a first flip-flop stage and a second flip-flop stage. The resulting flip-flop chain can be satisfactorily operated with a lower value for the supply voltage V.sub.DD of the flip-flop than in the case of the conventional device, as will be seen from FIG. 5. Thus, it will be appreciated that power consumption in the flip-flop chain can be reduced, and that the flip-flop can easily be constructed by the integrated circuit technique.

To sum up, the present invention is characterized in that gate MIS transistors are driven by an input pulse voltage of the inverter circuit and trigger MIS transistors are driven by the output pulse voltage of the inverter circuit. Of course, this invention may also be applied to a flip-flop 2 using a single trigger MIS transistor T'.sub.2 as shown in FIG. 10.

Claims

What is claImed is:

1. In combination, a flip-flop constituted by cross-connecting the inputs and outputs of first and second inverter stages each comprising a field effect transistor and load impedance means;

a first trigger circuit connected with the output of said first inverter stage and the input of said second inverter stage, said first trigger circuit being constituted by a first insulated gate field effect transistor, a second insulated gate field effect transistor having a path between the source and the drain thereof connected between the drain of said first transistor and the output of said first inverter stage, and a third insulated gate field effect transistor having the path between the source and the drain thereof connected between the gate of said first transistor and the output of said first inverter stage;

a second trigger circuit connected between the output of said inverter stage and the input of said first inverter stage, said second trigger circuit being constituted by a fourth insulated gate field effect transistor, a fifth insulated gate field effect transistor having the path between the source and the drain thereof connected between the drain of said fourth transistor and the output of said second inverter stage, and a sixth insulated gate field effect transistor having the path between the source and the drain thereof connected between the gate of said fourth transistor and the output of said second inverter;

a third inverter stage comprising a transistor and a load impedance means, the input of said third inverter stage being connected in common with the gates of said third and sixth transistors and the output thereof being connected in common with the gates of said second and fifth transistors; and

a pulse signal source connected with the input of said third inverter stage.

2. The combination according to claim 1, wherein a fourth inverter stage is connected between the input of said third inverter stage and said pulse signal source, said fourth inverter stage is constituted by a transistor, load impedance means thereof and a first power source, and a second power source is connected in common with said first, second and third inverter stages.

3. The combination according to claim 2, wherein all the impedance means are constituted by insulated gate field effect transistors, and the transistors constituting the first, second and third inverters are insulated gate field effect transistors.

4. In combination, a flip-flop constituted by cross-connecting the inputs and outputs of first and second inverter stages each comprising a field effect transistor and a load impedance;

a first and second insulated gate field effect transistors each having the drain thereof connected with the output of the first inverter stage and the input of the second inverter stage, the gate of the second transistor being connected with the source of the first transistor;

third and fourth insulated gate field effect transistors each having the drain thereof connected with the output of the second inverter stage and the input of the first inverter stage, the gate of the fourth transistor being connected with the source of the third transistor;

a fifth insulated gate field effect transistor having the drain thereof connected with the sources of said second and fourth transistors;

a third inverter stage comprising a transistor and load impedance means, the input of said third inverter stage being connected in common with the gates of said first and third transistors and the output thereof being connected with the gate of said fifth transistor; and

a pulse signal source connected with the input on said third inverter stage.

5. A combination according to claim 4, wherein a fourth inverter stage is connected between the input of said third inverter stage and said pulse signal source, said fourth inverter stage comprising a transistor, load impedance means therefor and a first power source, and wherein a second power source is connected in common with said first, second and third inverter stages.

6. The combination according to claim 5, wherein all the impedance means are constituted by insulated gate field effect transistors, and the transistors which constitute the first, second and third inverters are insulated gate field effect transistors.

7. The combination comprising a first and a second switching means; means interconnecting said first and second switching means to form a flip-flop circuit; a first and a second memory circuit connected to said first and second switching means, respectively, each of said first and second memory circuits comprising a first insulated gate-type field effect transistor for memorizing the state of said flip-flop circuit and a second insulated gate-type field effect transistor having two output terminals, one of said output terminals of said second transistor being connected to the gate electrode of said first transistor;

a trigger circuit coupled to said first and second memory circuits for controlling the state of said flip-flop circuit, said trigger circuit comprising at least one third insulated gate-type field effect transistor connected in series with said first transistor of said respective memory circuits; an inverter circuit including a fourth insulated gate-type field effect transistor having two output terminals and a load impedance means therefor; means for electrically connecting the gate electrode of said fourth transistor to the gate electrodes of said second transistor of said respective memory circuits; means for electrically connecting one of said output terminals of said fourth transistor to the gate electrode of said at least one third transistor; and means for supplying a pulse signal to the gate electrode of said fourth transistor.

8. The combination according to claim 7, further comprising a second inverter circuit including a fifth insulated gate-type field effect transistor having two terminals and a second load impedance means therefor, and means for connecting the gate electrode of said fourth transistor with one of said fifth transistor, whereby said pulse is applied to the gate electrode of said fourth transistor through said second inverter circuit.

9. The combination according to claim 8, wherein said flip-flop circuit and said first inverter circuit are operated by a first voltage-supplying source and said second inverter circuit is operated by a second voltage-supplying source having a voltage value higher than said first voltage-supplying source.

10. The combination comprising a first and a second switching means; means interconnecting said first and second switching means to form a flip-flop circuit; a first and a second circuit means for controlling the state of said flip-flop circuit connected to said first and second switching means, respectively, each of said circuit means comprising a first, a second and a third insulated gate-type field effect transistor, each transistor having a gate electrode and two output terminals, means for connecting said first and second transistors in series, means for connecting the gate electrode of said first transistor with one of said output terminals of said third transistor; an inverter circuit means having an input terminal and an output terminal; means for electrically connecting said input terminal of said inverter circuit means with said gate electrodes of said third transistors; means for electrically connecting said output terminal of said inverter circuit means with said gate electrodes of said second transistors; and means for supplying a control signal to said input terminal of said inverter circuit means.

11. The combination as claimed in claim 10, wherein said control-signal-supplying means comprises a second inverter circuit means having an input terminal and an output terminal and means for connecting said output terminal of said inverter circuit means to said input terminal of said first inverter circuit means, whereby said control signal is applied to said input terminal of said first inverter circuit means through said second inverter circuit means.

12. The combination according to claim 11, further including means for supplying a DC voltage to said second inverter means which is higher than the voltage applied to said flip-flop circuit and said first inverter circuit means.

13. The combination according to claim 11, wherein each of said first and second inverter circuit means comprises an insulated gate-type field effect transistor and a load impedance means.

14. The combination comprising, a first, a second and a third insulated gate-type field effect transistor each having an input terminal and two output terminals; means for connecting the output terminal of said first transistor to one of said output terminals of said third transistor; means for connecting one of said output terminals of said first transistor to one of said output terminals of said second transistor; means for supplying an operating source voltage between the other of said output terminals of said first transistor and the others of said output terminals of said second and third transistors through an impedance means; means for supplying a first pulse signal to said input terminal of said third transistor; and means for supplying a second pulse signal to said input terminal of said second transistor, said second pulse signal being inverted and delayed in phase with respect to said first pulse signal, wherein said first and second pulse-signal-supplying means comprise a fourth insulated gate-type field effect transistor having an input terminal and two output terminals, means for supplying a second operating source voltage between said two output terminals through a second impedance means, means for connecting one of said output terminals of said fourth transistor to said input terminal of said second transistor, means for connecting said input terminal of said fourth transistor to said input terminal of said third transistor and means for impressing an input signal on said input terminal of said fourth transistor.

15. The combination comprising a first, a second and a third insulated gate-type field effect transistor, each having an input terminal and to output terminals; means for connecting the input terminal of said first transistor to one of said output terminals of said third transistor, means for connecting one of said output terminals of said first transistor to one of said output terminals of said second transistor; means for supplying an operating source voltage between the other of said output terminals of said first transistor and the others of said output terminals of said second and third transistors through an impedance means; means for supplying a first pulse signal to said input terminal of said third transistor; and means for supplying a second pulse signal to said input terminal of said second transistor, said second pulse signal being inverted and delayed in phase with respect to said first pulse signal, wherein said first and second pulse-signal-supplying means comprise a fourth and a fifth insulated gate-type field effect transistor, respectively, each having an input terminal and two output terminals, means for connecting said input terminal of said fourth transistor to one of said output terminals of said fifth transistor, means for connecting said input terminal of said second transistor to one of said output terminals of said fourth transistor, means for connecting said input terminal of said third transistor to said input terminal of said fourth transistor, means for supplying a second and a third operating source voltage between said two output terminals of said fourth and fifth transistors through a second and a third load impedance, respectively, and means for impressing an input signal on said input terminal of said fifth transistor.

16. The combination according to claim 15, wherein the value of said third operating source voltage for operating said fifth transistor is larger than that of said second operating source voltage for operating said fourth transistor and that of said first operating source voltage for operating said first, second and third transistors.