Zero Deadband Reversing Control

Abstract

In a reversible phase controlled rectifier control system, zero deadband response is realized by generating overlapping firing waves for forward current and reverse current conducting controlled switch elements of the phase controlled rectifier and controlling the direction of load current flow substantially instantaneously to provide for current to flow alternately in both directions when the system is in a quiescent state. An oscillator driven flip-flop gates firing between forward current and reverse current conducting controlled switch elements to provide immediate current direction control and lockout. The oscillator is responsive to the state of conduction of the controlled switch elements, permitting the firing signals to pass to forward current conducting controlled switch elements when reverse current conducting controlled switch elements are nonconductive and vice versa. The oscillator drives the flip-flop between its stable states at a high rate when all controlled switch elements are nonconductive so that the control system is substantially instantaneously responsive to a command for current to flow in either direction.

Description

FIELD OF THE INVENTION

This invention relates to control circuits for phase controlled rectifiers. More specifically, it relates to such control circuits for reversible phase controlled rectifiers in which there is a zero deadband response to phase advance or retard commands.

HISTORY OF THE ART

In reversible phase controlled rectifiers, time delays and/or deadbands, i.e., regions of no response, are often experienced when the system is commanded to change its level or reverse its direction. One reason for such time delays and deadbands is that in some phase controlled rectifiers a quiescent condition, i.e., a command satisfied condition, requires all controlled switch elements of the phase controlled rectifier to be nonconducting and therefore a finite voltage command must appear before the circuit can respond. Thus, there is a signal level deadband. Because commands applied to the system are in many applications not instantaneous but change levels at controlled rates, this signal level deadband takes finite time to be traversed by the command and a time deadband before the system responds is realized. In many systems this time deadband is longer than several cycles of the AC source being rectified.

A primary problem with phase controlled rectifiers is the need to avoid turning on both forward current and reverse current conducting controlled switch elements at the same time. If this condition does exist even momentarily, the power source is short circuited. A solution to this problem, as mentioned above, is to require that all controlled switch elements are nonconducting before the system will respond to a command requiring current reversal. In such systems another time delay is realized by the method of determining when all controlled switch elements are nonconducting.

The nonconduction of the controlled switch elements of a phase controlled rectifier is often detected by observing load current. When the load current is substantially zero, it is assumed that all controlled switch elements are off and it is safe to turn the opposite current conducting elements on. This is not a completely reliable assumption, however, when the switch elements are silicon controlled rectifiers where the holding current, i.e., the lowest current that a controlled rectifier will conduct in the "on" state, in some cases approaches the level of the device's leakage current, i.e., the current that flows when the device is "off." Accordingly, even when a substantially zero load current level is detected, a delay is employed prior to turning on the controlled rectifiers to give added insurance that all controlled rectifiers are off.

SUMMARY OF THE INVENTION

It is accordingly an object of the present invention to provide a control circuit for a reversible phase controlled rectifier in which delay times in response are virtually eliminated. Another object is to provide a control circuit for a reversible phase controlled rectifier having zero deadband response to phase advance or retard commands. In general, these objects are realized by providing a range of control about each quiescent point (when the parameter in the load being controlled substantially satisfies the command), where zero current to the load is achieved by the average of nonsimultaneous current conduction in both directions during each half cycle of the alternating voltage being rectified. Such a range of either direction conduction is achieved by phase overlap of the firing waves for pairs of forward and reverse current conducting controlled switch elements of the phase controlled rectifier. Once it is made possible to conduct in either direction, the opportunity for a line to line short by having simultaneous conduction of a forward current conducting controlled switch element and a reverse current conducting controlled switch element and a reverse current conducting controlled switch element becomes much more likely. Accordingly, rapid response current direction control is also required. This is provided by an oscillator driven flip-flop which oscillates between a state which inhibits forward current conduction to a state which inhibits reverse current conduction. To avoid the delays of the methods normally employed for zero current detection, absolute information is provided by a voltage threshold detecting circuit which responds to the voltage across the individual controlled switch elements. Voltage detection avoids the guess between holding current or leakage current. If the voltage is below the threshold level, the controlled switch element is conducting. If the voltage is above the threshold level, the controlled switch element is blocking. The information is therefore accurate and no delays are needed before it can be accepted.

BRIEF DESCRIPTION OF THE DRAWINGS

The objects and advantages of the present invention will be better understood from a detailed description of exemplary embodiments thereof as shown in the drawings, in which:

FIG. 1 is a schematic diagram of a phase controlled rectifier suitable for use with the system shown in FIG. 4;

FIG. 2 is a schematic diagram of a voltage detector employed to detect the state of conduction of the controlled switch elements of the FIG. 1 power circuit;

FIG. 3 is a truth table showing information obtained from the voltage detector of FIG. 2;

FIG. 4 is a block diagram of a control system in accordance with the present invention;

FIG. 5 is a line diagram illustrating the conduction cycle of one controlled switch element in response to various control conditions;

FIG. 6 is a line diagram illustrating the conduction cycle of controlled switch elements in the power circuit in response to various control conditions; and

FIG. 7 is a block diagram of an alternative embodiment of current direction control.

DETAILED DESCRIPTION

A typical phase controlled rectifier power circuit 10 of the prior art is shown in FIG. 1. Here four controlled rectifiers SCR1, SCR2, SCR3 and SCR4 apply full wave single phase reversible rectified current to a load 5 which is shown as the armature of a direct current motor. A transformer T1 applies alternating voltage to the bridge circuit from a source not shown. The primary T1P of the transformer is connected directly to the source and the secondary T1S is shown applying the full wave voltage to SCR1 and SCR2, which may be designated as a group of forward current conducting controlled switch elements, and also to SCR3 and SCR4, which are the reverse current conducting counterparts. The designation of forward and reverse current is completely arbitrary and is only stated for convenience of description.

The load 5 is shown connected between the center tap 6 of secondary winding T1S and an electrical common 7 which may be ground as shown. This particular power circuit with the transformer input which permits the grounding of the load and the bridge is not necessary for the control system to be described. It does, however, provide the single access points 8 and 9 for detection of the voltage across the controlled rectifiers by a relatively simple voltage threshold detector such as shown in FIG. 2 and is therefore preferred.

While silicon controlled rectifiers (SCR's) are shown in the power circuit of FIG. 1 and the term SCR employed throughout the description, this is only one kind of controlled switch element capable of blocking or passing current in response to a control signal. The term controlled switch element is used to represent all such devices which make up a phase controlled rectifier including transistors and all controllable thyristors.

Referring now to FIG. 2, there is shown a voltage threshold detector used to determine the state of conduction of the SCR's in the power bridge of FIG. 1. FIGS. 2 and 3 are considered together for ease in understanding the operation of the voltage detector. It should be understood that input point 9 of the circuit shown in FIG. 2 is access point 9 of the power bridge. The circuit shown is identical in all respects to its twin which monitors SCR1 and SCR3 from access point 8. Likewise, while FIG. 3 shows the voltage conditions for varying inputs at point 9, the same points in the circuit monitoring access point 8 would have duplicate information at the various points shown in the table of FIG. 3.

The primary purpose of the circuit shown in FIG. 2 is to determine when all SCR's are in the off or blocking state. This information is obtained from the output 22 of the voltage detector 23 and output 22' of voltage detector 23'. The three conditions that can be presented to circuit 23, as shown in the first column "9" of FIG. 3, are voltage less than the threshold level (shown as 0); voltage more positive than the threshold level (shown as+); and voltage more negative than the threshold level (shown as -). These three distinct input conditions produce acceptable "high" or positive outputs for voltage more positive than the threshold level, signifying that SCR4 is blocking and for voltage more negative than the threshold level signifying that SCR2 is blocking. The "low" output signifies that either SCR4 or SCR2 is conducting. A "high" will appear as a positive voltage to which AND gate 45 in FIG. 4 will respond, and a "low" will appear as substantially zero voltage, i.e., positive logic is assumed throughout the description.

The primary elements of conduction detector 23 are NAND gates 10 and 11 and Zener diodes 13 and 14. The Zener diodes establish the threshold level of the circuit and directly respond to the input voltage. When the input voltage at 9 is zero, i.e., less than the Zener 13, Zener 14 breakdown voltage, no current i.sub.1 flows due to the blocking action of either Zener diode 13 if the input voltage is positive or diode 15 if the input voltage is negative, and a current i.sub.2 will flow from the NAND gate 10 input 17 through resistor 16 to the common. Current i.sub.2 is of small value and the input to NAND gate 10 is considered "low." The inverting action of NAND gate 10 and the isolation provided by diode 21 cause both inputs 18 and 19 to NAND gate 11 to be "high." Output 22 of NAND gate 11 is accordingly "low."

When a positive voltage sufficient to overcome the value of Zener diode 13 appears at input 9, a current i.sub.1 will flow through resistor 12, Zener diode 13, diode 15 and resistor 16 to ground. This will establish a positive voltage or "high" at NAND gate input 17. The inverting action of NAND gate 10 will produce a low voltage at input 18 to NAND gate 11 and output 22 will reflect this input as a "high."

When the input voltage 9 goes negative and exceeds the breakdown voltage of Zener diode 14, current will flow from input 19 of NAND gate 11 through diode 21, Zener diodes 14 and 13 and resistor 12 to the input, resulting in a signal logic "low" at the input 19 to NAND gate 11. This "low" input to the NAND gate produces the inverted "high" output at point 22. The table in FIG. 3 can be consulted to recognize all of the logic conditions of this threshold circuit. Note that Zener diode 20 is not necessary for operation but merely protects both NAND gates from overvoltage.

It should be noted that the full wave power bridge with a common ground point shown in FIG. 1 permits easy access to the SCR's and the single input circuit of FIG. 2 can be employed. This is not the only voltage threshold detector which can be used with the FIG. 1 power circuit, nor would it be used in the form shown with a power circuit not employing a common ground point. Many other voltage threshold detector circuits are suitable for this application.

Turning now to FIG. 4, there is shown a system for controlling a reversible phase controlled rectifier with zero deadband response. The phase controlled rectifier may be the full wave bridge rectifier power circuit shown in FIG. 1 or, with slight modification, any single or multiphase full or half wave controlled rectifier. While FIG. 1 shows a motor as the load and motor speed as the load parameter being controlled, it is intended that the concept of zero deadband response and the techniques for achieving it can be obtained regardless of the load or parameter being controlled.

FIG. 4 shows a command from speed reference 30 being summed with a speed feedback indication at speed node 31. The speed reference block 30 represents a source of voltage such as may be derived from a potentiometer and a direct voltage source, the output of a tachometer coupled to another motor, or any other source of direct voltage. A control function is developed at the speed node 31 which is the difference between the actual value of the parameter being controlled (indicated by the speed feedback line, which may be from a tachometer generator coupled to the motor), and the desired value of that parameter as generated by speed reference circuit 30. The control function is amplified by the speed error amplifier 32 and is shown being applied to current summing node 33 as a current reference. A current feedback signal derived from a monitoring device in the load circuit (not shown) is summed with the current reference and the resulting current error is amplified by current error amplifier 34.

The control function appearing at the output of amplifier 34 is applied to individual comparators 1, 2, 3 and 4 for each of the corresponding SCR's in the power circuit. This control function is a variable direct voltage having a level proportional to the change required in the power applied to the load to correct the parameter being controlled to the desired value. The comparators convert the control function into a firing time for firing the SCR's. While the control function is shown as a resultant error signal in a closed loop system, it is to be understood that the zero deadband control circuit could respond directly to the command generated by reference circuit 30 in an open loop system.

Along with the control function, a timing function is applied to the comparators. This timing function is a signal that relates the control function to the alternating voltage being rectified so that the firing of the SCR's is synchronized with the alternating voltage applied thereto. Dual ramp generator 35 generates this timing function. The timing function, as can be noted from curves 61 and 62 in FIG. 6, is made up of two sawtooth voltages or ramp functions. Each ramp extends for 360.degree. or one complete cycle of the alternating voltage being rectified and the two different functions, 61 for SCR1 and SCR4 and 62 for SCR2 and SCR3, are 180.degree. out of phase. A more appropriate observation is that the two ramp functions overlap by 180.degree.. It is noted that at least 270.degree. of each 360.degree. ramp is needed to control each SCR and that each ramp is 90.degree. out of phase with the related alternating voltage so that each ramp ends at the end of the period of possible SCR conduction. It is desired to have control throughout the rectifying range, which extends 180.degree. in advance (to the left) of the zero crossing of each AC cycle, and throughout the regenerative or inverting range, when the counter electromotive force of the motor is negative, which extends 90.degree. behind (to the right of) the zero crossing point.

Dual ramp generator 35 is made up of components well known in the art. It includes a zero crossing detector, i.e., a polarity or voltage threshold sensitive circuit, responsive to the zero crossings of each of the two phases of the alternating voltage applied to the SCR's by transformer T1.sub.1 to synchronize each ramp with the alternating voltage applied to the SCR, two sawtooth waveform generators and two 90.degree. phase shift circuits. The two outputs from dual ramp generator 35 are indicated as 35a and 35b in FIG. 4. These two outputs are phase displaced 180.degree. and as such are ramp function 61 as shown in FIG. 6, applied to comparators 1 and 4 from output 35a, and ramp function 62 applied to comparators 2 and 3 from output 35b.

It is noted that the control function from current error amplifier 34 is applied directly to comparators 1 and 2 and inverted by inverting amplifier 36 prior to being applied to comparators 3 and 4. The inversion permits a phase advance command to advance the firing of the forward current conducting SCR's and to retard the firing of the reverse current conducting SCR's a like amount. This will be more readily apparent by reference to FIG. 6 and the description of that FIG. below.

A source of direct voltage bias from supply 37 is also applied to each of the comparators. Thus, the direct voltage bias, the control function and the timing function constitute the three inputs to each of the comparators. Each comparator may consist of a summing network and an amplifier responsive to the polarity of the summed voltage at its input. The amplifier saturates to produce a low voltage output when the input sum is of one polarity and is nonconductive to produce a higher voltage output when the input sum is of the opposite polarity. Such circuits are well known in the art as switching amplifiers. Such amplifiers may also be used with a voltage threshold device at the input so that they respond to level change above or below the threshold instead of polarity change.

Other level sensitive devices of the prior art could also be used for the comparators. For example, each comparator could comprise a differential amplifier with the DC bias and control function summed at one input and the timing ramp function applied to the other input so that an output is generated when the level of the timing function exceeds the level of the combined control function and bias.

Before continuing with the description of the system shown in FIG. 4, the function performed by the comparators should be well in mind. In passing, however, it should be noted that the outputs of the comparators are applied to pulse generators 46, 47, 48 and 49 to fire the SCR's in the power bridge when permitted by AND gates 38, 39, 40 and 41. Reference is had to FIGS. 5 and 6 for a graphic showing of the operation of the comparators and the relationship of the DC bias, the control function and the timing function to produce zero deadband firing control of the SCR's of phase controlled rectifier 10.

FIG. 5 illustrates how the change in DC level of the timing function affects the firing of the SCR. This FIG. shows the alternating voltage waveforms, 50 in solid line and 51 in dashed line, as applied to the phase controlled rectifier power bridge by transformer secondary winding T1S FIG. 5 is divided into three illustrations, (a), (b) and (c), each showing sawtooth waveform timing function 61 as applied to comparator 1 with its DC level altered by the sum of the control function and DC bias. Horizontal line 52 indicates the fixed threshold level of the comparator in each of the portions of the FIG. and line graphs 53--55 show the resulting firing periods for SCR1.

In FIG. 5a the level of the ramp 61 is such that the ramp crosses the threshold level of the comparator, as indicated by line 52, at point a, approximately 45.degree. in advance of zero crossing point x of alternating voltage 50. When the ramp exceeds the threshold level of the comparator of fire condition indication is generated by the comparator and a pulse can be applied to fire SCR1. Line graph 53 shows the resulting SCR1 firing period.

FIG. 5b shows a higher DC level timing ramp which crosses the threshold level 52 sooner. The more advanced crossing at "b" causes the conduction period of SCR1 to begin 135.degree. in advance of the zero crossing point x. This is shown by line graph 54.

FIG. 5c shows a lower DC level timing ramp crossing the threshold level late in the cycle of alternating voltage 50 at point c. Line graph 55 shows that the conduction period of SCR1 now commences 45.degree. after the zero crossing point x.

Several things can be observed. Either the DC level of the timing ramp function can change, as shown in FIG. 5, or the DC level of the threshold level of the comparator can change. In the preferred embodiment where the DC bias, the control function, and the timing function are summed and applied to a switch amplifier, it is the timing function that has its DC level altered by the bias and control function. This command information bearing sawtooth waveform is compared with the fixed threshold level of the amplifier or a zero volt level which renders the switching amplifier of the comparator polarity sensitive. Where the comparator comprises a differential amplifier, the threshold level is established by the changing level of the bias and control function and the timing ramp remains constant in its DC level.

Again with reference to FIG. 5a, consider that this represents a quiescent condition, i.e., the previous command or control condition has been satisfied and the 45.degree. advance firing is just sufficient to compensate for system losses. Now assume the command calls for an increase in speed. Consider that FIG. 5b represents the response of SCR1 to this command and FIG. 5c shows the response of SCR4. This is an illustration of how the control system actually responds to such a command. Because of the inversion of the control function signal as it is applied to the comparators for SCR3 and SCR4, the firing of these controlled switch elements is retarded by the same amount as the firing of SCR1 and SCR2 is advanced.

A clearer picture of the quiescent condition, zero deadband, the effect of the DC bias, and the effect of the counter electromotive force of the motor (CEMF) is shown in FIG. 6.

In FIG. 6 sinusoidal waveforms 50 and 51, indicating the alternating voltage applied to the phase controlled rectifier, are again shown. Here, for each of the four situations illustrated, the ramp timing functions 61 and 62 are of a constant level and are shown being compared with the combined control function and DC bias, represented by line 64 for SCR1 and SCR2 and line 66 for SCR3 and SCR4, which serves as the threshold levels for the comparators. The difference in level of thresholds 64 and 66 is due to the inversion of the control function by amplifier 36 before being applied to comparators 3 and 4. These threshold levels remain constant throughout FIG. 6, which shows the motor load responding to a command for increased speed, typifying the condition present in an open loop system (no speed or current feedback provided). In the feedback or closed loop system shown in FIG. 4, the threshold level, a function of the control function in the example of FIG. 6, would rise for SCR1 and SCR2 and fall for SCR3 and SCR4 as the command is satisfied.

FIG. 6 is divided into four different illustrations of the output of the phase controlled rectifier as the motor load passes from a motoring condition to a command satisfying quiescent condition to a regenerative condition in response to a command for increased speed which becomes satisfied and then out of this state of command satisfaction when the load becomes overhauling. The output of the phase controlled rectifier is shown by heavy line 58 and the level of motor CEMF is indicated by horizontal line 59. The times of firing of the controlled rectifiers are indicated by vertical marking lines t.sub.1, t.sub.2, t.sub.3, and t.sub.4.

The showing in FIG. 6a is the response of the system to a command for more advanced firing. Forward current conducting SCR1 and SCR2 are shown in a state of conduction in response to the fire condition when the timing functions 61 and 62 respectively exceed threshold 64. Since the alternating voltages applied to SCR1 and SCR2 are more positive than the low level CEMF, SCR1 and SCR2 are forward biased and conduct in response to trigger pulses at times t.sub.2 and t.sub.4. SCR3 and SCR4, which would normally fire at times t.sub.1 and t.sub.3 when timing functions 62 and 61 exceed threshold 66, are reversed biased and thus do not conduct.

In FIG. 6b the CEMF level 59 has risen by the response of the motor to the command so that SCR1 and SCR2, although still forward biased, conduct only shortly and now SCR3 and SCR4, no longer reverse biased, also conduct. This is an illustration of zero deadband. Both forward current and reverse current is being conducted within a single half cycle of the AC line. Thus, with fast acting lockout to prevent short circuits, as will be discussed, the control system is substantially instantly responsive to commands for motor current reversal as well as to other advance or retard firing commands.

FIG. 6c illustrates the range of quiescence. All controlled rectifiers remain conductive with the small rise in the motor's CEMF. Now SCR3 and SCR4 conduct more than SCR1 and SCR2.

In FIG. 6d the condition has changed. The level of the CEMF of the motor has risen so that SCR1 and SCR2 are back biased into nonconduction and only SCR3 and SCR4 conduct. Because the command or system input indicated by threshold levels 64 and 66 has remained constant, the condition in FIG. 6d is the system's response to load change. Here the load has become overhauling, i.e., the load drives the motor to supply power back to the alternating voltage source through SCR3 and SCR4.

With zero deadband response as FIG. 6 illustrates, there is a continuum of response from conduction in one direction through the quiescent range of reversing overlap into conduction in the other direction. Since the only period of nonconduction of the switch elements is within the half cycle of the alternating voltage, no band of nonresponse as noted in systems of the prior art is realized. FIG. 6 shows that the system responds both to command change and load change with zero deadband response.

When the load has satisfied the command it is necessary to insure that a continuum of conduction is maintained. The DC bias is provided for this purpose. It has been shown that the DC bias can either be summed with the control function and serve as the threshold for the comparator as illustrated in FIG. 6 or can be summed with the control function and the timing ramp and compared with a fixed threshold level as shown in FIG. 5. By adjusting the value of the DC bias the amount of overlapped firing of forward and reverse current conducting switch elements during a quiescent state is determined. In addition, the DC bias provides for sufficient conduction of the SCR's during the quiescent state to satisfy system losses. 6b In order to accommodate the overlap shown in FIGS. 6b and 6c where both forward and reverse current conducting controlled switch elements are conducting in each half cycle of the alternating voltage, current direction control means that are extremely fast acting must be employed. Such means are shown in FIG. 4 and constitute another element of the invention.

FIG. 4 shows a substantially instantaneous reacting direction control circuit comprising a series of AND gates 38, 39 and 40 and 41, responsive to the outputs of the comparators 1, 2, 3 and 4 under the control of direction flip-flop and oscillator 43. AND gates 38 and 39 for forward current conducting SCR1 and SCR2 are enabled by one stable state of the flip-flop to respond to the output of comparators 1 and 2 respectively, and AND gates 40 and 41 are enabled by the other stable state of the flip-flop. When AND gates 38 and 39 are enabled, the state of the flip-flop is such that AND gates 40 and 41 block any output from comparators 3 and 4. Direction flip-flop and oscillator 43 constitute a bistable device driven by an oscillator at a rate which is high compared to the frequency of the alternating voltage source. The oscillator could be of the free running type, driving the flip-flop at 20,000 hertz which is at least two orders of magnitude greater than the normal alternating voltage source frequency of 60 hertz. Thus, the direction control circuit is able to substantially instantaneously respond to either forward or reverse current conduction within a half cycle of the alternating voltage source.

The oscillator which drives the flip-flop is activated to oscillate when all controlled rectifiers are blocking voltage as indicated by conduction detector 23, 23' and when there are no fire condition indications being presented to any of the pulse generators by the AND gates. This is logically achieved by AND gate 45 which responds to outputs 22 and 22' from the conduction detector and to the inverted output of OR gate 42 which in turn responds to the outputs of AND gates 38--41. AND gate 45 controls the activation of the oscillator of direction control circuit 43. Thus, when none of the SCR's in the bridge are conducting as indicated by conduction detectors 23, 23' and there is no output from the AND gates 38--41. To render any one of the SCR's conductive, the direction flip-flop will be driven by its oscillator between its bistable states. In this condition of oscillation, the first fire condition indication applied to an AND gate will pass within the microsecond of time it takes the flip-flop to get the the proper state if it isn't already there. The passage of this pulse changes the condition to AND gate 45 via OR gate 42; the oscillator is no longer activated; and, the flip-flop stays in the state that passed the fire condition indication.

The fire condition indication, once permitted to pass the AND gate, is applied to the pulse generator for the SCR via a small input delay. This delay allows the flip-flop to settle in the state that permitted the pulse to pass and prevents the pulse generator from responding to transient indications. If a fire condition indication was generated by a comparator just as the flip-flop was changing from one state to the other, the indication would not be of sufficient duration to appear when the delay period transpired. Coincident fire condition indications which can occur only during the transition of the flip-flop between states are suppressed in like manner because it is only the indication that remains at the end of the delay period when the flip-flop has settled in a stable state that is presented to the pulse generator.

The delay circuit could comprise a simple resistor-capacitor integrator and the pulse generator would accordingly respond to a predetermined capacitor charge level. Thus, if the fire condition indication passed by an AND gate was of short duration, the charge level would not be sufficient to initiate pulse generation by the pulse generator. For this purpose, the length of the delay can be comparatively short, i.e., several microseconds.

FIG. 7 shows an alternative embodiment of current direction control. In this FIG. only new elements and those elements shown in FIG. 4 necessary to understand the embodiment of FIG. 7 are shown. The conduction detector and other control logic is the same as shown in FIG. 4 and left out for convenience. The embodiment of FIG. 7 takes advantage of the fact that the ramp function for SCR1 is the same as that for SCR4 and the ramp function for SCR2 and SCR3 is the same. Thus, only one comparator 74 is time shared by the SCR1, SCR4 circuitry and one comparator 75 is time shared by the SCR2, SCR3 circuitry. The control function, again shown coming from current error amplifier 34, is applied to the comparators by gate circuits 70--73. These gates, called analog gates, are responsive to the level change of the control function when switched on by direction flip-flop 43. Each gate may comprise an emitter follower transistor responsive to the control function and a switching transistor responsive to the direction flip-flop. Any other switch arrangement of the prior art for passing an analog signal would also suffice.

Comparator 74 receives output 35a from dual ramp generator 35 (ramp function 61 as shown in FIG. 6), the output from either gate 70 (the direct control function for control of SCR1) or from gate 71 (the inverted control function for control of SCR4), and the DC bias from source 37. Comparator 75 receives output 35b from the dual ramp generator (ramp 62), the control function from gate 72 for control of SCR2 or the inverted control function from gate 73 for control of SCR3, and the DC bias. Note that since either gate 70 or gate 71 is on a single gate which switches from a regular to an inverted output could be used.

The output of comparator 74 is applied to AND gates 38 and 41 for SCR1 and SCR4 and the output of comparator 75 is applied to AND gates 39 and 40 for SCR2 and SCR3. Since AND gate 38 is controlled by the same flip-flop output as gate 70 so that the input and output gates for each comparator are synchronously controlled by the flip-flop whenever the flip-flop is in the state to apply a positive output to these two gates, a direct connection is established between the comparator and the control function and between the comparator and the pulse generator for SCR1. At the same time alternate gates 71 and 41 (as well as gates 73 and 40) are blocked by the direction control flip-flop.

It is to be understood that specific embodiments of the invention selected as preferable for illustrating the principles thereof have been described. Many alternatives are possible. For example, while a control system for a single phase source is shown, the principles of the invention are applicable to control a multiphase phase controlled rectifier. In a multiphase system the dual ramp generator could be replaced by means to apply phase shifted portions of the AC wave directly to the comparators.

The system that has been described utilizes a full wave power circuit requiring a timing function for each pair of forward and reverse current conducting SCR's. The zero deadband control system of the present invention is as readily applicable to a half wave reversible phase controlled rectifier. For control of a half wave circuit, it is noted that a timing function is generated for each SCR.

In addition, as mentioned above, transistors could be used instead of SCR's and are to be construed as included in the term "controlled switch elements." Since a transistor is not a latching device, i.e., one that remains in conduction after the triggering excitation has been removed, such device would not be fired by a pulse but rather by a voltage level that remains for the desired conduction period. Thus, the pulse generators would be replaced by voltage level switching means such as, for example, a Schmitt trigger.

Thus, because many changes of the type that fall within the skill of the art can be made in practicing this invention without departing from the teachings set forth, it is intended that the examples shown be taken as illustrating these principles only and that the appended claims alone shall serve to define the scope of the invention.

Claims

I claim:

1. A zero deadband response reversible phase controlled rectifier control system comprising

means for developing a control function indicative of desired load operation,

timing means for developing timing functions for the controlled switch elements of said phase controlled rectifier, each timing function establishing the range of current conduction for each controlled switch element responsive thereto,

the timing functions being phase displaced from one another by said timing means with periods of overlap therebetween creating common ranges of controlled switch element conduction such that during substantial satisfaction of the control function by the load, controlled switch elements capable of conducting forward load current and controlled switch elements capable of conducting reverse load current conduct nonsimultaneously during half cycles of the alternating voltage,

comparing means for comparing said control function with said timing functions to obtain a time of firing indication for each controlled switch element,

firing means responsive to the time of firing indications from said comparing means for triggering each controlled switch element into conduction at the time dictated by the corresponding time of firing indication,

and conduction direction control means responsive to the state of conduction of the controlled switch elements to prevent conduction of forward current conducting controlled switch elements when reverse current conducting controlled switch elements are conducting and to prevent conduction of reverse current conducting controlled switch elements when forward current conducting controlled switch elements are conducting,

said conduction direction control means being in an oscillatory state between forward and reverse blocking when neither forward nor reverse current conducting controlled switch elements are conducting such that substantially instantaneous conduction direction control is provided.

2. A control system as recited in claim 1 further including signal inverting means for inverting the control function prior to its being compared with the timing functions during control of reverse current conducting controlled switch elements such that an increase control function command advances the firing of forward current conducting controlled switch elements and retards the firing of reverse current conducting controlled switch elements.

3. A control system as recited in claim 2 further including bias means applying an adjustable DC bias to said comparing means to adjust said ranges of controlled switch element firing overlap to maintain a continuum of conduction during the times the load substantially satisfies the control function command.

4. A control system as recited in claim 3 wherein said comparing means includes a comparator for each controlled switch element and said signal inverting means inverts the control function as it is applied to the comparators for reverse current conducting controlled switch elements.

5. A control system as recited in claim 4 wherein said current direction control means includes gate means in the output path of each comparator, a bistable switch, an oscillator and conduction detection means for determining the state of conduction of said controlled switch elements,

said oscillator being responsive to an indication of nonconduction of all said controlled switch elements by said conduction detection means for oscillating and driving the said bistable switch between its stable states at a rate high compared with the frequency of said alternating voltage,

said gate means being controlled by said bistable switch to permit forward current conducting controlled switch elements to be triggered into conduction when the bistable switch is one stable state and reverse current conducting controlled switch elements to be triggered into conduction when the bistable switch is in the other stable state.

6. A control system as recited in claim 5 further including logic means responsive to the output of each of said gate means and to the output of said conduction detection means,

said oscillator being responsive to said logic means to oscillate and drive said bistable switch when all controlled switch elements are nonconductive and until a fire condition indication is permitted to pass one of said gate means, said oscillator stopping oscillation upon receipt of an indication from said logic means that a fire condition indication has passed so that the bistable switch remains in the stable state which permitted the gate means to pass the fire condition indication.

7. A control system as recited in claim 6 wherein said conduction detection means comprises a voltage threshold detector responsive to the voltage level across the controlled switch elements of the phase controlled rectifier.

8. A control system as recited in claim 3 wherein said phase controlled rectifier is a full wave rectifier, there being a pair of controlled switch elements consisting of a forward current conducting controlled switch element and a reverse current conducting controlled switch element responsive to each timing function,

and said comparing means includes a comparator for each pair of controlled switch elements and input gate means for each comparator permitting comparison of the control function with the timing function for alternate control of the forward current conducting controlled switch element and the reverse current conducting controlled switch element,

said signal inverting means being coupled to the comparators by the gate means during control of reverse current conducting controlled switch elements to invert said control function.

9. A control system as recited in claim 8 wherein said current direction control means includes gate means in the output path of said comparators, a bistable switch, an oscillator, and conduction detection means for determining the state of conduction of said controlled switch elements,

said oscillator being responsive to an indication of nonconduction of all of said controlled switch elements by said conduction detection means for oscillating and driving said bistable switch between its stable states at a rate high compared to the frequency of said alternating voltage,

the input gate means for each comparator being controlled by said bistable switch to permit comparison of the control function with the timing function when in one stable state to control the firing of the forward current conducting controlled switch element of each pair of controlled switch elements and the comparison of the inverted control function with the timing function when in the other stable state to control the firing of the reverse current conducting controlled switch element,

the output gate means for each comparator being controlled by said bistable switch to permit the forward current conducting controlled switch element to be triggered into conduction when the bistable switch is in said one stable state and the reverse current conducting controlled switch element to be triggered into conduction when the bistable switch is in said other stable state.

10. In a phase controlled rectifier reversible power supply in which firing signals are applied to the controlled switch elements of the phase controlled rectifier at varying phase angles to determine the amount and direction of power flow to and from the load, a lockout protection circuit for substantially instantly directing firing signals between forward and reverse current conducting switch elements comprising:

gate means capable of permitting said firing signals to be applied to the controlled switch elements,

conduction detection means responsive to the state of conduction of said controlled switch elements,

and bistable switch means responsive to said conduction detection means to cause the gate means to block firing signals for forward current conducting controlled switch elements when reverse current conducting controlled switch elements are conducting and to cause the gate means to block firing signals for reverse current conducting controlled switch elements when forward current conducting controlled switch elements are conducting,

said direction control means including an oscillator to continuously drive the bistable switch between its stable states when said conduction detection means indicate that all controlled switch elements are not conducting.

11. A lockout protection circuit as recited in claim 10 wherein said oscillator is responsive to the first firing signal passed by said gate means to stop the bistable switch in the state which permitted the firing signal to pass, said direction control means thereby causing the gate means to block firing signals for the opposite direction current conducting controlled switch elements.