U.S. patent number 11,069,393 [Application Number 16/431,641] was granted by the patent office on 2021-07-20 for apparatuses and methods for controlling steal rates.
This patent grant is currently assigned to Micron Technology, Inc.. The grantee listed for this patent is Micron Technology, Inc.. Invention is credited to Beau D. Barry, Timothy B. Cowles, Adam J. Grenzebach, Matthew D. Jenkinson, Jiyun Li, Nathaniel J. Meier, Dennis G. Montierth, Michael A. Shore.
United States Patent |
11,069,393 |
Cowles , et al. |
July 20, 2021 |
Apparatuses and methods for controlling steal rates
Abstract
An apparatus may include a refresh control circuit with multiple
timing circuits. The timing circuits may be used to control steal
rates, e.g., the rate of refresh time slots dedicated to healing
victim word lines of row hammers. The timing circuits may be
controlled to allow independent adjustment of the steal rates for
different victim word lines. Thus, different victim word lines may
be refreshed at different rates and the different rates may be
independent of one another.
Inventors: |
Cowles; Timothy B. (Boise,
ID), Li; Jiyun (Boise, ID), Barry; Beau D. (Boise,
ID), Jenkinson; Matthew D. (Boise, ID), Meier; Nathaniel
J. (Boise, ID), Shore; Michael A. (Boise, ID),
Grenzebach; Adam J. (Boise, ID), Montierth; Dennis G.
(Meridian, ID) |
Applicant: |
Name |
City |
State |
Country |
Type |
Micron Technology, Inc. |
Boise |
ID |
US |
|
|
Assignee: |
Micron Technology, Inc. (Boise,
ID)
|
Family
ID: |
73651547 |
Appl.
No.: |
16/431,641 |
Filed: |
June 4, 2019 |
Prior Publication Data
|
|
|
|
Document
Identifier |
Publication Date |
|
US 20200388325 A1 |
Dec 10, 2020 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
G11C
11/40611 (20130101); G11C 11/4087 (20130101); G11C
11/4085 (20130101); G11C 11/40618 (20130101) |
Current International
Class: |
G11C
7/00 (20060101); G11C 11/406 (20060101); G11C
11/408 (20060101) |
References Cited
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|
Primary Examiner: Le; Toan K
Attorney, Agent or Firm: Dorsey & Whitney LLP
Claims
What is claimed is:
1. An apparatus comprising: a refresh control circuit including: a
first victim steal rate timing circuit configured to provide a
first signal at a first frequency, wherein the first frequency
indicates a rate a first victim word line is refreshed; and a
second victim steal rate timing circuit configured to provide a
second signal at a second frequency, wherein the second frequency
indicates a rate a second victim word line is refreshed, wherein
the first frequency and the second frequency are independent of
each other.
2. The apparatus of claim 1, wherein the first frequency is greater
than the second frequency.
3. The apparatus of claim 2, wherein the first victim word line is
physically closer to an aggressor word line than the second victim
word line.
4. The apparatus of claim 1, wherein at least one of the first
frequency or the second frequency is set by a fuse.
5. The apparatus of claim 1, wherein at least one of the first
frequency or the second frequency is set by programming a mode
register.
6. The apparatus of claim 1, further comprising a targeted refresh
address controller circuit configured to receive the first signal
and the second signal, wherein the targeted refresh address
controller circuit is configured to provide a control signal based,
at least in part on the first signal and the second signal, wherein
the control signal determines a row address provided as a refresh
address.
7. The apparatus of claim 6, further comprising a multiplexer
configured to receive a first victim row address corresponding to
the first victim word line and a second victim row address
corresponding to the second victim word line, wherein based on the
control signal, the multiplexer is configured to provide the first
victim row address or the second victim row address as the refresh
address.
8. The apparatus of claim 7, wherein the control signal causes the
multiplexer to provide the first victim row address when the first
signal is active and the control signal causes the multiplexer to
provide the second victim row address as the refresh address when
the second signal is active.
9. The apparatus of claim 7, wherein the control signal causes the
multiplexer to provide the first victim row address as the refresh
address when both the first signal and the second signal are
active.
10. The apparatus of claim 7, wherein the targeted refresh address
controller circuit further receives a refresh signal and the
multiplexer further receives an auto-refresh address, wherein the
control signal causes the multiplexer to provide the auto-refresh
address as the refresh address when the refresh signal is active
and the first signal and the second signal are inactive.
11. The apparatus of claim 10, wherein the control signal causes
the multiplexer to not provide the refresh address when the refresh
signal is inactive.
12. The apparatus of claim 10, wherein the refresh signal is
provided by a command control circuit.
13. The apparatus of claim 1, wherein at least one of the first
victim steal rate timing circuit or the second victim steal rate
timing circuit receives a refresh signal, wherein the refresh
signal is configured to synchronize activation of at least one of
the first signal and the second signal.
14. An apparatus comprising: a memory array; a row control circuit
coupled to the memory array; a first timing circuit configured to
provide a first signal at a first frequency; a second timing
circuit configured to provide a second signal at a second
frequency, wherein the second frequency is independent of the first
frequency; and a targeted refresh address controller circuit
configured to provide a first type of victim row address at the
first frequency and a second type of victim row address at the
second frequency, wherein the first type and the second type of
victim row addresses are provided to the row control circuit for
performing refresh operations on victim word lines of the memory
array corresponding to the first type and the second type of victim
row addresses.
15. The apparatus of claim 14, further comprising: an aggressor row
detector circuit configured to detect an aggressor word line and
provide an aggressor row address corresponding to the aggressor
word line; a first victim address generator configured to provide
the first type of victim row address based, at least in part, on
the aggressor row address; and a second victim address generator
configured to provide the second type of victim row address based,
at least in part, on the aggressor row address.
16. The apparatus of claim 15, wherein a victim word line
corresponding to the first type of victim row address has a first
physical relationship to the aggressor word line and a victim word
line corresponding to the second type of victim row address has a
second physical relationship to the aggressor word line different
from the first physical relationship.
17. A method comprising: providing a first signal having a first
frequency; providing a second signal having a second frequency,
wherein the second frequency is independent of the first frequency;
refreshing a first victim word line based, at least in part, on the
first frequency; and refreshing a second victim word line based, at
least in part, on the second frequency.
18. The method of claim 17, further comprising: generating a
control signal based, at least in part, on the first signal and the
second signal; and providing a refresh address for refreshing a
word line based, at least in part, on the control signal, wherein
the refresh address is the first victim word line or the second
victim word line.
19. The method of claim 17, further comprising setting at least one
of the first frequency or the second frequency by setting a
fuse.
20. The method of claim 17, further comprising setting at least one
of the first frequency or the second frequency by programming a
mode register.
Description
BACKGROUND
This disclosure relates generally to semiconductor devices, and
more specifically to semiconductor memory devices. In particular,
the disclosure relates to volatile memory, such as dynamic random
access memory (DRAM). Information may be stored on individual
memory cells of the memory as a physical signal (e.g., a charge on
a capacitive element). The memory may be a volatile memory, and the
physical signal may decay over time (which may degrade or destroy
the information stored in the memory cells). It may be necessary to
periodically refresh the information in the memory cells by, for
example, rewriting the information to restore the physical signal
to an initial value.
As memory components have decreased in size, the density of memory
cells has greatly increased. Typically, memory cells are arranged
in an array that includes a series of rows referred to as word
lines and columns referred to as bit lines. An auto-refresh
operation may be carried out where the memory cells of one or more
word lines are periodically refreshed to preserve data stored in
the memory cells. Repeated access to a particular memory cell or
group of memory cells, such as a word line, may cause an increased
rate of data degradation in nearby memory cells (e.g., adjacent
word lines). This repeated access is often referred to as a `row
hammer.` To preserve the data in nearby memory cells, the word
lines of the nearby memory cells may need to be refreshed at a rate
higher than a rate of the auto-refresh operations. However, extra
refresh operations increase power consumption and may interfere
with other memory operations. Accordingly, reducing extra refresh
operations is desired.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of a semiconductor device according to an
embodiment of the present disclosure.
FIG. 2 is a block diagram of a refresh control circuit according to
an embodiment of the present disclosure.
FIG. 3 is a circuit diagram of an example targeted refresh address
controller circuit according to an embodiment of the present
disclosure.
FIG. 4 is an example timing diagram of a refresh signal, a first
timing signal, and a second timing signal in accordance with an
embodiment of the present disclosure.
FIG. 5 is an example aggressor row detector circuit according to an
embodiment of the present disclosure.
FIG. 6 is a flow chart of a method according to an embodiment of
the present disclosure.
DETAILED DESCRIPTION
The following description of certain embodiments is merely
exemplary in nature and is in no way intended to limit the scope of
the disclosure or its applications or uses. In the following
detailed description of embodiments of the present systems and
methods, reference is made to the accompanying drawings which form
a part hereof, and which are shown by way of illustration specific
embodiments in which the described systems and methods may be
practiced. These embodiments are described in sufficient detail to
enable those skilled in the art to practice presently disclosed
systems and methods, and it is to be understood that other
embodiments may be utilized and that structural and logical changes
may be made without departing from the spirit and scope of the
disclosure. Moreover, for the purpose of clarity, detailed
descriptions of certain features will not be discussed when they
would be apparent to those with skill in the art so as not to
obscure the description of embodiments of the disclosure. The
following detailed description is therefore not to be taken in a
limiting sense, and the scope of the disclosure is defined only by
the appended claims.
A memory device may include a plurality of memory cells. The memory
cells may store information (e.g., as one or more bits), and may be
organized at the intersection of word lines (rows) and bit lines
(columns). A number of word lines and bit lines may be organized
into a memory bank. The memory device may include a number of
different memory banks. The memory device may receive one or more
command signals which may indicate operations in one or more of the
banks of one or more memory packages. For example, the memory
device may enter a refresh mode, in which word lines in one or more
of the memory banks are refreshed.
Information in the memory cells may decay over time. The memory
cells may be refreshed on a row-by-row (e.g., word line-by-word
line) basis to preserve information in the memory cells. During a
refresh operation, the information in one or more rows may be
rewritten back to the respective word line to restore an initial
value of the information. Repeated access to a given word line
(e.g., an aggressor word line) may cause an increased rate of
information decay in one or more neighboring word lines (e.g.,
victim word lines). In some applications, victim word lines may be
considered to be the word lines which are physically adjacent to
the aggressor word line. For example, victim word lines may be
physically adjacent to the aggressor word line, that is, the victim
word lines may be physically on either side of the aggressor word
line (e.g., R+1 and R-1). In some embodiments, the word lines which
are physically adjacent to the adjacent word lines (e.g., R+2 and
R-2) may also be treated as victim word lines. In some
applications, such as memories where word lines are densely spaced,
more distant word lines may also be considered as victim word lines
(e.g., R+3, R-3, R+4, R-4, etc.). Other relationships between
victim and aggressor word lines may be used in other example
embodiments.
Accesses to different word lines of the memory may be tracked in
order to determine if a word line is an aggressor word line. For
example, the row address of the accessed word lines and/or
aggressor word lines may be stored in a register (e.g., file) or
other storage device in the memory. If a word line is determined to
be an aggressor word line, victim addresses associated with the
victim word lines may be determined based, at least in part, on a
row address of the aggressor word line. In some embodiments, the
victim word lines (e.g., R+1, R-1, R+2, and R-2) may be refreshed
as part of a targeted (or `row hammer`) refresh operation and thus
there may be, for example, four victim addresses refreshed for each
determined aggressor row address. A row address for a victim word
line refreshed during a targeted refresh operation may be referred
to as a targeted refresh address.
In some embodiments, some time slots for refresh operations may be
reserved for auto-refresh operations and some time slots may be
reserved for targeted refresh operations. In some embodiments, a
targeted refresh address may be issued in a time slot which would
otherwise have been assigned to an auto-refresh address (e.g.,
"steal") if no row hammer management was needed. In some
embodiments, certain refresh time slots may be reserved for
targeted refresh addresses. These time slots may be referred to as
targeted refresh time slots. The time period between time slots
reserved for targeted refresh addresses may be referred to as the
targeted refresh rate or steal rate.
Different victim word lines of an aggressor word line may not be
affected in the same manner by a row hammer. For example, victim
word lines closer to the aggressor word line (e.g., adjacent victim
word lines, R+/-1) may suffer a higher rate of data degradation
than more distant victim word lines (e.g., R+/-2). Accordingly, it
may be desirable to perform targeted refresh operations on
different victim word lines at different rates. For example, the
R+/-1 victim word lines may be refreshed at four times the rate of
the refreshing of R+/-2 victim word lines. In another example, the
R+/-1 victim word lines may be refreshed at eight times the rate of
the refreshing of R+/-2 victim word lines. In some applications, it
may be desirable to be able to adjust the targeted refresh rate of
the different victim word lines independently from one another.
That is, the targeted refresh rate of R+/-2 may not depend on the
targeted refresh rate of R+/-1. This may allow the targeted refresh
rates for each type of victim word line to be optimized, which may
reduce over-refreshing of the word lines.
The present disclosure is drawn to apparatuses and methods for
controlling targeted refresh rates (e.g., steal rates). More
specifically, the present disclosure is drawn to apparatuses and
methods for independently controlling the steal rates for different
victim word lines, such as victim word lines that have different
physical distances from an aggressor word line. In some
embodiments, a refresh control circuit may include two or more
timing circuits to allow independent control of the steal rates for
different victim word lines.
FIG. 1 is a block diagram showing an overall configuration of a
semiconductor device according to at least one embodiment of the
disclosure. The semiconductor device 100 may be a semiconductor
memory device, such as a DRAM device integrated on a single
semiconductor chip.
The semiconductor device 100 includes a memory array 112. In some
embodiments, the memory array 112 may include of a plurality of
memory banks. Each memory bank includes a plurality of word lines
WL, a plurality of bit lines BL and /BL, and a plurality of memory
cells MC arranged at intersections of the plurality of word lines
WL and the plurality of bit lines BL and /BL. The selection of the
word line WL is performed by a row control circuit 108 and the
selection of the bit lines BL and /BL is performed by a column
control circuit 110. In some embodiments, there may be a row
control circuit 108 and column control circuit 110 for each of the
memory banks.
The bit lines BL and /BL are coupled to a respective sense
amplifier (SAMP) 117. Read data from the bit line BL or /BL is
amplified by the sense amplifier SAMP 117, and transferred to
read/write amplifiers 120 over complementary local data lines
(LIOT/B), transfer gate (TG) 118, and complementary main data lines
(MIO). Conversely, write data outputted from the read/write
amplifiers 120 is transferred to the sense amplifier 117 over the
complementary main data lines MIO, the transfer gate 118, and the
complementary local data lines LIOT/B, and written in the memory
cell MC coupled to the bit line BL or /BL.
The semiconductor device 100 may employ a plurality of external
terminals that include command and address (C/A) terminals coupled
to a command and address bus to receive commands and addresses,
clock terminals to receive clocks CK and /CK, data terminals DQ to
provide data, and power supply terminals to receive power supply
potentials VDD, VSS, VDDQ, and VSSQ.
The clock terminals are supplied with external clocks CK and /CK
that are provided to a clock input circuit 122. The external clocks
may be complementary. The clock input circuit 122 generates an
internal clock ICLK based on the CK and /CK clocks. The ICLK clock
is provided to the command control circuit 106 and to an internal
clock generator circuit 124. The internal clock generator circuit
124 provides various internal clocks LCLK based on the ICLK clock.
The LCLK clocks may be used for timing operation of various
internal circuits. The internal data clocks LCLK are provided to
the input/output circuit 126 to time operation of circuits included
in the input/output circuit 126, for example, to data receivers to
time the receipt of write data.
The C/A terminals may be supplied with memory addresses. The memory
addresses supplied to the C/A terminals are transferred, via a
command/address input circuit 102, to an address decoder circuit
104. The address decoder circuit 104 receives the address and
supplies a decoded row address XADD to the row control circuit 108
and supplies a decoded column address YADD to the column control
circuit 110. The row address XADD may be used to specify one or
more word lines WL of the memory array 112 and the column address
YADD may specify one or more bit lines BL of the memory array 112.
The address decoder circuit 104 may also provide a bank address
BADD, which specifies a particular bank of the memory. The bank
address BADD may be provided to the row control circuit 108 and/or
column control circuit 110 to direct access operations to one or
more of the banks. The C/A terminals may be supplied with commands.
Examples of commands include timing commands for controlling the
timing of various operations, access commands for accessing the
memory, such as read commands for performing read operations and
write commands for performing write operations, as well as other
commands and operations. The access commands may be associated with
one or more row address XADD, column address YADD, and/or bank
address BADD to indicate the memory cell(s) to be accessed.
The commands may be provided as internal command signals to a
command control circuit 106 via the command/address input circuit
102. The command control circuit 106 includes circuits to decode
the internal command signals to generate various internal signals
and commands for performing operations. For example, the command
control circuit 106 may provide a row command signal to select a
word line and a column command signal to select a bit line.
The device 100 may receive an access command which is a row
activation command ACT. When the row activation command ACT is
received, a row address XADD is timely supplied with the row
activation command ACT.
The device 100 may receive an access command which is a read
command. When a read command is received, a bank address BADD and a
column YADD address are timely supplied with the read command, read
data is read from memory cells in the memory array 112
corresponding to the row address XADD and column address YADD. The
read command is received by the command control circuit 106, which
provides internal commands so that read data from the memory array
112 is provided to the read/write amplifiers 120. The read data is
output to outside from the data terminals DQ via the input/output
circuit 126.
The device 100 may receive an access command which is a write
command. When the write command is received, a bank address and a
column address are timely supplied with the write command, write
data supplied to the data terminals DQ is written to a memory cells
in the memory array 112 corresponding to the row address and column
address. The write command is received by the command control
circuit 106, which provides internal commands so that the write
data is received by data receivers in the input/output circuit 126.
Write clocks may also be provided to the external clock terminals
for timing the receipt of the write data by the data receivers of
the input/output circuit 126. The write data is supplied via the
input/output circuit 126 to the read/write amplifiers 120, and by
the read/write amplifiers 120 to the memory array 112 to be written
into the memory cell MC.
The device 100 may also receive commands causing it to carry out
refresh operations. A refresh signal AREF may be a pulse signal
which is activated when the command control circuit 106 receives a
signal which indicates a refresh command. In some embodiments, the
refresh command may be externally issued to the memory device 100.
In some embodiments, the refresh command may be periodically
generated by a component of the device. In some embodiments, when
an external signal indicates a self-refresh entry command, the
refresh signal AREF may also be activated. The refresh signal AREF
may be activated once immediately after command input, and
thereafter may be cyclically activated at a desired internal
timing. Thus, refresh operations may continue automatically. A
self-refresh exit command may cause the automatic activation of the
refresh signal AREF to stop and return to an IDLE state.
The refresh control circuit 116 supplies a refresh row address
RXADD to the row control circuit 108, which may refresh one or more
word lines WL indicated by the refresh row address RXADD. The
refresh control circuit 116 may control a timing of the refresh
operation based on the refresh signal AREF. In some embodiments,
responsive to an activation of AREF, the refresh control circuit
116 may generate one or more activations of a pump signal, and may
generate and provide a refresh address RXADD for each activation of
the pump signal (e.g., each pump).
One type of refresh operation may be an auto-refresh operation.
Responsive to an auto-refresh operation the memory bank may refresh
a word line or a group of word lines of the memory, and then may
refresh a next word line or group of word lines of the memory bank
responsive to a next auto-refresh operation. The refresh control
circuit 116 may provide an auto-refresh address as the refresh
address RXADD which indicates a word line or a group of word lines
in the memory bank. The refresh control circuit 116 may generate a
sequence of refresh addresses RXADD such that over time the
auto-refresh operation may cycle through all the word lines WL of
the memory bank. The timing of refresh operations may be such that
each word line is refreshed with a frequency based, at least in
part, on a normal rate of data degradation in the memory cells
(e.g., auto-refresh rate).
Another type of refresh operation may be a targeted refresh
operation. As mentioned previously, repeated access to a particular
word line of memory (e.g., an aggressor word line) may cause an
increased rate of decay in neighboring word lines (e.g., victim
word lines) due, for example, to electromagnetic coupling between
the word lines. In some embodiments, the victim word lines may
include word lines which are physically adjacent to the aggressor
word line. In some embodiments, the victim word lines may include
word lines further away from the aggressor word line. Information
in the victim word line may decay at a rate such that data may be
lost if they are not refreshed before the next auto-refresh
operation of that word line. In order to prevent information from
being lost, it may be necessary to identify aggressor word lines
and then carry out a targeted refresh operation where a refresh
address RXADD associated with one or more associated victim word
lines is refreshed.
The refresh control circuit 116 may selectively output a targeted
refresh address (e.g., a victim row address) or an automatic
refresh address (e.g., auto-refresh address) as the refresh address
RXADD. The auto-refresh addresses may be from a sequence of
addresses which are provided based on activations of the
auto-refresh signal AREF. The refresh control circuit 116 may cycle
through the sequence of auto-refresh addresses at a rate determined
by AREF. In some embodiments, the sequence of auto-refresh
addresses may be generated by updating (e.g., incrementing) one or
more portions of the previous auto-refresh address.
The refresh control circuit 116 may also determine targeted refresh
addresses which are addresses that require refreshing (e.g., victim
row addresses corresponding to victim word lines) based on the
access pattern of nearby addresses (e.g., aggressor row addresses
corresponding to aggressor word lines) in the memory array 112. The
refresh control circuit 116 may selectively use one or more signals
of the device 100 to calculate the refresh address RXADD. For
example, the refresh address RXADD may be calculated based on the
row addresses XADD provided by the address decoder circuit 104. The
refresh control circuit 116 may receive the current value of the
row address XADD provided by the address decoder circuit 104 and
determine a targeted refresh address based on one or more of the
received addresses XADD.
The refresh address RXADD may be provided with a timing based on a
timing of the refresh signal AREF. The refresh control circuit 116
may have time slots corresponding to the timing of AREF, and may
provide one or more refresh addresses RXADD during each time slot.
A targeted refresh address may be issued in a time slot which would
otherwise have been assigned to an auto-refresh address (e.g.,
"steal"). In some embodiments, certain time slots may be reserved
for targeted refresh addresses. These time slots may be referred to
as a targeted refresh intervals or targeted refresh time slots. The
time period between time slots reserved for targeted refresh
addresses may be referred to as the targeted refresh rate or steal
rate.
In some embodiments, certain targeted refresh time slots may be
reserved for refreshing a type of victim word line while other
targeted refresh time slots may be reserved for refreshing another
type of victim word lines. For example, certain targeted refresh
time slots may be reserved for refreshing R+/-1 victim word lines
and other targeted refresh time slots may be reserved for
refreshing R+/-2 victim word lines. In some embodiments, the steal
rates for the targeted refresh time slots for the different types
of victim word lines may be different. In some embodiments, the
steal rates for the targeted refresh time slots for the different
types of victim word lines may be independent of one another.
The refresh control circuit 116 may receive the row addresses XADD
provided by the address decoder circuit 104 and may determine which
word lines are being hammered based on the row addresses XADD. For
example, the refresh control circuit 116 may count accesses to the
word lines and may determine which word lines are aggressors based
on the count of the accesses (e.g., reach a threshold value). The
row addresses XADD and access count values may be stored by the
refresh control circuit 116. When an aggressor word line is
determined, the refresh control circuit 116 may calculate victim
word lines associated with the aggressor word line and perform
targeted refresh operations as previously described.
The power supply terminals are supplied with power supply
potentials VDD and VSS. The power supply potentials VDD and VSS are
supplied to an internal voltage generator circuit 128. The internal
voltage generator circuit 128 generates various internal potentials
VPP, VOD, VARY, VPERI, and the like based on the power supply
potentials VDD and VSS supplied to the power supply terminals. The
internal potential VPP is mainly used in the row decoder circuit
108, the internal potentials VOD and VARY are mainly used in the
sense amplifiers SAMP included in the memory array 112, and the
internal potential VPERI is used in many peripheral circuit
blocks.
The power supply terminals are also supplied with power supply
potentials VDDQ and VSSQ. The power supply potentials VDDQ and VSSQ
are supplied to the input/output circuit 126. The power supply
potentials VDDQ and VSSQ supplied to the power supply terminals may
be the same potentials as the power supply potentials VDD and VSS
supplied to the power supply terminals in an embodiment of the
disclosure. The power supply potentials VDDQ and VSSQ supplied to
the power supply terminals may be different potentials from the
power supply potentials VDD and VSS supplied to the power supply
terminals in another embodiment of the disclosure. The power supply
potentials VDDQ and VSSQ supplied to the power supply terminals are
used for the input/output circuit 122 so that power supply noise
generated by the input/output circuit 126 does not propagate to the
other circuit blocks.
FIG. 2 is a block diagram of a refresh control circuit 216
according to an embodiment of the present disclosure. In some
embodiments, the refresh control circuit 216 may be included in a
memory device, such as memory device 100 shown in FIG. 1. For
context, a DRAM interface 226 and a row decoder circuit 208 are
also shown in FIG. 2. In some embodiments, refresh control circuit
216 may be included in refresh control circuit 116 shown in FIG. 1.
In some embodiments, row decoder circuit 208 may be included in row
control circuit 108. In some embodiments, some of the components
(e.g., the refresh control circuit 216 and row decoder circuit 208)
may be provided for a particular bank of memory and these
components may be repeated for each of the banks of memory. Thus,
there may be multiple refresh control circuits 216 and row decoder
circuits 208 in a memory device. For the sake of brevity, only
components for a single bank will be described.
A DRAM interface 226 may provide one or more signals to an address
refresh control circuit 216 and row decoder circuit 208. The
refresh control circuit 216 may include an aggressor row detector
circuit 230, a first victim address generator 232, a second victim
address generator 234, an auto-refresh (AREF) address generator
236, a first victim steal rate timing circuit 238, a second victim
steal rate timing circuit 240, a multiplexer 242, and a targeted
refresh address controller circuit 244. The DRAM interface 226 may
provide one or more control signals, such as an auto-refresh signal
AREF, an activation/precharge signal ACT/Pre, and a row address
XADD.
The DRAM interface 226 may represent one or more components which
provides signals to components of a memory bank, such as refresh
control circuit 216 and row decoder circuit 208. In some
embodiments, the DRAM interface 226 may represent a memory
controller coupled to the semiconductor memory device (e.g., device
100 of FIG. 1). In some embodiments, the DRAM interface 226 may
represent components such as the command address input circuit 102,
the address decoder circuit 104, and/or the command control circuit
106 of FIG. 1. The DRAM interface 226 may provide a row address
XADD, the auto-refresh signal AREF, an activation signal ACT,
and/or a precharge signal Pre. The auto-refresh signal AREF may be
a periodic signal which may indicate when an auto-refresh operation
is to occur. The activation signal ACT may be provided to activate
a given bank of the memory. The row address XADD may be a signal
including multiple bits (which may be transmitted in series or in
parallel) and may correspond to a specific row of a memory bank
(e.g., the memory bank activated by ACT/Pre).
During a memory operation, the aggressor row detector circuit 230
may receive the current row address XADD. In some embodiments, the
aggressor row detector circuit 230 may store the current value of
the row address XADD. The aggressor row detector circuit 230 may
further store a count value associated with each stored row
address. The count value for a row address may be adjusted (e.g.,
incremented) each time the row address stored in the aggressor row
detector circuit 230 is received as XADD.
For each row address XADD stored in the aggressor row detector
circuit 230, the aggressor row detector circuit 230 may determine
if the current row address XADD is an aggressor row address based
on one or more previously stored row addresses. For example, in
some embodiments, the aggressor row detector circuit 230 may
determine a row address is an aggressor row address based on a
number of times the row address XADD is received (e.g., the count
value of the stored row address exceeds a threshold value). The
aggressor row detector circuit 230 may then reset the count value
associated with the aggressor row address. Other aggressor row
detection methods may be used in other embodiments. When an
aggressor row address is identified, the aggressor row detector
circuit 230 may provide the matched address HitXADD to the first
victim address generator 232 and the second victim address
generator 234 in some embodiments.
The row address XADD may change as the DRAM interface 226 directs
access operations (e.g., read and write operations) to different
rows of the memory cell array (e.g., memory cell array 118 of FIG.
1). In some embodiments, the aggressor row detector circuit 230 may
store every received row address XADD. In other embodiments, the
aggressor row detector circuit 230 may store received row addresses
responsive to an active sample signal provided by a sample timing
generator (not shown). In some embodiments, the sample signal may
be a pulse signal. That is, it may transition to an active state
and return to an inactive state after a time period (e.g., half a
clock cycle, one clock cycle). The sample generator may regularly,
randomly, or pseudo-randomly vary a time interval between pulses of
the sample signal.
The first victim address generator 232 and the second victim
address generator 234 calculate one or more row addresses to be
refreshed based on aggressor row addresses identified by the
aggressor row detector circuit 230 (e.g. row addresses XADD
associated with count values above a threshold value). The row
addresses calculated by the first victim address generator 232 and
the second victim address generator 234 may be victim row addresses
corresponding to victim word lines of an aggressor word line
associated with HitXADD. The first victim address generator 232 and
the second victim address generator 234 may be provided the match
address HitXADD as input. The first victim address generator 232
may provide a targeted refresh address V1ADD and the second victim
address generator 234 may provide targeted refresh address V2ADD in
response to these inputs. The targeted refresh addresses may be an
addresses for a memory location (e.g., a word line) that may be
affected by repeated activation of the memory location
corresponding to the match address HitXADD. In other words, the
match address HitXADD may be an `aggressor` row address, and the
targeted refresh address V1ADD and V2ADD may be a `victim`
addresses. Different calculations may be used for generating
different victim addresses as the targeted refresh addresses V1ADD
and V2ADD.
The first victim address generator 232 and the second victim
address generator 234 may employ different calculations for
generating victim row addresses. In one example, a first
calculation may be used by the first victim address generator 232,
and a second calculation may be used by the second victim address
generator 234. The calculations may provide targeted refresh
addresses V1ADD or V2ADD corresponding to word lines which have a
known physical relationship (e.g., a spatial relationship) with a
word line corresponding to the match address HitXADD. In some
embodiments, the different calculations may be based on different
physical relationships between the victim word line and the
aggressor word line. The calculations may result in a single
targeted refresh address for V1ADD and/or V2ADD in some embodiments
of the disclosure. The calculations may result in a sequence of
targeted refresh addresses for V1ADD and/or V2ADD in other
embodiments of the disclosure.
In one embodiment, the first calculation may cause the first victim
address generator 232 to output a pair of addresses which
correspond to word lines that are adjacent to the word line
corresponding to the match address HitXADD (e.g.,
V1ADD=HitXADD+/-1). The second calculation may cause the second
victim address generator 234 to output a pair of addresses which
correspond to word lines that are adjacent to word lines
corresponding to the addresses HitXADD+/-1 (e.g.,
V2ADD=HitXADD+/-2). In other words, the second calculation may
output a pair of addresses that correspond to victim word lines
adjacent to the victim word lines corresponding to the addresses
VADD. Other calculations are possible in other example embodiments.
For example, the first calculation may be based on a physical
relationship with the match address HitXADD, while the second
calculation may be based on a physical relationship with the
address(es) provided by the first calculation. The targeted
addresses V1ADD and V2ADD calculated by the first victim address
generator 232 and the second victim address generator 234 may be
provided to a multiplexer 242 in some embodiments. In some
embodiments, the first victim address generator 232 and the second
victim address generator 234 may include buffers (not shown) for
storing victim row addresses to be provided to the multiplexer 242
during subsequent targeted refresh operations.
The AREF address generator 236 generates an auto-refresh address
Pre_RXADD in response to the refresh signal AREF. The auto-refresh
address Pre_RXADD may be part of a sequence of addresses to be
refreshed as part of an auto-refresh operation. The AREF address
generator 236 may update the current auto-refresh address Pre_RXADD
to a next address in the sequence in response to an active refresh
signal AREF. The AREF address generator 236 is also provided the
command signal RHR from targeted refresh address controller circuit
244. In some embodiments, when the command signal RHR is active,
the AREF address generator 236 may be controlled to stop updating
the automatic refresh address Pre_RXADD even if the automatic
refresh signal AREF is active. As described herein, since the
active command signal RHR indicates that a targeted refresh
operation is to be conducted instead of an automatic refresh
operation, this allows the automatic refresh operation to be
suspended while the targeted refresh is carried out, and resumed
when the command signal RHR is not active.
The multiplexer 242 accepts the automatic refresh address Pre_RXADD
provided by the AREF address generator 236, V1ADD provided by first
victim address generator 232, V2ADD provided by second victim
address generator 234, and outputs one of them as the refresh
address RXADD. The multiplexer 242 may select between the refresh
addresses based on the command signal RHR. Targeted refresh address
controller circuit 244 provides an output RHR to the multiplexer
242 to control selection of providing the Pre_RXADD, V1ADD, or
V2ADD addresses as the refresh address RXADD.
First victim steal rate timing circuit 238 may provide a timing
signal V1Time that may determine a rate at which victim row address
V1ADD is provided as RXADD. Second victim steal rate timing circuit
240 may provide a timing signal V2Time that may determine a rate at
which victim row address V2ADD is provided as RXADD. Timing signals
V1Time and V2Time may be periodic signals that alternate between
active and inactive states (e.g., between high and low logic
levels). The timing signals V1Time and V2Time may operate at
different frequencies in some embodiments. For example, in some
embodiments, V1Time may have a higher frequency than V2Time. In
these embodiments, this may cause victim row address V1ADD to be
provided as RXADD at a higher frequency than V2ADD. The first
victim steal rate timing circuit 238 and the second victim steal
rate timing circuit 240 may be independent. That is, neither timing
circuit requires an input from the other timing circuit to generate
its output. In some embodiments, the timing circuits may each
receive at least one input unique to the timing circuit such that
the timing circuits do not receive completely identical inputs.
The first victim steal rate timing circuit 238 and/or the second
victim steal rate timing circuit 240 may include a square wave
generating circuit for generating the outputs V1Time and V2Time,
respectively. For example, a Schmitt waveform generator, a 555
timer (not shown), and/or a ring-type waveform generator may be
included in the first victim steal rate timing circuit 238 and/or
the second victim steal rate timing circuit 240. As indicted by
Set(1) and Set(2) in FIG. 2, the frequencies of V1Time and/or
V2Time may be set by fuses, antifuses, programming one or more mode
registers, and/or other frequency setting method. For example, the
frequencies may be set by providing a timing control voltage
via/responsive to a command signal from the DRAM interface 226 in
some embodiments.
Optionally, in some embodiments, the first victim steal rate timing
circuit 238 and/or the second victim steal rate timing circuit 240
may receive the AREF signal to synchronize the activation of the
V1Time and/or V2Time with the AREF signal. This may help ensure
that the V1Time and/or V2Time signals are activated during refresh
operations rather than between refresh operations when the timing
signals may be ignored.
The targeted refresh address controller circuit 244 may receive
V1Time, V2Time, and AREF as inputs and provide control signal RHR
based on these inputs. Targeted refresh address controller circuit
244 may include logic gates and/or other circuitry to generate
control signal RHR. Control signal RHR may have multiple states in
some embodiments. In some embodiments, control signal RHR may be a
multi-bit signal with multiple states (e.g., `00`, `01,` `10,`
`11`). For example, RHR may have a first state when AREF is
inactive, regardless of the states of V1Time and V2Time, a second
state when AREF is active and V1Time is active, a third state when
AREF is active and V2Time is active, and a fourth state when AREF
is active and neither V1Time nor V2Time are inactive. In some
embodiments, V1Time and V2Time may be prohibited from being active
at the same time. In some embodiments, the targeted refresh address
controller circuit 244 may favor one timing signal over another.
For example, if both V1Time and V2Time are active, targeted refresh
address control circuit 244 may favor V1Time and provide RHR in the
second state.
In some embodiments, the multiplexer 242 may provide V1ADD as RXADD
when RHR is in a state indicating AREF and V1Time are active,
provide V2ADD as RXADD when RHR is in a state indicating AREF and
V2Time are active, and provide Pre_RXADD when RHR is in a state
indicating only AREF is active. When AREF is inactive, no address
may be provided as RXADD and/or the row decoder circuit 208 may
ignore RXADD when AREF is inactive.
The row decoder circuit 208 may perform one or more operations on
the memory array (not shown) based on the received signals and
addresses. For example, responsive to the activation signal ACT and
the row address XADD (and AREF being at a low logic level), the row
decoder circuit 208 may direct one or more access operations (for
example, a read operation) on the specified row address XADD.
Responsive to the AREF signal being active, the row decoder circuit
208 may refresh the refresh address RXADD.
Although the example illustrated in FIG. 2 shows two victim steal
rate timing circuits and two victim address generators, it is
understood that additional victim steal rate timing circuits and
victim address generators may be included in other embodiments. For
example, it may be desirable to have separate steal rate timing for
additional victim word line types (e.g., R+/-3, R+/-4) and perform
targeted refresh operations on these additional victim word
lines.
FIG. 3 is a circuit diagram of an example targeted refresh address
controller circuit 300 according to an embodiment of the present
disclosure. In some embodiments, the targeted refresh address
controller circuit 300 may be included in targeted refresh address
controller circuit 244 shown in FIG. 2. For context, a multiplexer
302 is also shown in FIG. 3. Multiplexer 302 may be included in
multiplexer 242 shown in FIG. 2 in some embodiments.
The targeted refresh address controller circuit 300 may receive
refresh signal AREF, a first timing signal V1Time, and a second
timing signal V2Time. In some embodiments, the refresh signal AREF
may be provided by a command control circuit such as command
control circuit 106 shown in FIG. 1. In some embodiments, the
refresh signal AREF may be provided via a DRAM interface such as
DRAM interface 226 shown in FIG. 2. In some embodiments, the first
timing signal V1Time and/or the second timing signal V2Time may be
provided by victim steal rate timing circuits, such as first victim
steal rate timing circuit 238 and second victim steal rate timing
circuit 240 shown in FIG. 2. Based on the refresh signal AREF and
timing signals V1Time and V2Time, the targeted refresh address
controller circuit 300 may provide control signal RHR to the
multiplexer 302. The state of the control signal RHR may determine
what row address is provided as the refresh address RXADD. In the
example shown in FIG. 3, the control signal RHR is a two-bit signal
including a least significant bit RHR_LSB and a most significant
bit RHR_MSB.
The multiplexer 302 may provide a first victim row address V1ADD, a
second victim row address V2ADD, or an auto-refresh address
Pre-RXADD as RXADD depending on the state of the RHR signal. In
some embodiments, the first victim row address V1ADD and/or second
victim row address V2ADD may be provided by victim row address
generators, such as first victim row address generator 232 and
second victim row address generator 234 shown in FIG. 2. In some
embodiments, the auto-refresh address Pre_RXADD may be provided by
an auto-refresh address generator, such as AREF address generator
236 shown in FIG. 2. In some embodiments, the first victim row
address V1ADD may include one or more victim row addresses that
correspond to one or more victim word lines having a first physical
relationship to an aggressor word line. In some embodiments, the
second victim row address V2ADD may include one or more victim row
addresses that correspond to one or more victim word lines having a
second physical relationship to the aggressor word line. For
example, the first victim row address V1ADD may correspond to
victim word lines physically adjacent to the aggressor word line
and the second victim row address V2ADD may correspond to victim
word lines physically adjacent to the victim word lines
corresponding to V1ADD.
In some embodiments, the targeted refresh address controller
circuit 300 may include a first AND gate 304 that receives the AREF
signal at a first input and an inverted V2Time signal at a second
input. The V2Time signal may be inverted by inverter 306. A second
AND gate 308 may receive the AREF signal and the V1Time signal at
its inputs. The outputs of the first AND gate 304 and the second
AND gate 308 may be provided to a first OR gate 310. Based on the
inputs, the first OR gate 310 may output RHR_LSB. The targeted
refresh address controller circuit 300 may include a third AND gate
312 that receives AREF and V2Time signals as inputs. A fourth AND
gate 314 may receive the AREF and V1Time signals as inputs. The
outputs of the third AND gate 312 and the fourth AND gate 314 may
be provided to a second OR gate 316. The OR gate 316 may provide
RHR_MSB as an output.
In the example shown in FIG. 3, the multiplexer 302 is configured
to provide Pre_RXADD when RHR is in state `00` or `01,` provide
V2ADD when RHR is in state `10,` and provide V1ADD when RHR is in
state `11.` In operation, the targeted refresh address controller
circuit 300 provides RHR in state `00` when AREF is inactive (e.g.,
logic low) regardless of the states of V1Time and V2Time. Although
the multiplexer 302 may provide Pre_RXADD as RXADD in this state,
as mentioned previously, it may be ignored by a row decoder circuit
since a refresh operation is not occurring. When AREF is active
(e.g., logic high) and V1Time and V2Time are inactive, RHR is in
state `01.` In response, the multiplexer 302 may provide Pre_RXADD
as RXADD, which may be received by a row decoder circuit for use
during a refresh operation. When AREF and V1Time are active and
V2Time is inactive, RHR is in state `11` and the multiplexer 302
provides victim row address V1ADD as RXADD. When AREF and V2Time
are active and V1Time is inactive, RHR is in state `10` and the
multiplexer 302 provides victim row address V2ADD as RXADD.
In the example shown in FIG. 3, when AREF, V1Time, and V2Time are
all active, RHR is in a state `11` and VADD is provided as RXADD.
Thus, in the event of a conflict between V1Time and V2Time, the
victim word lines associated with V1ADD are favored for refreshing
over word lines associated with V2ADD. This may be desirable if, as
in the example described above, the word lines associated with
V1ADD are in closer physical proximity to the aggressor word line
than word lines associated with V2ADD. However, in other
embodiments, alternative logic gates may be provided to favor word
lines associated with V2ADD over word lines associated with V1ADD
when there is a conflict between V1Time and V2Time. In other
embodiments, additional circuitry and/or logic gates may be
provided that prevent V1Time and V2Time from being active at the
same time.
Although not shown in FIG. 3, in some embodiments, RHR_MSB may be
provided to an auto-refresh address generator, such as AREF address
generator 236 shown in FIG. 2. The auto-refresh address generator
may use the RHR_MSB signal to pause the generation of auto-refresh
addresses during targeted refresh address operations as discussed
previously with reference to FIG. 2.
FIG. 4 is an example timing diagram of a refresh signal, a first
timing signal, and a second timing signal in accordance with an
embodiment of the present disclosure. Timing diagram 400 shows
refresh signal AREF, first timing signal V1Time, and second timing
signal V2Time. In some embodiments, the refresh signal AREF may be
provided by a command control circuit such as command control
circuit 106 shown in FIG. 1. In some embodiments, the refresh
signal AREF may be provided via a DRAM interface such as DRAM
interface 226 shown in FIG. 2. In some embodiments, the first
timing signal V1Time and/or the second timing signal V2Time may be
provided by victim steal rate timing circuits, such as first victim
steal rate timing circuit 238 and second victim steal rate timing
circuit 240 shown in FIG. 2. AREF, V1Time, and V2Time may be used
to control a targeted refresh address controller circuit, such as
targeted refresh address controller circuit 244 shown in FIG. 2 or
targeted refresh address controller circuit 300 shown in FIG. 3.
Other components of a refresh control circuit, such as refresh
control circuit 116 shown in FIG. 1 or refresh control circuit 216
shown in FIG. 2, may receive AREF, V1Time, and/or V2Time in some
embodiments.
The timing diagram 400 as shown displays the state of the signals
for a refresh control circuit which refreshes first victim word
lines at a first rate based off of the rate of timing signal
V1Time, and second victim word lines refreshed at a second rate
based off of the rate of timing signal V2Time. In this example, the
first victim word lines are a pair of word lines adjacent to an
aggressor word line. The first victim word lines may be associated
with a victim row address V1ADD. The second victim word lines are a
pair of word lines which are each adjacent to one of the first
victim word lines. The second victim word lines may be associated
with a victim row address V2ADD. Other circuits may employ other
operations wherein, for example, neither set of word lines are
adjacent to the aggressor word line.
The first two line of FIG. 6 shows a portion of the refresh signal
AREF. The refresh signal AREF may be a sequence of pulses (e.g.,
from a low to a high logic level for a set duration). The refresh
signal AREF may occur in a set pattern, at regular intervals in
time. The refresh signal AREF may control refresh operations, which
refreshes one or more word lines of a memory. As discussed herein,
the refresh signal AREF may be used to trigger a refresh operation
in the memory. As shown, some of the individual pulses have been
labeled "T" or "A" to indicate that a targeted refresh operation or
an auto-refresh operation is being conducted, respectively, during
the period when that particular AREF pulse is active.
The second line of FIG. 4 shows first timing signal V1Time. As
shown, the first command signal V1Time is a periodic pulse signal.
The first timing signal V1Time may have a duration longer than the
duration of each of the pulses of the refresh signal AREF in some
embodiments. In this example, the first timing signal V1Time
indicates that word lines adjacent to an aggressor word line are to
be refreshed (e.g., the refreshed addresses are V1ADD). When the
first timing signal V1Time is active, a first activation of refresh
signal AREF will instead refresh a first adjacent victim word line
(e.g., R+1), and the second activation of refresh signal AREF will
refresh a second adjacent victim word line (e.g., R-1).
The third line of FIG. 4 shows second timing signal V2Time. As
shown, the second timing signal V2Time may also be a periodic pulse
signal. In the example shown in FIG. 4, the frequency of second
timing signal V2Time is different than the frequency of first
timing signal V1Time. The pulse of the second timing signal V2Time
may have a duration equal to a duration of the pulse of the first
timing signal V1Time in some embodiments. In this example, the
second timing signal V2Time indicates that word lines adjacent to
the victim word lines adjacent to the aggressor word line are to be
refreshed (e.g., the refreshed addresses are V2ADD). When the
second timing signal V2Time is active, a first activation of
refresh signal AREF will instead refresh a first victim word line
(e.g., R+2), and the second activation of refresh signal AREF will
refresh a second victim word line (e.g., R-2).
FIG. 5 is an example aggressor row detector circuit 500 according
to an embodiment of the present disclosure. In some embodiments,
aggressor row detector circuit 500 may be included in aggressor row
decoder circuit 230 shown in FIG. 2. However, in other embodiments,
other aggressor row detector circuits may be included in aggressor
row decoder circuit 230. The aggressor row detector circuit 500 may
include a stack 501. The stack 501 may be a content addressable
memory (CAM) stack in some embodiments. The stack 501 may include
multiple registers (e.g., files) 502, each of which may have
corresponding fields 504, 506. In the embodiment shown in FIG. 5,
each register includes a field 504 configured to store a row
address (RowADD0-7) and a field 506 configured to store a
corresponding count value (ACntVal0-7). The fields 506 storing the
count values may be coupled to a comparator 508 which may be
coupled to pointers 512 through a counter scrambler 510. In some
embodiments, the fields 504 storing row addresses may be coupled to
one or more victim address generators (not shown in FIG. 5), such
first victim address generator 232 and/or second victim address
generator 234 shown in FIG. 2, and provide a matched address
HitXADD to the victim address generators. While the example in FIG.
5 shows eight registers 502 in the stack 501, it is understood that
the stack could include fewer or more registers. For example, the
stack 501 could have 128 registers. In another example, the stack
501 could have 1,024 registers.
Each time a row address XADD is provided to the registers 502, the
row address XADD may be compared to the fields 504. If the current
row address XADD is already stored in one of the registers 502,
then the count value in field 506 associated with the matching row
address in field 504 may be adjusted (e.g., increased). If the
current row address XADD is not already stored in one of the
registers 502, it may be added to the registers 502. If there is an
open register (e.g., a register without a row address) then the row
address XADD may be stored in the open register. If there is not an
open register, then the register 502 associated with the count
value which has the lowest value (as indicated by the pointers 512)
may have its row address replaced with the current row address XADD
and count value reset.
The comparator 508 may compare the count values in fields 506 to a
threshold value to determine if a count value for a row address has
matched or exceeded the threshold value (e.g., 2,000, 3,000,
5,000). In some embodiments, the comparator 508 may further compare
the count values to determine which row address is associated with
the lowest count value. The fields 506 corresponding to the minimum
count value and count values that meet or exceed the threshold
value may be provided to a counter scrambler 510, which may match
the above threshold value fields and minimum count value field to
their respective associated row address fields 504. The pointers
512 may point to the row addresses in fields 504 associated with
count values at or above the threshold value and may point to the
fields 504 associated with the minimum count value in fields 506.
The threshold value pointer(s) may be used to reset the counts of
the row addresses determined to be aggressors. In some embodiments,
the threshold value pointer(s) may be used to provide the
corresponding row address(es) to the victim address generators as
HitXADD. The minimum count value pointer may be used to overwrite a
register 502 when a new row address XADD is received and there is
no open register 502 to store it in.
FIG. 6 is a flow chart 600 of a method according to an embodiment
of the present disclosure. At block 602, a step of "providing a
first signal having a first frequency" may be performed. In some
embodiments, the first signal may be generated by a victim steal
rate timing circuit, such as first victim steal rate timing circuit
238 shown in FIG. 2. At block 604, a step of "providing a second
signal having a second frequency" may be performed. In some
embodiments, the second signal may be generated by a victim steal
rate timing circuit, such as second victim steal rate timing
circuit 240 shown in FIG. 2. In some embodiments, the second
frequency is independent of the first frequency. In some
embodiments, the second frequency is different than the first
frequency. At block 606, a step of "refreshing a first victim word
line" may be performed. In some embodiments, the refreshing may be
based, at least in part, on the first frequency. At block 608, a
step of "refreshing a second victim word line" may be performed. In
some embodiments, the refreshing may be based, at least in part, on
the second frequency.
In some embodiments, the method shown in flow chart 600 may further
include generating a control signal based, at least in part, on the
first signal and the second signal. In some embodiments, the
control signal may be generated by a targeted refresh address
controller circuit, such as targeted refresh address controller
circuit 244 shown in FIG. 2 or targeted refresh address controller
circuit 300 shown in FIG. 3. In some embodiments, the method shown
in flow chart 600 may further include providing a refresh address
for refreshing a word line based, at least in part, on the control
signal, wherein the refresh address is the first victim word line
or the second victim word line. In some embodiments, the refresh
address may be provided by a multiplexer, such as multiplexer 242
shown in FIG. 2 or multiplexer 302 shown in FIG. 3.
The apparatuses and methods described herein may allow for
independently controlling the steal rates for different victim word
lines, such as victim word lines that have different physical
distances from an aggressor word line. In some embodiments, a
refresh control circuit may include two or more timing circuits to
allow independent control of the steal rates for different victim
word lines. This may allow the targeted refresh rates for each type
of victim word line to be optimized, which may reduce
over-refreshing of the word lines.
Of course, it is to be appreciated that any one of the examples,
embodiments or processes described herein may be combined with one
or more other examples, embodiments and/or processes or be
separated and/or performed amongst separate devices or device
portions in accordance with the present systems, devices and
methods.
Finally, the above-discussion is intended to be merely illustrative
of the present system and should not be construed as limiting the
appended claims to any particular embodiment or group of
embodiments. Thus, while the present system has been described in
particular detail with reference to exemplary embodiments, it
should also be appreciated that numerous modifications and
alternative embodiments may be devised by those having ordinary
skill in the art without departing from the broader and intended
spirit and scope of the present system as set forth in the claims
that follow. Accordingly, the specification and drawings are to be
regarded in an illustrative manner and are not intended to limit
the scope of the appended claims.
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