Processing in memory

Abstract

Apparatuses and methods are provided for processing in memory. An example apparatus comprises a host and a processing in memory (PIM) capable device coupled to the host via an interface comprising a sideband channel. The PIM capable device comprises an array of memory cells coupled to sensing circuitry and is configured to perform bit vector operations on data stored in the array, and the host comprises a PIM control component to perform virtual address resolution for PIM operations prior to providing a number of corresponding bit vector operations to the PIM capable device via the sideband channel.

Parent Case Text

PRIORITY INFORMATION

This application is a Continuation of U.S. application Ser. No. 15/693,378, filed Aug. 31, 2017, the contents of which are included herein by reference.

Description

TECHNICAL FIELD

The present disclosure relates generally to semiconductor memory and methods, and more particularly, to apparatuses and methods for processing in memory.

BACKGROUND

Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other computing systems. There are many different types of memory including volatile and non-volatile memory. Volatile memory can require power to maintain its data (e.g., host data, error data, etc.) and includes random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), and thyristor random access memory (TRAM), among others. Non-volatile memory can provide persistent data by retaining stored data when not powered and can include NAND flash memory, NOR flash memory, and resistance variable memory such as phase change random access memory (PCRAM), resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM), such as spin torque transfer random access memory (STT RAM), among others.

Computing systems often include a number of processing resources (e.g., one or more processors), which may retrieve and execute instructions and store the results of the executed instructions to a suitable location. A processing resource (e.g., CPU) can comprise a number of functional units such as arithmetic logic unit (ALU) circuitry, floating point unit (FPU) circuitry, and/or a combinatorial logic block, for example, which can be used to execute instructions by performing logical operations such as AND, OR, NOT, NAND, NOR, and XOR, and invert (e.g., inversion) logical operations on data (e.g., one or more operands). For example, functional unit circuitry may be used to perform arithmetic operations such as addition, subtraction, multiplication, and/or division on operands via a number of logical operations.

A number of components in a computing system may be involved in providing instructions to the functional unit circuitry for execution. The instructions may be executed, for instance, by a processing resource such as a controller and/or host processor. Data (e.g., the operands on which the instructions will be executed) may be stored in a memory array that is accessible by the functional unit circuitry. The instructions and/or data may be retrieved from the memory array and sequenced and/or buffered before the functional unit circuitry begins to execute instructions on the data. Furthermore, as different types of operations may be executed in one or multiple clock cycles through the functional unit circuitry, intermediate results of the instructions and/or data may also be sequenced and/or buffered. A sequence to complete an operation in one or more clock cycles may be referred to as an operation cycle. Time consumed to complete an operation cycle costs in terms of processing and computing performance and power consumption of a computing device and/or system.

In many instances, the processing resources (e.g., processor and/or associated functional unit circuitry) may be external to the memory array, and data is accessed via a bus between the processing resources and the memory array to execute a set of instructions. Processing performance may be improved in a processor-in-memory (PIM) device, in which a processor may be implemented internal and/or near to a memory (e.g., directly on a same chip as the memory array).

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of an apparatus in the form of a computing system including a memory device for processing in memory in accordance with a number of embodiments of the present disclosure.

FIG. 2 is a schematic diagram illustrating a portion of a memory device in accordance with a number of embodiments of the present disclosure.

FIG. 3 is a schematic diagram illustrating another portion of a memory device in accordance with a number of embodiments of the present disclosure.

FIG. 4 is a logic table illustrating logic operation results implemented using the circuitry shown in FIG. 3 in accordance with a number of embodiments of the present disclosure.

DETAILED DESCRIPTION

The present disclosure includes apparatuses and methods associated with processing in memory. In one example embodiment, an example apparatus comprises a host and a processing in memory (PIM) capable device coupled to the host via an interface comprising a sideband channel. The PIM capable device comprises an array of memory cells coupled to sensing circuitry and is configured to perform bit vector operations on data stored in the array, and the host comprises a PIM control component to perform virtual address resolution for PIM operations prior to providing a number of corresponding bit vector operations to the PIM capable device via the sideband channel.

The sensing circuitry includes a sense amplifier and a compute component. In some embodiments, the apparatus may include a PIM control device (e.g., bit vector operation circuitry), which may include timing circuitry and/or timing management circuitry. The PIM control device may be configured to control timing of operations for the array and receive logical operation commands to enable performance of memory operations. In some embodiments, the PIM control device may be configured to perform arbitration and/or control the timing of performance of Boolean functions responsive to receipt of commands from a host.

As used herein, a processing in memory (PIM) capable device refers to a memory device capable of performing logical operations on data stored in an array of memory cells using a processing resource internal to the memory device (e.g., without transferring the data to an external processing resource such as a host processor). As an example, a PIM capable device can include a memory array coupled to sensing circuitry comprising sensing components operable as 1-bit processing elements (e.g., to perform parallel processing on a per column basis). A PIM capable device can also perform memory operations in addition to logical operations performed "in memory," which can be referred to as "bit vector operations." As an example, PIM capable device can comprise a dynamic random access memory (DRAM) array with memory operations including memory access operations such as reads (e.g., loads) and writes (e.g., stores), among other operations that do not involve operating on the data (e.g., such as by performing a Boolean operation on the data). For example, a PIM capable device can operate a DRAM array as a "normal" DRAM array and/or as a PIM DRAM array depending on a type of program being executed (e.g., by a host), which may include both memory operations and bit vector operations. For example, bit vector operations can include logical operations such as Boolean operations (e.g., AND, OR, XOR, etc.) and transfer operations such as shifting data values in the array and inverting data values, for example.

As used herein, a PIM operation can refer to various operations associated with performing in memory processing utilizing a PIM capable device. An operation hierarchy can be used to define a PIM operation. For example, a first (e.g., lowest) level in the operation hierarchy can include bit vector operations (e.g., fundamental logical operations, which may be referred to as "primitive" operations). A next (e.g., middle) level in the hierarchy can include composite operations, which comprise multiple bit vector operations. For instance, composite operations can include mathematical operations such as adds, multiplies, etc., which can comprise a number of logical ANDs, ORs, XORs, shifts, etc. A third (e.g., highest) level in the hierarchy can include control flow operations (e.g., looping, branching, etc.) associated with executing a program whose execution involves performing processing using a PIM capable device.

As described in more detail herein, PIM operations may be executed by various components within a system comprising a PIM capable device. For instance, a first PIM control component (e.g., control logic, which may be referred to as a "scalar unit"), which can be located on a host, may execute control flow operations and provide composite operations to a second PIM control component (e.g., a sequencer), which can also be located on the host. In a number of embodiments, the second control component can provide low level bit vector operations to a PIM control component located on the PIM capable device (e.g., bit vector timing circuitry), which can then execute the bit vector operations in memory and return results to the host. As described further herein, an interface used to transfer PIM operations between a PIM capable device and a host can comprise a sideband channel, which can be a bus separate from a typical memory interface, such as a DDR interface, used to transfer commands, addresses, and/or data. Also, in a number of embodiments, providing PIM control components on the host can provide benefits such as allowing a PIM program to use virtual addressing (e.g., by resolving virtual addresses on the host since the PIM capable device may operate only on physical addresses).

Timing circuitry and control logic associated with the memory device may be in different clock domains and/or operate at different clock speeds. In at least one embodiment, the timing circuitry is separate from other control registers, (e.g., double data rate (DDR) registers), used to control read and write access requests for the array, (e.g., in a DRAM array).

In the following detailed description of the present disclosure, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration how one or more embodiments of the disclosure may be practiced. These embodiments are described in sufficient detail to enable those of ordinary skill in the art to practice the embodiments of this disclosure, and it is to be understood that other embodiments may be utilized and that process, electrical, and/or structural changes may be made without departing from the scope of the present disclosure. As used herein, designators such as "N", "M", etc., particularly with respect to reference numerals in the drawings, indicate that a number of the particular feature so designated can be included. As used herein, "a number of" a particular thing can refer to one or more of such things (e.g., a number of memory arrays can refer to one or more memory arrays). A "plurality of" is intended to refer to more than one of such things.

The figures herein follow a numbering convention in which the first digit or digits correspond to the drawing figure number and the remaining digits identify an element or component in the drawing. Similar elements or components between different figures may be identified by the use of similar digits. For example, 206 may reference element "06" in FIG. 2, and a similar element may be referenced as 306 in FIG. 3. As will be appreciated, elements shown in the various embodiments herein can be added, exchanged, and/or eliminated so as to provide a number of additional embodiments of the present disclosure. In addition, as will be appreciated, the proportion and the relative scale of the elements provided in the figures are intended to illustrate certain embodiments of the present invention, and should not be taken in a limiting sense.

FIG. 1 is a block diagram of an apparatus in the form of a computing system 100 including a memory device 120 for processing in memory (e.g., a "PIM capable device") in accordance with a number of embodiments of the present disclosure. The memory device 120 may be referred to herein as a "PIM capable device" or "PIM capable memory device." The PIM capable device may comprise an array of memory cells coupled to sensing circuitry, as described in more detail, here. As used herein, a memory device 120 for processing in memory, controller 140, channel controller 143, memory array 130, and/or sensing circuitry 150 might also be separately considered an "apparatus."

System 100 includes a host 111 coupled (e.g., connected) to memory device 120 for processing in memory, which includes a memory array 130. Host 111 can be a host system such as a personal laptop computer, a desktop computer, a digital camera, a smart phone, or a memory card reader, among various other types of hosts. Host 111 can include a system motherboard and/or backplane and can include a number of processing resources (e.g., one or more processors, microprocessors, or some other type of controlling circuitry). The system 100 can include separate integrated circuits or both the host 111 and the memory device 120 for processing in memory can be part of a same integrated circuit (e.g., on a same chip). The system 100 can be, for instance, a server system and/or a high performance computing (HPC) system and/or a portion thereof. Although the example shown in FIG. 1 illustrates a system having a Von Neumann architecture, embodiments of the present disclosure can be implemented in non-Von Neumann architectures, which may not include one or more components (e.g., CPU, ALU, etc.) often associated with a Von Neumann architecture.

In some embodiments, the host 111 uses virtual addressing while the memory device 120 for processing in memory uses physical addressing. In order to perform PIM operations on the memory device 120 for processing in memory (e.g., in order to perform bit vector operations using the memory device 120 for processing in memory), the virtual addresses used by the host 111 must be translated into corresponding physical addresses, which are used by the memory device 120 for processing in memory. In some embodiments, a PIM control component (e.g., control logic 131) and/or memory management unit (MMU) controller 134 may perform address resolution to translate the virtual addresses used by the host 111 into the respective physical addresses used by the memory device 120 for processing in memory. In some embodiments, the PIM control component(s) may perform virtual address resolution for PIM operations prior to providing a number of corresponding bit vector operations to the memory device 120 (e.g., the PIM capable device) via the sideband channel 157.

The host 111 may include various components including PIM control components (e.g., control logic 131, a sequencer 132), a channel controller 143, and a MMU controller 134. The control logic 131 may be configured to execute control flow commands associated with an executing PIM program and to provide composite commands to the sequencer 132. The control logic 131 may be, or may include, a RISC type controller configured to generate and issue an extensible set of composite operation PIM commands that includes commands, different from DDR commands to the sequencer 132. In some embodiments, the control logic 131 may be configured to issue composite operation commands to cause bit vector operations to be performed on the memory devices 120. In some embodiments, the composite operation commands may be transferred from the control logic 131 to the memory device 120 for processing in memory (e.g., via sequencer 132 and sideband channel 157). As shown in FIG. 1, the host 111 (and control logic 131, sequencer 132, and/or MMU controller 134) may be located physically separate from the memory device 120 and/or the array 130.

The control logic 131 may, in some embodiments, decode microcode instructions into function calls, which may be microcode function calls, associated with performing a bit vector operation, implemented by the sequencer 132. The microcode function calls can be the operations that the sequencer 132 receives and/or executes to cause the memory device 120 for processing in memory to perform particular bit vector operations using the sensing circuitry, such as sensing circuitry 150.

As shown in FIG. 1, the control logic 131 and MMU controller 134 are located on the host 111, which may allow for the control logic 131 and/or the MMU controller 134 to access virtual addresses stored on the host 111 and perform virtual to physical address resolution on the physical addresses stored on the host 111 prior to transferring instructions to the memory device 120 for processing in memory.

As used herein, a "bit vector" can refer to a physically contiguous number of bits, whether physically contiguous in rows (e.g., horizontally oriented) or columns (e.g., vertically oriented). A "PIM capable device" refers to a memory device configured to perform bit vector operations such as logical operations and/or transfer operations on a number of contiguous portions (e.g., "chunks") of virtual address space. For example, a chunk of virtual address space may have a bit length of 256 bits. A chunk may or may not be contiguous sequentially to other chunks in the virtual address space.

The MMU controller 134 can reside on the host 111, as shown in FIG. 1. In some embodiments, the MMU controller may be a standard MMU controller such as an ARM.RTM. CoreLink.RTM. MMU-500 MMU controller. The MMU controller may be responsible for performing the translation of virtual memory addresses (e.g., addresses associated with the host 111) to physical addresses (e.g., addresses associated with the memory device 120 for processing in memory). The MMU controller 134 may also perform memory protection operations, cache control, and/or bus arbitration operations.

The timing circuitry 133 may provide timing to coordinate performance of logical operations and be responsible for providing conflict free access to the arrays, such as array 130 in FIG. 1. In various embodiments, the controller 140 and/or the timing management circuitry 135 may generate status information, which may be transferred to or from host 111, for example via the sideband channel 157. The sideband channel 157 may be independent of (e.g., separate from) a double data rate (DDR) memory interface (e.g., control bus 154) that may be used to transfer (e.g., pass) DDR commands between the host 111 and the memory device 120 for processing in memory. That is, in some embodiments, the sideband channel 157 may be used to transfer commands to cause performance of bit vector operations from the host 111 to the memory device 120 for processing in memory while the control bus 154 is used to transfer DRAM commands from the host 111 to the memory device 120 for processing in memory. In some embodiments, the DRAM commands that are transferred via the control bus 154 may be commands to control operation of DRAM such as DDR1 SDRAM, DDR2 SDRAM, DDR3 SDRAM, and/or DDR4 SDRAM.

In some embodiments, the sequencer 132 may include a very large instruction word (VLIW) type controller configured to operate on logical operation commands and the control logic 131 may be configured to issue the logical operation commands to the sequencer 132 in response to a signal from a processing resource (not shown) of the host 111. For example, the sequencer may be configured to sequence multiple logical operations so that composite operation commands may be issued by the sequencer 132. The control logic 131 may, in some embodiments, be configured to generate a VLIW as a bit vector operation command(s). The VLIW may comprise microcode instructions. The sequencer 132 may be, or may include, the VLIW type controller configured to decode the VLIW into a plurality of separate microcode instructions. For example, the sequencer 132 may decode the VLIW into instructions to cause performance of composite operations (e.g., ADD, MULTIPLY, etc.). In some embodiments, the composite operation commands may provide an entry point into a sequence of VLIW instructions to cause perform such composite operations. The sequencer 132 may be coupled to the memory device 120 for processing in memory and may pass commands to coordinate bit vector operations to the memory device 120 for processing in memory via sideband channel 157. The plurality of microcode instructions may be executable in sequence and/or in parallel by the sequencer 132 itself and/or by other components in the memory device 120 for processing in memory, (e.g., the bit vector operation timing circuitry 139, the timing circuitry 133, timing management circuitry 135, and/or the sensing circuitry 150).

For clarity, the system 100 has been simplified to focus on features with particular relevance to the present disclosure. The memory array 130 can be a DRAM array, SRAM array, STT RAM array, PCRAM array, TRAM array, RRAM array, NAND flash array, and/or NOR flash array, for instance. The array 130 can comprise memory cells arranged in rows coupled by access lines, which may be referred to herein as word lines or select lines, and columns coupled by sense lines, which may be referred to herein as data lines or digit lines. Although a single array 130 is shown in FIG. 1, embodiments are not so limited. For instance, memory device 120 for processing in memory may include a number of arrays 130 (e.g., a number of banks of DRAM cells, NAND flash cells, etc.).

The memory device 120 for processing in memory includes address circuitry 142 to latch address signals for data provided over a bus 156 (e.g., a data/address bus) through I/O circuitry 144. Status and/or exception information can be provided from the controller 140 on the memory device 120 for processing in memory to a channel controller 143, through a high speed interface (HSI) including a sideband channel 157, which in turn can be provided from the channel controller 143 to the host 111. Address signals are received through address circuitry 142 and decoded by a row decoder 146 and a column decoder 152 to access the memory array 130. Data can be read from memory array 130 by sensing voltage and/or current changes on the digit lines using sensing circuitry 150. The sensing circuitry 150 can read and latch a page (e.g., row) of data from the memory array 130. The I/O circuitry 144 can be used for bi-directional data communication with host 111 over the bus 156. The write circuitry 148 can be used to write data to the memory array 130. In some embodiments, bus 154 may serve as both a control and address bus for DRAM control and addressing (e.g., in accordance with a DDR protocol in which bus 154 operates as a unidirectional data bus). Although shown as separate buses in FIG. 1, in some embodiments, bus 154 and bus 156 may not be separate buses.

Controller 140 (e.g., memory controller) decodes signals provided by control bus 154 from the host 111. These signals can include chip enable signals, write enable signals, and address latch signals that are used to control DRAM operations performed on the memory array 130, including data read, data write, and data erase operations. In various embodiments, the controller 140 is responsible for executing instructions from the host 111 and sequencing access to the array 130. The controller 140 can be a state machine, sequencer, or some other type of controller and include hardware and/or firmware (e.g., microcode instructions) in the form of an application specific integrated circuit (ASIC). In a number of embodiments, the controller 140 may include bit vector operation timing circuitry 139. The controller 140 can control, for example, sensing circuitry in accordance with embodiments described herein. For example, the controller 140 can control generation of clock signals and application of the clock signals to compute components in association with performing bit vector operations.

As shown in FIG. 1, the bit vector operation timing circuitry 139 may include timing circuitry 133 and timing management circuitry 135. The timing circuitry 133 may include a FIFO buffer to provide timing coordination with the sensing circuitry 150 associated with the array 130 of memory cells. In some embodiments, the timing circuitry 133 may be a state machine such as an atomic state machine.

The control logic 131, sequencer 132, and/or MMU controller 134 may assist in resolving virtual memory to physical memory decoding between the host 111 and the RAS 136, array 130, and/or sensing circuitry 150. For example, in some embodiments, the host 111 may utilize virtual memory addressing, while the components associated with the memory device 120 for processing in memory (e.g., controller 140, RAS 136, array 130, sensing circuitry 150, etc.) may utilize physical addressing.

In some embodiments, the sequencer 132 and/or control logic 131 may be configured to resolve virtual addresses into physical addresses using a translation lookaside buffer (TLB) and/or a MMU controller 134. These resolved addresses may be passed via the sideband channel 157 to the controller 140 and/or bit vector operation timing circuitry 139. The resolved physical addresses may then be used by the bit vector operation timing circuitry to coordinate performance of bit vector operations using the array 130 and/or sensing circuitry 150.

By resolving virtual addresses to physical addresses at the host 111, for example by using the sequencer 132 and/or control logic 131 to resolve virtual addresses to physical addresses, a reliance on pinning memory at a boot of the computing device 100 may be alleviated. In addition, in some embodiments, incorrect address resolutions may be identified and/or corrected by the control logic 131 and/or sequencer 132, which may allow for improved alignment of data values in the array 130.

The timing management circuitry 135 may be configured to coordinate timing of logical operations (e.g., a sequence of logical operations), associated with the bit vector operation, performed using a row address strobe (RAS) component 136 associated with the array 130. The RAS component 136 may be configured to send and/or receive a RAS signal to or from the memory array 130 to identify and/or select a row address of the array 130. The memory device 120 for processing in memory may, in some embodiments, be configured to execute a DRAM operation such as a memory array access request, which may be issued by the host 111 via bus 154. In some embodiments, the timing management circuitry 135 may be configured to execute instructions to control timing of performance of a bit vector operation.

In one or more embodiments, portions of the controller 140, (e.g., bit vector operation timing circuitry 139, timing circuitry 133, and/or timing management circuitry 135), can be a reduced instruction set computer (RISC) type controller operating on 32 and/or 64 bit length instructions. In various embodiments, the timing management circuitry 135 is responsible for executing instructions received from the timing circuitry 133 to cause performance of bit vector operations involving data values associated with the sensing circuitry 150.

As described further below, in a number of embodiments, the sensing circuitry 150 can comprise a plurality of sensing components, which can each include a sense amplifier and a compute component. The compute component may serve as an accumulator, and the sensing circuitry can be used to perform bit vector operations (e.g., on data associated with complementary digit lines). In a number of embodiments, the sensing circuitry 150 can be used to perform bit vector operations using data stored in array 130 as inputs and/or store the results of the operations back to the array 130 without transferring data via a digit line address access (e.g., without firing a column decode signal). For instance, various operations (e.g., bit vector operations) can be performed using, and within, sensing circuitry 150 rather than (or in association with) being performed by processing resources external to the sensing circuitry (e.g., by a processing resource associated with host 111 and/or other processing circuitry, such as ALU circuitry, located on memory device 120 for processing in memory (e.g., on controller 140 or elsewhere)). In a number of embodiments, the sensing circuitry 150 (e.g., the number of sensing components) can be used to execute bit vector operations in a SIMD (single instruction multiple data) manner with the sensing components serving as 1-bit processing elements on a per column basis. In embodiments in which the sensing circuitry 150 executes bit vector operations, it can serve as and/or be referred to as an in memory processor.

In various previous approaches, data associated with an operand, for instance, would be read from memory via sensing circuitry and provided to external ALU circuitry via I/O lines (e.g., via local I/O lines and/or global I/O lines). The external ALU circuitry could include a number of registers and would perform bit vector operations using the operands, and the result would be transferred back to the array via the I/O lines. In contrast, in a number of embodiments of the present disclosure, sensing circuitry 150 is configured to perform bit vector operations on data stored in memory array 130 and store the result back to the memory array 130 without enabling an I/O line (e.g., a local I/O line) coupled to the sensing circuitry 150. The sensing circuitry 150 can be formed on pitch with the memory cells of the array. For example, a compute component may conform to a same pitch as adjacent digit lines of the array such that the compute component and the sense amplifier obey a particular sense line pitch constraint (e.g., 4F, 6F, etc., where "F" is a feature size).

In a number of embodiments, circuitry external to array 130 and sensing circuitry 150 may not be needed to perform operations as the sensing circuitry 150 can perform the appropriate bit vector operations without the use of an external processing resource. Therefore, the sensing circuitry 150 may be used to compliment and/or to replace, at least to some extent, such an external processing resource (or at least the bandwidth consumption of such an external processing resource).

However, in a number of embodiments, the sensing circuitry 150 may be used to perform logical operations (e.g., to execute instructions) in addition to logical operations performed by an external processing resource (e.g., host 111). For instance, host 111 and/or sensing circuitry 150 may be limited to performing only certain logical operations and/or a certain number of logical operations.

Enabling an I/O line can include enabling (e.g., turning on) a transistor having a gate coupled to a decode signal (e.g., a column decode signal) and a source/drain coupled to the I/O line. However, embodiments are not limited to performing logical operations using sensing circuitry (e.g., 150) without enabling column decode lines of the array. Whether or not local I/O lines are used in association with performing logical operations via sensing circuitry 150, the local I/O line(s) may be enabled in order to transfer a result to a suitable location other than back to the array 130 (e.g., to an external register).

FIG. 2 is a schematic diagram illustrating a portion of a memory device in accordance with a number of embodiments of the present disclosure. The sensing component 250 represents one of a number of sensing components that can correspond to sensing circuitry 150 shown in FIG. 1.

In the example shown in FIG. 2, the memory array 230 is a DRAM array of 1T1C (one transistor one capacitor) memory cells in which a transistor serves as the access device and a capacitor serves as the storage element; although other embodiments of configurations can be used (e.g., 2T2C with two transistors and two capacitors per memory cell). In this example, a first memory cell comprises transistor 202-1 and capacitor 203-1, and a second memory cell comprises transistor 202-2 and capacitor 203-2, etc. In a number of embodiments, the memory cells may be destructive read memory cells (e.g., reading the data stored in the cell destroys the data such that the data originally stored in the cell is refreshed after being read).

The cells of the memory array 230 can be arranged in rows coupled by access lines 204-X (Row X), 204-Y (Row Y), etc., and columns coupled by pairs of complementary sense lines (e.g., digit lines 205-1 labelled DIGIT(n) and 205-2 labelled DIGIT(n) in FIG. 2). Although only one pair of complementary digit lines are shown in FIG. 2, embodiments of the present disclosure are not so limited, and an array of memory cells can include additional columns of memory cells and digit lines (e.g., 4,096, 8,192, 16,384, etc.).

Memory cells can be coupled to different digit lines and word lines. For instance, in this example, a first source/drain region of transistor 202-1 is coupled to digit line 205-1, a second source/drain region of transistor 202-1 is coupled to capacitor 203-1, and a gate of transistor 202-1 is coupled to word line 204-Y. A first source/drain region of transistor 202-2 is coupled to digit line 205-2, a second source/drain region of transistor 202-2 is coupled to capacitor 203-2, and a gate of transistor 202-2 is coupled to word line 204-X. A cell plate, as shown in FIG. 2, can be coupled to each of capacitors 203-1 and 203-2. The cell plate can be a common node to which a reference voltage (e.g., ground) can be applied in various memory array configurations.

The digit lines 205-1 and 205-2 of memory array 230 are coupled to sensing component 250 in accordance with a number of embodiments of the present disclosure. In this example, the sensing component 250 comprises a sense amplifier 206 and a compute component 231 corresponding to a respective column of memory cells (e.g., coupled to a respective pair of complementary digit lines). The sense amplifier 206 is coupled to the pair of complementary digit lines 205-1 and 205-2. The compute component 231 is coupled to the sense amplifier 206 via pass gates 207-1 and 207-2. The gates of the pass gates 207-1 and 207-2 can be coupled to selection logic 213.

The selection logic 213 can include pass gate logic for controlling pass gates that couple the pair of complementary digit lines un-transposed between the sense amplifier 206 and the compute component 231 and swap gate logic for controlling swap gates that couple the pair of complementary digit lines transposed between the sense amplifier 206 and the compute component 231. The selection logic 213 can be coupled to the pair of complementary digit lines 205-1 and 205-2 and configured to perform logical operations on data stored in array 230. For instance, the selection logic 213 can be configured to control continuity of (e.g., turn on/turn off) pass gates 207-1 and 207-2 based on a selected logical operation that is being performed.

The sense amplifier 206 can be operated to determine a data value (e.g., logic state) stored in a selected memory cell. The sense amplifier 206 can comprise a cross coupled latch 215 (e.g., gates of a pair of transistors, such as n-channel transistors 227-1 and 227-2 are cross coupled with the gates of another pair of transistors, such as p-channel transistors 229-1 and 229-2), which can be referred to herein as a primary latch. However, embodiments are not limited to this example.

In operation, when a memory cell is being sensed (e.g., read), the voltage on one of the digit lines 205-1 or 205-2 will be slightly greater than the voltage on the other one of digit lines 205-1 or 205-2. An ACT signal and an RNL* signal can be driven low to enable (e.g., fire) the sense amplifier 206. The digit line 205-1 or 205-2 having the lower voltage will turn on one of the transistors 229-1 or 229-2 to a greater extent than the other of transistors 229-1 or 229-2, thereby driving high the digit line 205-1 or 205-2 having the higher voltage to a greater extent than the other digit line 205-1 or 205-2 is driven high.

Similarly, the digit line 205-1 or 205-2 having the higher voltage will turn on one of the transistors 227-1 or 227-2 to a greater extent than the other of the transistors 227-1 or 227-2, thereby driving low the digit line 205-1 or 205-2 having the lower voltage to a greater extent than the other digit line 205-1 or 205-2 is driven low. As a result, after a short delay, the digit line 205-1 or 205-2 having the slightly greater voltage is driven to the voltage of the supply voltage V.sub.CC through a source transistor, and the other digit line 205-1 or 205-2 is driven to the voltage of the reference voltage (e.g., ground) through a sink transistor. Therefore, the cross coupled transistors 227-1 and 227-2 and transistors 229-1 and 229-2 serve as a sense amplifier pair, which amplify the differential voltage on the digit lines 205-1 and 205-2 and operate to latch a data value sensed from the selected memory cell.

Embodiments are not limited to the sensing component configuration illustrated in FIG. 2. As an example, the sense amplifier 206 can be a current-mode sense amplifier and/or a single-ended sense amplifier (e.g., sense amplifier coupled to one digit line). Also, embodiments of the present disclosure are not limited to a folded digit line architecture such as that shown in FIG. 2.

As described further below, the sensing component 250 can be one of a plurality of sensing components selectively coupled to a shared I/O line. As such, the sensing component 250 can be used in association with reversing data stored in memory in accordance with a number of embodiments of the present disclosure.

In this example, the sense amplifier 206 includes equilibration circuitry 214, which can be configured to equilibrate the digit lines 205-1 and 205-2. The equilibration circuitry 214 comprises a transistor 224 coupled between digit lines 205-1 and 205-2. The equilibration circuitry 214 also comprises transistors 225-1 and 225-2 each having a first source/drain region coupled to an equilibration voltage (e.g., V.sub.DD/2), where V.sub.DD is a supply voltage associated with the array. A second source/drain region of transistor 225-1 is coupled to digit line 205-1, and a second source/drain region of transistor 225-2 is coupled to digit line 205-2. Gates of transistors 224, 225-1, and 225-2 can be coupled together and to an equilibration (EQ) control signal line 226. As such, activating EQ enables the transistors 224, 225-1, and 225-2, which effectively shorts digit lines 205-1 and 205-2 together and to the equilibration voltage (e.g., V.sub.DD/2). Although FIG. 2 shows sense amplifier 206 comprising the equilibration circuitry 214, embodiments are not so limited, and the equilibration circuitry 214 may be implemented discretely from the sense amplifier 206, implemented in a different configuration than that shown in FIG. 2, or not implemented at all.

As shown in FIG. 2, the compute component 231 can also comprise a latch, which can be referred to herein as a secondary latch 264. The secondary latch 264 can be configured and operated in a manner similar to that described above with respect to the primary latch 215, with the exception that the pair of cross coupled p-channel transistors (e.g., PMOS transistors) included in the secondary latch can have their respective sources coupled to a supply voltage (e.g., V.sub.DD), and the pair of cross coupled n-channel transistors (e.g., NMOS transistors) of the secondary latch can have their respective sources selectively coupled to a reference voltage (e.g., ground), such that the secondary latch is continuously enabled. The configuration of the compute component 231 is not limited to that shown in FIG. 2, and various other embodiments are feasible.

FIG. 3 is a schematic diagram illustrating circuitry portion of a memory device in accordance with a number of embodiments of the present disclosure. FIG. 3 shows a sense amplifier 306 coupled to a pair of complementary sense lines 305-1 and 305-2, logical operation select logic 313, and a compute component 331 coupled to the sense amplifier 306 via pass gates 307-1 and 307-2. The sense amplifier 306 shown in FIG. 3 can correspond to sense amplifier 206 shown in FIG. 2. The compute component 331 shown in FIG. 3 can correspond to sensing circuitry, including compute component, 150 in FIG. 1. The logical operation selection logic 313 shown in FIG. 3 can correspond to logical operation selection logic 213 shown in FIG. 2. The gates of the pass gates 307-1 and 307-2 can be controlled by a logical operation selection logic 313 signal, (e.g., Pass). For example, an output of the logical operation selection logic 313 can be coupled to the gates of the pass gates 307-1 and 307-2. Further, the compute component 331 can comprise a loadable shift register configured to shift data values left and right.

According to the embodiment illustrated in FIG. 3, the compute components 331 can comprise respective stages (e.g., shift cells) of a loadable shift register configured to shift data values left and right. For example, as illustrated in FIG. 3, each compute component 331 (e.g., stage) of the shift register comprises a pair of right-shift transistors 381 and 386, a pair of left-shift transistors 389 and 390, and a pair of inverters 387 and 388. The signals PHASE 1R, PHASE 2R, PHASE 1L, and PHASE 2L can be applied to respective control lines 382, 383, 391 and 392 to enable/disable feedback on the latches of the corresponding compute components 331 in association with performing logical operations and/or shifting data in accordance with embodiments described herein.

The sensing circuitry shown in FIG. 3 shows operation selection logic 313 coupled to a number of logic selection control input control lines, including ISO, TF, TT, FT, and FF. Selection of a logical operation from a plurality of logical operations is determined from the condition of logic selection control signals on the logic selection control input lines, as well as the data values present on the pair of complementary sense lines 305-1 and 305-2 when isolation transistors 350-1 and 350-2 are enabled via an ISO control signal being asserted.

According to various embodiments, the operation selection logic 313 can include four logic selection transistors: logic selection transistor 362 coupled between the gates of the swap transistors 342 and a TF signal control line, logic selection transistor 352 coupled between the gates of the pass gates 307-1 and 307-2 and a TT signal control line, logic selection transistor 354 coupled between the gates of the pass gates 307-1 and 307-2 and a FT signal control line, and logic selection transistor 364 coupled between the gates of the swap transistors 342 and a FF signal control line. Gates of logic selection transistors 362 and 352 are coupled to the true sense line through isolation transistor 350-1 (having a gate coupled to an ISO signal control line). Gates of logic selection transistors 364 and 354 are coupled to the complementary sense line through isolation transistor 350-2 (also having a gate coupled to an ISO signal control line).

Data values present on the pair of complementary sense lines 305-1 and 305-2 can be loaded into the compute component 331 via the pass gates 307-1 and 307-2. The compute component 331 can comprise a loadable shift register. When the pass gates 307-1 and 307-2 are OPEN, data values on the pair of complementary sense lines 305-1 and 305-2 are passed to the compute component 331 and thereby loaded into the loadable shift register. The data values on the pair of complementary sense lines 305-1 and 305-2 can be the data value stored in the sense amplifier 306 when the sense amplifier is fired. In this example, the logical operation selection logic signal, Pass, is high to OPEN the pass gates 307-1 and 307-2.

The ISO, TF, TT, FT, and FF control signals can operate to select a logical function to implement based on the data value ("B") in the sense amplifier 306 and the data value ("A") in the compute component 331. In particular, the ISO, TF, TT, FT, and FF control signals are configured to select the logical function to implement independent from the data value present on the pair of complementary sense lines 305-1 and 305-2 (although the result of the implemented logical operation can be dependent on the data value present on the pair of complementary sense lines 305-1 and 305-2. For example, the ISO, TF, TT, FT, and FF control signals select the logical operation to implement directly since the data value present on the pair of complementary sense lines 305-1 and 305-2 is not passed through logic to operate the gates of the pass gates 307-1 and 307-2.

Additionally, FIG. 3 shows swap transistors 342 configured to swap the orientation of the pair of complementary sense lines 305-1 and 305-2 between the sense amplifier 306 and the compute component 331. When the swap transistors 342 are OPEN, data values on the pair of complementary sense lines 305-1 and 305-2 on the sense amplifier 306 side of the swap transistors 342 are oppositely-coupled to the pair of complementary sense lines 305-1 and 305-2 on the compute component 331 side of the swap transistors 342, and thereby loaded into the loadable shift register of the compute component 331.

The logical operation selection logic 313 signal Pass can be activated (e.g., high) to OPEN the pass gates 307-1 and 307-2 (e.g., conducting) when the ISO control signal line is activated and either the TT control signal is activated (e.g., high) with data value on the true sense line is "1" or the FT control signal is activated (e.g., high) with the data value on the complement sense line is "1."

The data value on the true sense line being a "1" OPENs logic selection transistors 352 and 362. The data value on the complimentary sense line being a "1" OPENs logic selection transistors 354 and 364. If the ISO control signal or either the respective TT/FT control signal or the data value on the corresponding sense line (e.g., sense line to which the gate of the particular logic selection transistor is coupled) is not high, then the pass gates 307-1 and 307-2 will not be OPENed by a particular logic selection transistor.

The logical operation selection logic signal Pass* can be activated (e.g., high) to OPEN the swap transistors 342 (e.g., conducting) when the ISO control signal line is activated and either the TF control signal is activated (e.g., high) with data value on the true sense line is "1," or the FF control signal is activated (e.g., high) with the data value on the complement sense line is "1." If either the respective control signal or the data value on the corresponding sense line (e.g., sense line to which the gate of the particular logic selection transistor is coupled) is not high, then the swap transistors 342 will not be OPENed by a particular logic selection transistor.

The Pass* control signal is not necessarily complementary to the Pass control signal. It is possible for the Pass and Pass* control signals to both be activated or both be deactivated at the same time. However, activation of both the Pass and Pass* control signals at the same time shorts the pair of complementary sense lines together, which may be a disruptive configuration to be avoided.

The sensing circuitry illustrated in FIG. 3 is configured to select one of a plurality of logical operations to implement directly from the four logic selection control signals (e.g., logical operation selection is not dependent on the data value present on the pair of complementary sense lines). Some combinations of the logic selection control signals can cause both the pass gates 307-1 and 307-2 and swap transistors 342 to be OPEN at the same time, which shorts the pair of complementary sense lines 305-1 and 305-2 together. According to a number of embodiments of the present disclosure, the logical operations which can be implemented by the sensing circuitry illustrated in FIG. 3 can be the logical operations summarized in the logic tables shown in FIG. 4.

FIG. 4 is a logic table illustrating selectable logic operation results implemented using the circuitry shown in FIG. 3 in accordance with a number of embodiments of the present disclosure. The four logic selection control signals (e.g., TF, TT, FT, and FF), in conjunction with a particular data value present on the complementary sense lines, can be used to select one of plural logical operations to implement involving the starting data values stored in the sense amplifier 306 and compute component 331. The four control signals, in conjunction with a particular data value present on the complementary sense lines, controls the continuity of the pass gates 307-1 and 307-2 and swap transistors 342, which in turn affects the data value in the compute component 331 and/or sense amplifier 306 before/after firing. The capability to selectably control continuity of the swap transistors 342 facilitates implementing logical operations involving inverse data values (e.g., inverse operands and/or inverse result), among others.

Logic Table 4-1 illustrated in FIG. 4 shows the starting data value stored in the compute component 331 shown in column A at 444, and the starting data value stored in the sense amplifier 306 shown in column B at 445. The other 3 column headings in Logic Table 4-1 refer to the continuity of the pass gates 307-1 and 307-2, and the swap transistors 342, which can respectively be controlled to be OPEN or CLOSED depending on the state of the four logic selection control signals (e.g., TF, TT, FT, and FF), in conjunction with a particular data value present on the pair of complementary sense lines 305-1 and 305-2. The "Not Open" column corresponds to the pass gates 307-1 and 307-2 and the swap transistors 342 both being in a non-conducting condition, the "Open True" corresponds to the pass gates 307-1 and 307-2 being in a conducting condition, and the "Open Invert" corresponds to the swap transistors 342 being in a conducting condition. The configuration corresponding to the pass gates 307-1 and 307-2 and the swap transistors 342 both being in a conducting condition is not reflected in Logic Table 4-1 since this results in the sense lines being shorted together.

Via selective control of the continuity of the pass gates 307-1 and 307-2 and the swap transistors 342, each of the three columns of the upper portion of Logic Table 4-1 can be combined with each of the three columns of the lower portion of Logic Table 4-1 to provide 3.times.3=9 different result combinations, corresponding to nine different logical operations, as indicated by the various connecting paths shown at 475. The nine different selectable logical operations that can be implemented by the sensing circuitry (e.g., 150 in FIG. 1) are summarized in Logic Table 4-2 illustrated in FIG. 4, including an XOR logical operation.

The columns of Logic Table 4-2 illustrated in FIG. 4 show a heading 480 that includes the state of logic selection control signals. For example, the state of a first logic selection control signal is provided in row 476, the state of a second logic selection control signal is provided in row 477, the state of a third logic selection control signal is provided in row 478, and the state of a fourth logic selection control signal is provided in row 479. The particular logical operation corresponding to the results is summarized in row 447.

While example embodiments including various combinations and configurations of sensing circuitry, sense amplifiers, compute component, dynamic latches, isolation devices, and/or shift circuitry have been illustrated and described herein, embodiments of the present disclosure are not limited to those combinations explicitly recited herein. Other combinations and configurations of the sensing circuitry, sense amplifiers, compute component, dynamic latches, isolation devices, and/or shift circuitry disclosed herein are expressly included within the scope of this disclosure.

Although specific embodiments have been illustrated and described herein, those of ordinary skill in the art will appreciate that an arrangement calculated to achieve the same results can be substituted for the specific embodiments shown. This disclosure is intended to cover adaptations or variations of one or more embodiments of the present disclosure. It is to be understood that the above description has been made in an illustrative fashion, and not a restrictive one. Combination of the above embodiments, and other embodiments not specifically described herein will be apparent to those of skill in the art upon reviewing the above description. The scope of the one or more embodiments of the present disclosure includes other applications in which the above structures and methods are used. Therefore, the scope of one or more embodiments of the present disclosure should be determined with reference to the appended claims, along with the full range of equivalents to which such claims are entitled.

In the foregoing Detailed Description, some features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the disclosed embodiments of the present disclosure have to use more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment.

Claims

What is claimed is:

1. An apparatus, comprising: a processing in memory (PIM) capable device comprising a PIM control component including timing circuitry and timing management circuitry coupleable to a host via an interface comprising a sideband channel, wherein the PIM control component is configured to: receive at least one command selected from a group of a logical operation command and a composite operation command via the interface; perform virtual address resolution for the at least one command for PIM operations; and provide a number of bit vector operations to the PIM capable device via the sideband channel subsequent to performance of the virtual address resolution.

2. The apparatus of claim 1, wherein the interface further comprises a control bus separate from the sideband channel and over which memory commands are provided from the host to the PIM capable device.

3. The apparatus of claim 1, wherein the PIM control component is coupled to a memory management unit of the host to perform the virtual address resolution by translating virtual addresses of the host to physical addresses of the array.

4. The apparatus of claim 1, wherein at least one of the bit vector operations comprises a Boolean operation to be performed between first and second operands stored in the PIM capable device.

5. The apparatus of claim 1, wherein the PIM control component comprises a sequencer configured to receive composite operations and to send constituent bit vector operations to bit vector operation circuitry on the PIM capable device.

6. The apparatus of claim 1, wherein the host is located physically separate from the PIM capable device.

7. The apparatus of claim 1, wherein the host further comprises control logic including a reduced instructions set computer (RISC) type controller configured to generate a logical operation commands, and wherein the logical operation commands include commands that are different from double data rate (DDR) commands.

8. An apparatus, comprising: a processing in memory (PIM) control component comprising timing circuitry and timing management circuitry, wherein the PIM control component is configured to: receive at least one command selected from a group of a logical operation command and a composite operation command via an interface comprising a sideband channel to enable performance of bit vector operations, wherein a virtual address associated with the at least one command has been resolved to a physical address prior to receipt of the at least one command by the PIM control component.

9. The apparatus of claim 8, wherein the PIM control component is further configured to perform a data alignment operation on data stored in the array prior to performance of the bit vector operations.

10. The apparatus of claim 8, wherein the PIM control component resides on a controller of a memory device, and wherein the controller is further configured to control execution of dynamic random-access memory (DRAM) commands in addition to the at least one command, the DRAM commands received via a control bus separate from the sideband channel.

11. The apparatus of claim 8, further comprising a host coupled to the array and the PIM control device, wherein the host includes circuitry to perform logical to physical address resolution for the at least one command.

12. The apparatus of claim 8, wherein the bit vector operation includes at least one operation selected from the group of a shift operation and a Boolean operation.

13. The apparatus of claim 8, wherein the PIM control device is configured to receive instructions to control timing of operations for an array of memory cells to a RAS component via the sideband channel, and wherein the sideband channel is separate from a double data rate (DDR) channel used to control read and write dynamic random-access memory (DRAM) commands for the array.

14. The apparatus of claim 8, wherein the PIM control device resides on a controller of a memory device coupled to a host, and wherein the host comprises PIM control components configured to: perform scalar operations corresponding to bit vector operations performed on the memory device; and send corresponding composite operations and/or logical operations to the controller in association with performing the bit vector operations.

15. A method, comprising: providing a number of bit vector operations from a host to a PIM capable device coupled thereto via an interface comprising a sideband channel; receiving at least one command selected from a group of a logical operation command and a composite operation command via the interface; and prior to providing the number of bit vector operations to the PIM capable device, performing, using a PIM control component coupled to the PIM capable device and comprising timing circuitry and timing management circuitry, virtual address resolution for the at least one command for a number of PIM operations to which the number of bit vector operations correspond.

16. The method of claim 15, wherein the bit vector operations comprise at least one operation selected from the group of a Boolean logic operation and a data transfer operation.

17. The method of claim 15, wherein the PIM capable device comprises an array of memory cells, and wherein the method further comprises receiving, by a row address strobe (RAS) component coupled to the array, a command to perform a dynamic random-access memory (DRAM) operation.

18. The method of claim 15, further comprising receiving a command to perform a dynamic random-access memory (DRAM) operation via a double data rate (DDR) control channel separate from the sideband channel.

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