U.S. patent number 10,505,552 [Application Number 15/475,274] was granted by the patent office on 2019-12-10 for locked loop circuit with reference signal provided by un-trimmed oscillator.
This patent grant is currently assigned to STMicroelectronics International N.V.. The grantee listed for this patent is STMicroelectronics International N.V.. Invention is credited to Nitin Gupta, Nitin Jain, Anand Kumar.
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United States Patent |
10,505,552 |
Kumar , et al. |
December 10, 2019 |
Locked loop circuit with reference signal provided by un-trimmed
oscillator
Abstract
An electronic device disclosed herein includes a locked loop
circuit configured to receive a reference signal intended to have
an intended frequency, wherein the locked look circuit is intended
to generate an intended output signal having an intended frequency
equal to the intended frequency multiplied by an intended
multiplier. A frequency counter counts a number of pulses of the
reference signal during a time window so as to determine an actual
frequency of the reference signal. A control circuit determines an
actual multiplier for the locked loop circuit that, when multiplied
by the actual frequency of the reference signal, causes the locked
loop circuit to generate an actual output signal having an actual
frequency equal to the intended frequency.
Inventors: |
Kumar; Anand (Noida,
IN), Gupta; Nitin (Noida, IN), Jain;
Nitin (Uttar Pradesh, IN) |
Applicant: |
Name |
City |
State |
Country |
Type |
STMicroelectronics International N.V. |
Schiphol |
N/A |
NL |
|
|
Assignee: |
STMicroelectronics International
N.V. (Schiphol, NL)
|
Family
ID: |
62403987 |
Appl.
No.: |
15/475,274 |
Filed: |
March 31, 2017 |
Prior Publication Data
|
|
|
|
Document
Identifier |
Publication Date |
|
US 20180287617 A1 |
Oct 4, 2018 |
|
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H03L
7/087 (20130101); H03L 1/00 (20130101); H03L
7/183 (20130101); H03L 7/085 (20130101) |
Current International
Class: |
H03L
1/00 (20060101); H03L 7/087 (20060101); H03L
7/085 (20060101); H03L 7/183 (20060101) |
Field of
Search: |
;327/156-158 |
References Cited
[Referenced By]
U.S. Patent Documents
Primary Examiner: Donovan; Lincoln D
Assistant Examiner: Cheng; Diana J.
Attorney, Agent or Firm: Crowe & Dunlevy
Claims
The invention claimed is:
1. An electronic device, comprising: an RC oscillator configured to
generate a reference signal; a locked loop circuit configured to
receive the reference signal, and to generate therefrom an output
signal, the output signal having a frequency that is a multiple of
a frequency of the reference signal, wherein the multiple is set by
a division value applied by a frequency divider in a feedback path
of the locked loop circuit; wherein the locked loop circuit
comprises: a frequency detector configured to generate a comparison
signal as a function of a comparison between the reference signal
and a feedback signal; and an oscillator configured to generate the
output signal as a function of the comparison signal; wherein the
frequency divider is configured to divide the output signal by the
division value to produce the feedback signal as having the
frequency that is the multiple of the frequency of the reference
signal; a frequency counter circuit configured to measure the
frequency of the reference signal and to generate a count signal
based thereupon, wherein the frequency counter circuit is not
coupled to the feedback signal and is configured to receive the
reference signal and a comparison signal, and to measure the
frequency of the reference signal by comparing it to the comparison
signal; and a control circuit configured to adjust the division
value used by the locked loop circuit to generate the output signal
based upon the count signal.
2. The electronic device of claim 1, wherein the control circuit is
configured to adjust the division value such that the frequency of
the output signal matches a desired frequency.
3. The electronic device of claim 1, wherein the frequency of the
reference signal is not equal to a desired reference frequency; and
wherein the control circuit is configured to adjust the division
value such that the frequency of the output signal is equal to the
desired reference frequency multiplied by a desired multiplier.
4. The electronic device of claim 1, wherein the frequency counter
circuit measures the frequency of the reference signal by counting
pulses of the reference signal over a time period based upon a
desired accuracy of the frequency of the output signal.
5. The electronic device of claim 4, wherein the time period is
equal to a number of cycles of a calibration frequency equal in
number to 1 divided by a desired accuracy threshold.
6. The electronic device of claim 1, wherein the RC oscillator
generates the reference signal in an un-trimmed manner.
7. The electronic device of claim 6, wherein the RC oscillator does
not contain a digital to analog converter.
8. The electronic device of claim 1, wherein the locked loop
circuit is a phase locked loop circuit.
9. The electronic device of claim 1, wherein the locked loop
circuit is a frequency locked loop circuit.
10. The electronic device of claim 1, wherein the comparison signal
is not the feedback signal.
11. The electronic device of claim 1, wherein the locked loop
circuit is further configured to receive a feedback signal and to
generate the output signal as a function of a comparison between
the reference signal and the feedback signal; and wherein the
frequency counter circuit is configured to measure the frequency of
the reference signal by comparing it to a comparison signal.
12. The electronic device of claim 1, wherein the frequency of the
reference signal is not equal to a desired reference frequency;
wherein the multiple is not equal to a desired multiple; and
wherein the control circuit adjusts the division value such that
the frequency of the output signal is equal to the desired
reference frequency multiplied by the desired multiple.
13. The electronic device of claim 1, wherein the control circuit
receives a non-zero intended division value, and adjusts the
division value by adjusting the received non-zero intended division
value based upon the count signal.
14. A method, comprising: generating a reference signal using an RC
oscillator; receiving a feedback signal; operating a locked loop
circuit to generate an output signal from the reference signal, the
output signal having a frequency that is a multiple of a frequency
of the reference signal, wherein the multiple is set by a division
value applied by a frequency divider in a feedback path of the
locked loop circuit, wherein the locked loop circuit is operated to
generate the output signal from the reference signal as a function
of a comparison between the reference signal and the feedback
signal; measuring the frequency of the reference signal and
generating a count signal based thereupon, wherein the frequency of
the reference signal is measured by comparing it to a comparison
signal, the comparison signal being separate and distinct from the
feedback signal; and adjusting the division value used by the
locked loop circuit to generate the output signal, based upon the
count signal.
15. The method of claim 14 wherein the division value is adjusted
such that the frequency of the output signal matches a desired
frequency.
16. The method of claim 14, wherein the frequency of the reference
signal is not equal to a desired reference frequency; and wherein
the division value is adjusted such that the frequency of the
output signal is equal to the desired reference frequency
multiplied by a desired multiplier.
17. The method of claim 14, wherein the frequency of the reference
signal is measured by counting pulses of the reference signal over
a time period based upon a desired accuracy threshold of the
frequency of the output signal.
18. The method of claim 17, wherein the time period is equal to a
number of cycles of a calibration frequency equal in number to 1
divided by the desired accuracy threshold.
19. The method of claim 14, wherein the frequency of the reference
signal is not equal to a desired reference frequency; wherein the
multiple is not equal to a desired multiple; and wherein the
division value is adjusted such that the frequency of the output
signal is equal to the desired reference frequency multiplied by
the desired multiple.
20. The method of claim 14, further comprising receiving a non-zero
intended division value; and wherein the division value is adjusted
by adjusting the received non-zero intended division value.
Description
TECHNICAL FIELD
This disclosure is directed to the field of locked loop circuits,
and, in particular, to locked loop circuits capable of
self-adjusting for process variations in oscillators providing
reference frequencies used by those locked loop circuits.
BACKGROUND
A locked loop circuit operates to produce an output signal having a
frequency that is a multiple, or fraction, of a reference
frequency. In some cases, the reference frequency may be provided
by a crystal oscillator. While a crystal oscillator accurately
generate the reference frequency, it may be undesirably expensive,
and may consume an undesirable amount of area.
Therefore, an RC oscillator may be used to generate the reference
frequency for a locked loop circuit. However, due to process
variations in fabrication of resistors and capacitors, an RC
oscillator without a feedback mechanism may inaccurately generate
such the reference frequency, which would result in the locked loop
circuit employing that RC oscillator not actually generating its
output signal as having a desired frequency.
Consequently, an RC oscillator used with a locked loop circuit will
conventionally employ a feedback loop, calibration, or compensation
circuit and be adjusted based thereupon. A digital to analog
converter (DAC) is employed to generate control signals for
components within the RC oscillator. By adjusting the operation of
these components, the frequency of the signal generated by the RC
oscillator may be adjusted.
Unfortunately, to obtain a high degree of accuracy in feedback
signal generation with an RC oscillator, the DAC utilizes a large
number of bits as input, resulting in the DAC being undesirably
large and consuming an undesirable amount of area. In addition, a
large DAC can consume an undesirable amount of power.
Therefore, further developments in the area of locked loop circuits
is needed to address these issues.
SUMMARY
Disclosed herein is an electronic device including a locked loop
circuit configured to receive a reference signal, and to generate
therefrom an output signal, with the output signal having a
frequency that is a fractional or integer multiple of a frequency
of the reference signal. A frequency counter circuit is configured
to measure the frequency of the reference signal and to generate a
count signal based thereupon. A control circuit is configured to
adjust a multiplier used by the locked loop circuit to generate the
output signal based upon the count signal.
The control circuit may be configured to adjust the multiplier such
that the frequency of the output signal matches a desired
frequency. The frequency of the reference signal may not be equal
to a desired reference frequency, and the control circuit may be
configured to adjust the multiplier such that the frequency of the
output signal is equal to the desired reference frequency
multiplied by a desired multiplier.
The frequency counter circuit may measure the frequency of the
reference signal by counting pulses of the reference signal over a
time period based upon a desired accuracy of the frequency of the
output signal. The time period may be equal to a number of cycles
of a calibration frequency equal in number to 1 divided by a
desired accuracy threshold.
An oscillator may generate the reference signal in an un-trimmed
manner. The oscillator does not contain a digital to analog
converter and is not a crystal oscillator.
The locked loop circuit may be a phase locked loop circuit or a
frequency locked loop circuit or any other frequency multiplier
circuit.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of an electronic device including a
locked loop circuit in accordance with this disclosure.
FIG. 2 is a schematic block diagram of an electronic device
including a digital phase locked loop circuit in accordance with
this disclosure.
FIG. 3 is a schematic block diagram of an electronic device
including an analog phase locked loop circuit in accordance with
this disclosure.
FIG. 4 is a schematic block diagram of an electronic device
including an analog frequency locked loop circuit in accordance
with this disclosure.
DETAILED DESCRIPTION
One or more embodiments of the present disclosure will be described
below. These described embodiments are only examples of the
presently disclosed techniques. Additionally, in an effort to
provide a concise description, some features of an actual
implementation may not be described in the specification. When
introducing elements of various embodiments of the present
disclosure, the articles "a," "an," and "the" are intended to mean
that there are one or more of the elements. The terms "comprising,"
"including," and "having" are intended to be inclusive and mean
that there may be additional elements other than the listed
elements.
With initial reference to FIG. 1, an electronic device 50 is now
described. This electronic device 50 may be, or may be incorporated
within, a mobile electronic device such as a smartphone, tablet,
smartwatch, or wearable. In some cases, the electronic device 50
may form part of a single integrated circuit chip, or may form part
of a single package or single module.
The electronic device 50 includes a locked loop 58, which operates
to generate an output signal Fout having a frequency f.sub.out that
is a fractional or integer multiple of a frequency f.sub.ref of a
reference signal Frcosi. A RC oscillator 52 provides the reference
signal Frcosi to the locked loop 58. As will be explained in
greater detail below, the frequency of the reference signal Frcosi
may be inaccurate in that the frequency f.sub.actual Frcosi may not
be the frequency f.sub.intended that Frcosi is intended to have. A
frequency counter 54 measures the actual frequency f.sub.actual of
the reference signal Frcosi in comparison to a comparison frequency
f.sub.calibrate of a calibration signal Fcal, and generates an
output Count to control circuitry 56. The control circuitry 56
receives a desired fractional or integer multiplier Mult as an
input, and adjusts the multiplier Mult_LL actually used by the
locked loop 58, based upon Count, so that the frequency f.sub.out
of the output signal Fout is actually equal to
f.sub.intended*Mult.
Stated another way, the reference signal Frcosi is intended to have
the frequency f.sub.intended, but actually has the frequency
f.sub.actual. The desired multiplier for f.sub.intended is Mult.
The desired frequency f.sub.out for the output signal Fout is
therefore f.sub.intended*Mult. However, since Frcosi actually has
the frequency f.sub.actual the frequency f.sub.out of the output
signal Fout would be f.sub.actual*Mult, which is not equal to
f.sub.intended*Mult. Therefore, the control circuitry 56 adjusts
the multiplier Mult_LL used by the locked loop 58, such that the
output signal Fout has a frequency f.sub.out of
f.sub.actual*Mult_LL, which is equal to f.sub.intended*Mult.
The RC oscillator 52 generates the reference signal Frcosi in an
"un-trimmed" fashion. As will be understood by those of skill in
the art, "un-trimmed" means that output of the RC oscillator 52 is
not adjusted for process variations. As will also be understood by
those of skill in the art, a RC oscillator, such as the RC
oscillator 52, requires some form of feedback, calibration, or
compensation in order to precisely generate a signal having a
desired frequency. Without that feedback, calibration, or
compensation the frequency of the generated signal may be too high
or too low, potentially by a large amount (i.e. 20%). Such
mechanisms typically involve a digital to analog converter used to
precisely control current sources within the RC oscillator to
compensate for the fact that the actual resistance of the resistors
and the actual capacitance of the capacitors is not the intended
resistance and the intended capacitance and thereby ensure that the
generated signal has the desired frequency.
Is therefore made explicitly clear here that the RC oscillator 52
uses no feedback, calibration, or compensation mechanisms, uses no
digital to analog converter, and generates its output signal Frcosi
having an actual frequency f.sub.actual that is not equal to the
desired frequency f.sub.intended, and is instead higher or lower
than f.sub.intended. There are no mechanisms to correct Frcosi
itself, and Frcosi remains uncorrected. Thus, it is also made
explicitly clear that the locked loop 58 may not receive a
reference signal Frcosi having the intended frequency
f.sub.intended, but instead may receive the reference signal Frcosi
having the incorrect and undesired frequency f.sub.actual as the RC
oscillator 52 is free running and un-trimmed.
The frequency counter 54 determines the actual frequency
f.sub.actual of the reference signal Frcosi by counting the number
of pulses in Frcosi over a time window measured in clock cycles of
Fcal and related to a desired accuracy of the frequency. The
desired accuracy can be represented as a percentage, and in that
case, the time window has a duration of 100/DesiredAccuracy clock
cycles, referred to as Count_Ref. For example, if the desired
accuracy is 0.1%, then the window has a duration of 100/0.1=1000
cycles at a frequency of Fintended. Therefore, if the frequency
counter 54 counts 800 cycles (where the desired accuracy is 0.1%),
it is known that f.sub.actual is 20% less than f.sub.desired,
within an accuracy of 0.1%.
The output Count generated by the frequency counter 54 is thus a
digital representation of:
Count=Count_Ref*f.sub.actual/f.sub.intended.
The control circuitry 56 receives Count, and then calculates the
multiple Mult_LL to be used by the locked loop 58 as:
MMult_LL=(Count_Ref/Count)*Mult=f.sub.intended*Mult/f.sub.actual.
Therefore, the frequency of Fout will be
f.sub.out=f.sub.actual*Mult_LL=f.sub.intended*Mult. Thus, the
electronic device 50 has realized an accurate locked loop circuit
58 that receives its reference frequency from an un-trimmed RC
oscillator 52. By using the un-trimmed RC oscillator 52, the amount
of surface area consumed by the RC oscillator 52 is greatly
reduced, as the digital to analog converters utilized in trimmed RC
oscillators can consume as much, or more than, 70% of the available
surface area. In addition, power consumption is reduced due to the
lack of trimming.
In addition, since there is no surface area penalty for increasing
the accuracy of the output signal Fout from the locked loop 58, the
frequency of the reference signal Frcosi can be greatly reduced and
Mult_LL can be increased accordingly to produce the desired output
frequency f.sub.out. This helps to further reduce power
consumption. Moreover, the effect of temperature on the reference
signal Frcosi is reduced by the reduction in frequency, as is the
effect of transient switching.
It should be understood that the locked loop 58 which may be a
frequency locked loop or a phase locked loop, and may be
constructed from entirely analog components or a combination of
analog or digital components. In the case where the locked loop 58
is a frequency locked loop, the locked loop 58 operates to generate
an output signal Fout that has a frequency f.sub.out that is a
desired multiple Mult of a desired frequency f.sub.intended of a
reference signal Frcosi, and in the case where the locked loop 58
is a phase locked loop, in addition to the output signal Fout
having a frequency f.sub.out that is the desired multiple Mult of
the desired frequency f.sub.intended of the reference signal
Frcosi, the phase of the output signal Fout is locked to the phase
of the reference signal Frcosi.
An embodiment in which the locked loop 58 is a digital phase locked
loop is now described with reference to FIG. 2. Operation of the RC
oscillator 52, frequency counter 54, and control circuitry 56
remains the same as above and will not be repeated for brevity.
Here, the locked loop 58 includes a phase frequency detector (PFD)
22. The PFD 22 receives as input the reference signal Frcosi and a
feedback signal Fmult. The PFD 22 determines a difference in phase
between the reference frequency signal Frcosi and the feedback
signal Fmult and outputs a digital signal Ddif indicative of that
measured difference. The digital signal Ddif is filtered by digital
filter 26, such as a low pass digital filter, which generates a
control signal Dcont. A digital-to-analog converter (DAC) 28
converts the digital control signal Dcont to an analog control
signal Acont. A control input of an oscillator circuit 30, such as
a voltage controlled oscillator or current controlled oscillator,
receives the analog control signal Acont and generates an output
clock signal Fout having a frequency f.sub.out that is dependent on
the magnitude of the analog control signal Acont. A divider circuit
(/N) 32 divides the output clock signal Fout by N (equal to
Mult_LL) to generate a feedback signal Fmult.
An embodiment in which the locked loop 58' is an analog phase
locked loop is now described with reference to FIG. 3. Operation of
the RC oscillator 52, frequency counter 54, and control circuitry
56 remains the same as above and will not be repeated for brevity.
Here, the locked loop 58' includes a phase frequency detector (PFD)
22. The PFD 22 receives as input the reference signal Frcosi and a
feedback signal Fmult. The PFD 22 determines a difference in phase
between the reference frequency signal Frcosi and the feedback
signal Fmult and outputs an analog signal Adif indicative of that
measured difference. The analog signal Adif is filtered by filter
26', such as a low pass analog filter, which generates a control
signal Acont. A control input of an oscillator circuit 30, such as
a voltage controlled oscillator or current controlled oscillator,
receives the analog control signal Acont and generates an output
clock signal Fout having a frequency f.sub.out that is dependent on
the magnitude of the analog control signal Acont. A divider circuit
(/N) 32 divides the output clock signal Fosc by N (equal to
Mult_LL) to generate a feedback signal Fmult.
An embodiment in which the locked loop 58'' is an analog frequency
locked loop is now described with reference to FIG. 3. Operation of
the RC oscillator 52, frequency counter 54, and control circuitry
56 remains the same as above and will not be repeated for brevity.
Here, the locked loop 58'' includes a frequency comparator 22. The
frequency comparator 22 receives as input the reference signal
Frcosi and the feedback signal Fmult. The frequency comparator 22
determines a difference in frequency between the reference
frequency signal Frcosi and the feedback signal Fmult and outputs
an analog signal Fdif indicative of that measured difference. The
analog signal Fdif is filtered by filter 26'', such as a low pass
analog filter, which generates a control signal Cont. A control
input of an oscillator circuit 30, such as a voltage controlled
oscillator or current controlled oscillator, receives the control
signal Cont and generates an output clock signal Fout having a
frequency f.sub.out that is dependent on the magnitude of the
control signal Cont. A divider circuit (/N) 32 divides the output
clock signal Fout by N (equal to Mult_LL) to generate a feedback
signal Fmult.
While the disclosure has been described with respect to a limited
number of embodiments, those skilled in the art, having benefit of
this disclosure, will appreciate that other embodiments can be
envisioned that do not depart from the scope of the disclosure as
disclosed herein. Accordingly, the scope of the disclosure shall be
limited only by the attached claims.
* * * * *