U.S. patent number 10,355,110 [Application Number 15/640,920] was granted by the patent office on 2019-07-16 for finfet and method of forming same.
This patent grant is currently assigned to Taiwan Semiconductor Manufacturing Company, Ltd.. The grantee listed for this patent is Taiwan Semiconductor Manufacturing Company, Ltd.. Invention is credited to Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng, Po-Chi Wu.
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United States Patent |
10,355,110 |
Chang , et al. |
July 16, 2019 |
FinFET and method of forming same
Abstract
A method includes forming a first active fin structure and a
second active fin structure on a substrate. A dummy fin structure
is formed on the substrate, the dummy fin structure being
interposed between the first active fin structure and the second
active fin structure. The dummy fin structure is removed to expose
a first portion of the substrate, the first portion of the
substrate being disposed directly below the dummy fin structure. A
plurality of protruding features is formed on the first portion of
the substrate. A shallow trench isolation (STI) region is formed
over the first portion of the substrate, the STI region covering
the plurality of protruding features, at least a portion of the
first active fin structure and at least a portion of the second
active fin structure extending above a topmost surface of the STI
region.
Inventors: |
Chang; Che-Cheng (New Taipei,
TW), Wu; Po-Chi (Zhubei, TW), Lin;
Chih-Han (Hsinchu, TW), Tseng; Horng-Huei
(Hsinchu, TW) |
Applicant: |
Name |
City |
State |
Country |
Type |
Taiwan Semiconductor Manufacturing Company, Ltd. |
Hsinchu |
N/A |
TW |
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Assignee: |
Taiwan Semiconductor Manufacturing
Company, Ltd. (Hsinchu, TW)
|
Family
ID: |
61069478 |
Appl.
No.: |
15/640,920 |
Filed: |
July 3, 2017 |
Prior Publication Data
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Document
Identifier |
Publication Date |
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US 20180040713 A1 |
Feb 8, 2018 |
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Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
Issue Date |
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62405735 |
Oct 7, 2016 |
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62370099 |
Aug 2, 2016 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L
29/0649 (20130101); H01L 29/6681 (20130101); H01L
21/823431 (20130101); H01L 29/7848 (20130101); H01L
21/823481 (20130101); H01L 27/0886 (20130101) |
Current International
Class: |
H01L
29/66 (20060101); H01L 29/06 (20060101); H01L
29/78 (20060101); H01L 27/088 (20060101); H01L
21/8234 (20060101) |
References Cited
[Referenced By]
U.S. Patent Documents
Other References
Jovanovi et. al., "Sub-100 nm silicon-nitride hard mask for high
aspect-ratio silicon fins", 2007. cited by examiner.
|
Primary Examiner: Parker; Allen L
Assistant Examiner: Ausar-El; Charles N
Attorney, Agent or Firm: Slater Matsil, LLP
Parent Case Text
PRIORITY CLAIM AND CROSS-REFERENCE
This application claims the benefit of U.S. Provisional Application
Ser. No. 62/370,099, filed on Aug. 2, 2016, entitled "Fin Structure
and Method of Forming Same," and U.S. Provisional Application Ser.
No. 62/405,735, filed on Oct. 7, 2016, entitled "FinFET and Method
of Forming Same," which applications are hereby incorporated herein
by reference in their entireties.
Claims
What is claimed is:
1. A method comprising: forming a first active fin structure and a
second active fin structure on a substrate, the first active fin
structure and the second active fin structure comprise a same
number of active fins; forming a dummy fin structure on the
substrate, the dummy fin structure being interposed between the
first active fin structure and the second active fin structure;
after forming the first active fin structure, the second active fin
structure and the dummy fin structure, completely removing the
dummy fin structure to expose a first portion of the substrate, the
first portion of the substrate being disposed directly below the
dummy fin structure; after completely removing the dummy fin
structure, forming a plurality of protruding features on the first
portion of the substrate, a number of the plurality of protruding
features being less than a number of active fins in the first
active fin structure, the number of the plurality of protruding
features being less than a number of dummy fins in the dummy fin
structure before completely removing the dummy fin structure; and
forming a shallow trench isolation (STI) region over the first
portion of the substrate, the STI region covering the plurality of
protruding features, at least a portion of the first active fin
structure and at least a portion of the second active fin structure
extending above a topmost surface of the STI region.
2. The method of claim 1, wherein removing the dummy fin structure
comprises: protecting the first active fin structure and the second
active fin structure; and etching the dummy fin structure for a
first time interval.
3. The method of claim 2, wherein forming the plurality of
protruding features comprises etching the first portion of the
substrate for a second time interval.
4. The method of claim 3, wherein a ratio of the second time
interval over the first time interval is between 0.1 and about
1.5.
5. The method of claim 1, wherein a height of a first protruding
feature of the plurality of protruding features and a height of a
second protruding feature of the plurality of protruding features
are substantially equal.
6. The method of claim 1, wherein a height of a first protruding
feature of the plurality of protruding features is different from a
height of a second protruding feature of the plurality of
protruding features.
7. A method comprising: forming a first active base and a second
active base on a substrate; forming a dummy base on the substrate,
the dummy base being interposed between the first active base and
the second active base; forming a plurality of first active fins on
the first active base; forming a plurality of second active fins on
the second active base; forming a plurality of dummy fins on the
dummy base; performing a first etching process on the plurality of
dummy fins and the dummy base to completely remove the plurality of
dummy fins and the dummy base and form a recess in the substrate;
after performing the first etching process, performing a second
etching process on a bottom of the recess to form a plurality of
protruding features on the bottom of the recess, a number of the
plurality of protruding features after performing the second
etching process being less than a number of the plurality of dummy
fins before performing the first etching process; and forming a
shallow trench isolation (STI) region in the recess, a topmost
surface of the STI region being below topmost surfaces of the
plurality of first active fins and topmost surfaces of the
plurality of second active fins.
8. The method of claim 7, further comprising: before performing the
first etching process, forming a mask layer over the plurality of
first active fins, the plurality of second active fins and the
plurality of dummy fins; and patterning the mask layer to expose
the plurality of dummy fins.
9. The method of claim 7, wherein the first etching process is
performed for a first time interval, wherein the second etching
process is performed for a second time interval, and wherein a
ratio of the second time interval over the first time interval is
between 0.1 and about 1.5.
10. The method of claim 7, wherein a height of a first protruding
feature of the plurality of protruding features and a height of a
second protruding feature of the plurality of protruding features
are substantially equal.
11. The method of claim 7, wherein a height of a first protruding
feature of the plurality of protruding features is different from a
height of a second protruding feature of the plurality of
protruding features.
12. The method of claim 7, wherein the first etching process and
the second etching process are performed with a same etchant.
13. A method comprising: patterning a substrate to form an active
fin structure and a dummy fin structure, the active fin structure
comprising an active base and a plurality of active fins over the
active base, the dummy fin structure comprising a dummy base and a
plurality of dummy fins over the dummy base, a number of the
plurality of active fins being equal to a number of the plurality
of dummy fins; after forming the active fin structure and the dummy
fin structure, performing a first etching process to completely
remove the dummy fin structure and to expose a region of the
substrate directly below the dummy fin structure; after performing
the first etching process, performing a second etching process on
the region of the substrate to form a plurality of protruding
features on an exposed side of the region of the substrate, a
number of the plurality of protruding features after performing the
second etching process being less than the number of the plurality
of dummy fins before performing the first etching process; and
depositing a dielectric layer over the active fin structure and the
plurality of protruding features.
14. The method of claim 13, wherein the first etching process is
different from the second etching process.
15. The method of claim 13, wherein the first etching process and
the second etching process are performed using different mixtures
of process gases.
16. The method of claim 13, further comprising recessing the
dielectric layer to expose sidewalls of the plurality of active
fins.
17. The method of claim 16, wherein a topmost surface of the
dielectric layer is level with a topmost surface of the active base
after recessing the dielectric layer.
18. The method of claim 16, wherein a topmost surface of the
dielectric layer is above a topmost surface of the active base
after recessing the dielectric layer.
19. The method of claim 13, wherein the first etching process is
performed using a first mixture of process gases including
CF.sub.4, SF.sub.6, NF.sub.3, N.sub.2, Cl.sub.2, or a combination
thereof.
20. The method of claim 19, wherein the second etching process is
performed using a second mixture of process gases including
O.sub.2, HBr, H.sub.2, N.sub.2, or a combination thereof.
Description
BACKGROUND
Semiconductor devices are used in a variety of electronic
applications, such as personal computers, cell phones, digital
cameras, and other electronic equipment, as examples. Semiconductor
devices are typically fabricated by sequentially depositing
insulating or dielectric layers, conductive layers, and
semiconductive layers of material over a semiconductor substrate,
and patterning the various material layers using lithography to
form circuit components and elements thereon.
A transistor is an element that is used often in semiconductor
devices. There may be a large number of transistors (e.g. hundreds
of, thousands of, or millions of transistors) on a single
integrated circuit (IC), for example. A common type of transistor
used in semiconductor device fabrication is a metal oxide
semiconductor field effect transistor (MOSFET), as an example. A
planar transistor (e.g. planar MOSFET) typically includes a gate
dielectric disposed over a channel region in a substrate, and a
gate electrode formed over the gate dielectric. A source region and
a drain region of the transistor are formed on either side of the
channel region.
Multiple gate field-effect transistors (MuGFETs) are a recent
development in semiconductor technology. One type of MuGFET is
referred to as a fin field-effect transistor (FinFET), which is a
transistor structure that includes a fin-shaped semiconductor
material that is raised vertically out of the semiconductor surface
of an integrated circuit.
BRIEF DESCRIPTION OF THE DRAWINGS
Aspects of the present disclosure are best understood from the
following detailed description when read with the accompanying
figures. It is noted that, in accordance with the standard practice
in the industry, various features are not drawn to scale. In fact,
the dimensions of the various features may be arbitrarily increased
or reduced for clarity of discussion.
FIGS. 1A-11B illustrate top and cross-sectional views of various
intermediate stages of fabrication of a fin structure in accordance
with some embodiments.
FIGS. 12A-12E illustrate cross-sectional views of fin structures in
accordance with some embodiments.
FIGS. 13A-13C illustrate cross-sectional views of fin structures in
accordance with some embodiments.
FIGS. 14-18C illustrate cross-sectional views of various
intermediate stages of fabrication of a semiconductor device in
accordance with some embodiments.
FIGS. 19A, 19B, and 19C illustrate cross-sectional views of a
semiconductor device in accordance with some embodiments.
FIG. 20 is a flow diagram illustrating a method of forming a
semiconductor device in accordance with some embodiments.
DETAILED DESCRIPTION
The following disclosure provides many different embodiments, or
examples, for implementing different features of the invention.
Specific examples of components and arrangements are described
below to simplify the present disclosure. These are, of course,
merely examples and are not intended to be limiting. For example,
the formation of a first feature over or on a second feature in the
description that follows may include embodiments in which the first
and second features are formed in direct contact, and may also
include embodiments in which additional features may be formed
between the first and second features, such that the first and
second features may not be in direct contact. In addition, the
present disclosure may repeat reference numerals and/or letters in
the various examples. This repetition is for the purpose of
simplicity and clarity and does not in itself dictate a
relationship between the various embodiments and/or configurations
discussed.
Further, spatially relative terms, such as "beneath," "below,"
"lower," "above," "upper" and the like, may be used herein for ease
of description to describe one element or feature's relationship to
another element(s) or feature(s) as illustrated in the figures. The
spatially relative terms are intended to encompass different
orientations of the device in use or operation in addition to the
orientation depicted in the figures. The apparatus may be otherwise
oriented (rotated 90 degrees or at other orientations) and the
spatially relative descriptors used herein may likewise be
interpreted accordingly.
Embodiments will be described with respect to a specific context,
namely, a fin structure and a method of forming the same. In some
embodiments, a fin structure may be used to form a fin field-effect
transistor (FinFET). Various embodiments described herein allow for
enlarging a fin etch process window, better critical dimension (CD)
loading for strained source and drain (SSD) epitaxial (EPI)
process, CVD stress effect (bending) improvement, better wafer
acceptance test (WAT) and reliability performance, and better
circuit probe (CP) yield performance.
FIGS. 1A-11B illustrate top and cross-sectional views of various
intermediate stages of fabrication of a fin structure in accordance
with some embodiments, where an "A" figure represents a top view
and a "B" figure represents a cross-sectional view along a B-B line
of the respective "A" figure. In some embodiments, further process
steps may be performed on the fin structure to form a FinFET as
described below with reference to FIGS. 14-18C. FIGS. 1A and 1B
illustrate top and cross-sectional views of a substrate 101, which
may be a part of a wafer 100. The substrate 101 may be a
semiconductor substrate, such as a bulk semiconductor, a
semiconductor-on-insulator (SOI) substrate, or the like, which may
be doped (e.g., with a p-type or an n-type dopant) or undoped.
Generally, an SOI substrate includes a layer of a semiconductor
material formed on an insulator layer. The insulator layer may be,
for example, a buried oxide (BOX) layer, a silicon oxide layer, or
the like. The insulator layer is provided on a substrate, typically
a silicon or glass substrate. Other substrates, such as a
multi-layered or gradient substrate may also be used. In some
embodiments, the semiconductor material of the substrate 101 may
include silicon; germanium; a compound semiconductor including
silicon carbide, gallium arsenic, gallium phosphide, indium
phosphide, indium arsenide, and/or indium antimonide; an alloy
semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP,
and/or GaInAsP; or combinations thereof.
The substrate 101 may include integrated circuit devices (not
shown). As one of ordinary skill in the art will recognize, a wide
variety of integrated circuit devices such as transistors, diodes,
capacitors, resistors, the like, or combinations thereof may be
formed in and/or on the substrate 101 to generate the structural
and functional requirements of the design for the resulting FinFET.
The integrated circuit devices may be formed using any suitable
methods.
In some embodiments, a first mask layer 103 is formed over the
substrate 101, a second mask layer 105 is formed over the first
mask layer 103, and a third mask layer 107 is formed over the
second mask layer 105. The first mask layer 103 may be a hard mask
comprising silicon nitride, silicon oxynitride, silicon carbide,
silicon carbonitride, the like, or a combination thereof. In some
embodiments where the first mask layer 103 comprises silicon
nitride, the first mask layer 103 may be formed using thermal
nitridation, plasma anodic nitridation, Low-Pressure Chemical Vapor
Deposition (LPCVD), Plasma Enhanced Chemical Vapor Deposition
(PECVD), the like, or a combination thereof. In some embodiments,
the first mask layer 103 may have a thickness between about 10
.ANG. and about 1000 .ANG.. It is appreciated that the values
recited throughout the description are examples, and different
values may also be adopted without changing the principle of the
present disclosure.
The second mask layer 105 may be a hard mask comprising an oxide,
such as silicon oxide, or the like. The second mask layer 105 may
also be referred to as a pad oxide. In some embodiments, the second
mask layer 105 may be formed using Atomic Layer Deposition (ALD),
Chemical Vapor Deposition (CVD), thermal oxidation, the like, or a
combination thereof. In some embodiments, the second mask layer 105
may have a thickness between about 20 .ANG. and about 500 .ANG..
The third mask layer 107 may be formed using similar materials and
methods as the first mask layer 103 and the description is not
repeated herein. In some embodiments, the third mask layer 107 may
have a thickness between about 100 .ANG. and about 2000 .ANG.. A
stack of the first mask layer 103, the second mask layer 105, and
the third mask layer 107 may also be referred to as a mask stack
109, or a hard mask stack 109.
Referring further to FIGS. 1A and 1B, the third mask layer 107 of
the mask stack 109 is patterned to form a plurality of openings 111
in the third mask layer 107. In some embodiments, the third mask
layer 107 may be patterned using suitable photolithography and etch
processes. In other embodiments, the patterned third mask layer 107
may be formed using a multiple-patterning process, such as a
self-aligned double patterning (SADP) process, a self-aligned
quadruple patterning (SAQP) process, or the like, that allows for
forming features having a reduced critical dimension (CD) and
pitch. In such embodiments, one or more additional mask layers (not
shown), one or more mandrel layers (not shown), and one or more
spacer layers (not shown) may be formed over the mask stack 109.
For example, a mandrel layer (not shown) is formed and patterned
over the second mask layer 105. The patterned third mask layer 107
is formed on the sidewalls of the patterned mandrel layer.
Subsequently, the patterned mandrel layer is removed, leaving
behind the patterned third mask layer 107. In the illustrated
embodiment, unremoved features 107A of the patterned third mask
layer 107 have a uniform width and pitch. In other embodiments, the
features 107A of the patterned third mask layer 107 may have a
non-uniform width and/or a non-uniform pitch.
In some embodiments, a patterned mask layer 113 having openings 115
is formed over the mask stack 109. The patterned mask layer 113 may
comprise a photo-patternable material, such as a photoresist
material, and may be formed using a spin-on coating, or the like.
Alternatively, the patterned mask layer 113 may comprise a
non-photo-patternable material. In yet other embodiments, the
patterned mask layer 113 may comprise a multi-layer mask formed of
layers of photo-patternable and non-photo-patternable materials. In
some embodiments where the patterned mask layer 113 comprises a
photoresist material, the photoresist material is irradiated
(exposed) and developed to remove portions of the photoresist
material and form the openings 115. In the illustrated embodiment,
each of the openings 115 exposes two features 107A of the patterned
third mask layer 107. In other embodiments, each of the openings
115 may expose less than two or more than two features 107A of the
patterned third mask layer 107.
Referring to FIGS. 2A and 2B, the exposed features 107A of the
third mask layer 107 are removed using a suitable etching process.
In some embodiments where the third mask layer 107 comprises
silicon nitride, the exposed features 107A of the third mask layer
107 are selectively removed in a wet process using hot phosphoric
acid (H.sub.3PO.sub.4) as an etchant. Subsequently, the patterned
mask layer 113 (see FIGS. 1A and 1B) is removed using a suitable
removal process. In some embodiments where the patterned mask layer
113 is formed of a photoresist material, the patterned mask layer
113 may be removed using, for example, an ashing process followed
by a wet clean process. In some embodiments, after removing the
patterned mask layer 113, a capping layer (not shown) is
conformally formed over the second mask layer 105 and the third
mask layer 107. The capping layer may comprise silicon nitride and
may have a thickness between about 100 .ANG. and about 1000
.ANG..
Referring further to FIGS. 2A and 2B, after removing the exposed
features 107A of the patterned third mask layer 107, the resulting
patterned third mask layer 107 comprises the original openings 111
and new openings 201 formed as a result of removing the exposed
features 107A of the patterned third mask layer 107. In some
embodiments, a width W.sub.2 of the openings 201 is greater than a
width W.sub.1 of the openings 111. For example, in some embodiments
where each of the openings 201 are formed by removing two features
107A of the patterned third mask layer 107, the width W.sub.2 of
the openings 201 approximately equals to a sum of three times the
width W.sub.1 of the openings 111 and two times a width W.sub.3 of
the features 107A of the patterned third mask layer 107. The width
W.sub.1 of the openings 111 may be between about 10 .ANG. and about
200 .ANG., and the width W.sub.2 of the openings 201 may be between
about 50 .ANG. and about 1000 .ANG., and the width W.sub.3 of the
features 107A of the patterned third mask layer 107 may be between
about 100 .ANG. and about 1000 .ANG..
Referring to FIGS. 3A and 3B, the first mask layer 103 and the
second mask layer 105 of the mask stack 109 are patterned to form
openings 301A and 301B in the mask stack 109 while using the third
mask layer 107 (see FIGS. 2A and 2B) as an etch mask. In some
embodiments, the first mask layer 103 and the second mask layer 105
of the mask stack 109 are patterned using one or more suitable etch
processes. During the patterning process, the third mask layer 107
may be consumed. The openings 301A and 301B expose portions of the
substrate 101. The patterns of the openings 301A and 301B, and the
pattern of the unremoved portions 303 of the mask stack 109 as
illustrated in FIGS. 3A and 3B are provided for illustration only.
In other embodiments, the patterns of the openings 301A and 301B,
and the pattern of the unremoved portions 303 of the mask stack 109
may be altered according to design requirements of the resulting
FinFET. The openings 301A correspond to the openings 111 (see FIGS.
2A and 2B) and may have a width approximately equal to the width
W.sub.1. The openings 301B correspond to the openings 201 (see
FIGS. 2A and 2B) and may have a width approximately equal to the
width W.sub.2.
Referring to FIGS. 4A and 4B, the substrate 101 is patterned to
form openings 401A and 401B in the substrate 101. The openings 401A
correspond to respective openings 301A in the mask stack 109, and
the openings 401B correspond to respective openings 301B in the
mask stack 109 (see FIGS. 3A and 3B). The openings 401A may have a
similar pattern as the openings 301A as viewed from top, and the
openings 401B may have a similar pattern as the openings 301B as
viewed from top. In some embodiments, a width of the openings 401B
may be greater than a width of the openings 401A. A depth D.sub.1
of the openings 401A and 401B may be between about 50 .ANG. and
about 500 .ANG.. Strips of a semiconductor material of the
substrate 101 interposed between adjacent ones of the openings 401A
and 401B form fins 403A, 403B and 403C. In some embodiments,
adjacent fins 403A are separated by respective openings 401A,
adjacent fins 403B are separated by respective openings 401A, and
adjacent fins 403C are separated by respective openings 401A.
Furthermore, the group of fins 403A is separated from the group of
fins 403B by a respective opening 401B, and the group of fins 403B
is separated from the group of fins 403C by a respective opening
401B. In some embodiments, the substrate 101 may be patterned by a
suitable etch process using the unremoved portions 303 of the mask
stack 109 as an etch mask. The suitable etch process may include an
anisotropic dry etch process, or the like. In some embodiments
where the substrate 101 is formed of silicon, the substrate 101 is
patterned by a reactive ion etch (RIE) process with etch process
gases including N.sub.2, CH.sub.2F.sub.2, CF.sub.4, CHF.sub.3,
CH.sub.3F, HBr, NF.sub.3, Ar, He, Cl.sub.2, CH.sub.3F, SiCl.sub.4,
the like, or a combination thereof. The RIE process may be
performed at a pressure between about 1 mTorr and about 500 mTorr,
a temperature between about 20.degree. C. and 100.degree. C., and a
radio frequency (RF) power between about 50 W and about 1000 W.
Referring to FIGS. 5A and 5B, a mask layer 501 is formed over the
substrate 101 and the fins 403A, 403B and 403C. In some
embodiments, the mask layer 501 may be formed using similar
materials and methods as the mask layer 113, described above with
reference to FIGS. 1A and 1B, and the description is not repeated
herein for the sake of brevity. The mask layer 501 is patterned to
form openings 503 in the mask layer 501. In some embodiments, the
mask layer 501 may be patterned using similar methods as the mask
layer 113, described above with reference to FIGS. 1A and 1B, and
the description is not repeated herein for the sake of brevity. The
openings 503 expose portions of bottoms of the openings 401B. In
some embodiments, a width of the openings 503 is less than the
width of the openings 401B. In some embodiments, the openings 503
may have elongated portions with lengthwise directions parallel to
each other as viewed from top. Furthermore, the lengthwise
directions of the openings 503 may be parallel to the lengthwise
directions of the openings 111 and 201, and the openings 401A and
401B (see FIGS. 2A-4B).
Referring to FIGS. 6A and 6B, the substrate 101 is patterned to
form openings 601 in the substrate 101. The openings 601 correspond
to respective openings 503 in the mask layer 501 (see FIGS. 5A and
5B). The openings 601 may have a similar pattern as the openings
503 as viewed from top. In some embodiments, a width of the
openings 601 may be approximately equal to the width of the
openings 503. A depth D.sub.2 of the openings 601 may be between
about 100 .ANG. and about 1000 .ANG.. Bottoms of the openings 601
are lower than bottoms of the openings 401A. The patterning process
further forms bases 603A, 603B, and 603C for fins 403A, 403B, and
403C, respectively. Each of the bases 603A, 603B, and 603C is
interposed between respective adjacent openings 601. In the
illustrated embodiment, the group of fins 403A with the
corresponding base 603A, the group of fins 403B with the
corresponding base 603B, and the group of fins 403C with the
corresponding base 603C have a shape of a crown. Accordingly, such
structures may also be referred to as crown-shaped fin structures.
In the illustrated embodiment, each crown-shaped fin structure
comprises three fins. Alternatively, each crown-shaped fin
structure may comprise less than or more than three fins, depending
on the designed drive currents of the resulting FinFETs. In some
embodiments, the substrate 101 may be patterned by a suitable etch
process using the mask layer 501 (see FIGS. 5A and 5B) as an etch
mask. The suitable etch process may include an anisotropic dry etch
process, or the like. In some embodiments where the substrate 101
is formed of silicon, the substrate 101 is patterned by a reactive
ion etch (RIE) process with etch process gases including N.sub.2,
CH.sub.2F.sub.2, CF.sub.4, CHF.sub.3, CH.sub.3F, HBr, NF.sub.3, Ar,
He, Cl.sub.2, CH.sub.3F, SiCl.sub.4, the like, or a combination
thereof. The RIE process may be performed at a pressure between
about 1 mTorr and about 500 mTorr, a temperature between about
20.degree. C. and 150.degree. C., and a radio frequency (RF) power
between about 10 W and about 500 W. During the patterning process,
the mask layer 501 may be partially or fully consumed. If any
residue of the mask layer 501 is left over the substrate 101 and
the fins 403A, 403B and 403C after the patterning processes, the
residue may also be removed. In some embodiments where the mask
layer 501 is formed of a photoresist material, the residue of the
mask layer 501 may be removed using, for example, an ashing process
followed by a wet clean process.
Referring further to FIGS. 6A and 6B, not all of the fins 403A,
403B and 403C are active fins and are used to form FinFETs. In some
embodiments, the fins 403A and 403C are active fins, while the fins
403B are dummy fins and are not used for forming active FinFETs.
Accordingly, the fins 403B and the corresponding base 603B may be
also referred to as the dummy fins 403B and the dummy base 603B,
respectively. As described below in greater detail, the dummy fins
403B and the dummy base 603B are removed. In the illustrated
embodiment, two active fin structures (such as the active fins 403A
with the corresponding active base 603A, and the active fins 403C
with the corresponding active base 603C) and one dummy fin
structure (such as the dummy fins 403B with the corresponding dummy
base 603B) are shown. In other embodiments, a plurality of active
fin structures and a plurality of dummy fin structures may be
formed on the substrate 101, such that each dummy fin structure is
interposed between respective adjacent active fin structures. In
the illustrated embodiment, the active fin structures and the dummy
fin structures are portions of the initial substrate 101. In other
embodiments, the active fin structures and the dummy fin structures
may be formed on the substrate 101 by, for example, epitaxially
growing a suitable semiconducting material on the substrate
101.
Referring to FIGS. 7A and 7B, a mask layer 701 is formed over the
substrate 101 and the fins 403A, 403B and 403C. In some
embodiments, the mask layer 701 may be formed using similar
materials and methods as the mask layer 113, described above with
reference to FIGS. 1A and 1B, and the description is not repeated
herein for the sake of brevity. The mask layer 701 is patterned to
form openings 703 in the mask layer 701. In some embodiments, the
mask layer 701 may be patterned using similar methods as the mask
layer 113, described above with reference to FIGS. 1A and 1B, and
the description is not repeated herein for the sake of brevity. The
openings 703 expose respective dummy fin structures, such as the
dummy fins 403B and the corresponding dummy base 603B. In some
embodiments, a width of the openings 703 may be approximately equal
to or greater than a width of the dummy base 603B.
Referring to FIGS. 8A and 8B, the dummy fin structures, such as the
dummy fins 403B and the corresponding dummy base 603B, are removed
to form openings 801 separating active fin structures, such as the
active fins 403A with the corresponding active base 603A and the
active fins 403C with the corresponding active base 603C.
Furthermore, end portions of the active fins, such as the active
fins 403A and the active fins 403C, are removed. In some
embodiments, the dummy fin structures, such as the dummy fins 403B
and the corresponding dummy base 603B, may be removed by a main
etch process using the mask layer 701 (see FIGS. 7A and 7B) as an
etch mask. The main etch process may include a suitable etch
process, such as an anisotropic dry etch process, or the like. In
some embodiments where the substrate 101 is formed of silicon, the
main etch process includes a reactive ion etch (RIE) process with
etch process gases including N.sub.2, CH.sub.2F.sub.2, CF.sub.4,
CHF.sub.3, CH.sub.3F, HBr, NF.sub.3, Ar, He, Cl.sub.2, CH.sub.3F,
SiCl.sub.4, the like, or a combination thereof. The RIE process may
be performed at a pressure between about 3 mTorr and about 30
mTorr, a temperature between about 15.degree. C. and 70.degree. C.,
and a radio frequency (RF) power less than about 1500 W.
During the main etch process, the unremoved portions 303 of the
mask stack 109 over the dummy fins, such as the dummy fins 403B,
are exposed to etchants during a certain time and are etched to
expose the underlying dummy fins (see FIGS. 7A and 7B). The exposed
dummy fins, such as the dummy fins 403B, are then etched and
corresponding dummy bases, such as the dummy base 603B, are
exposed. The dummy bases, such as the dummy base 603B, are then
etched until the dummy bases are fully removed. In some
embodiments, the main etch process is performed for an etch time
t.sub.etch to fully remove the dummy fin structures, such as the
dummy fins 403B and the dummy base 603B. In some embodiments, the
etch time t.sub.etch may be between about 5 sec and about 200
sec.
In some embodiments, after the full removal of the dummy fin
structures, such as the dummy fins 403B and the corresponding dummy
base 603B, an over-etch process may be performed on the underlying
substrate 101 for an over-etch time t.sub.over-etch. In some
embodiments, the over-etch time t.sub.over-etch may be between
about 1 sec and about 20 sec, and an over-etch ratio
t.sub.over-etch/t.sub.etch may be between about 0.1 and about 1.5.
Depending on the main etch and over etch process recipes and the
over-etch ratio, bottoms of the openings 801 may have different
structures and shapes. In some embodiments, the bottom surfaces
801B may be planar surfaces. In other embodiments, two, three, or
more divots and protrusions may be formed at the bottoms of the
opening 801 such that the bottom surfaces 801B' are non-planar
surfaces. In such embodiments, the protrusions may be generated
directly underlying and vertically aligned to the removed dummy
fins, such as the dummy fins 403B (see FIGS. 7A and 7B), with the
number of protrusions equal to the number of the dummy fins.
Alternatively, the divots are generated directly underlying and
vertically aligned to the removed dummy fins, such as the dummy
fins 403B, with the number of divots equal to the number of the
dummy fins. In yet other embodiments, the number of divots and/or
the number of protrusions may be different from the number of the
removed dummy fins, such as the dummy fins 403B. In some
embodiments, the main etch process and the over-etch process may be
performed using different mixtures of etch process gases, different
temperatures, different pressures, different RF powers, different
bias voltages, and/or different etch times to obtain desired
structures of the bottoms of the opening 801. For example, the main
etch process may be performed using a mixture of process gases
including CF.sub.4, SF.sub.6, NF.sub.3, N.sub.2, Cl.sub.2, the
like, or a combination thereof, and the over-etch process may be
performed using a mixture of process gases including O.sub.2, HBr,
H.sub.2, N.sub.2, the like, or a combination thereof.
During performing the main etch and over-etch processes, the mask
layer 701 (see FIGS. 7A and 8B) may be partially consumed. The
remaining mask layer 701 may be then removed. In some embodiments
where the mask layer 701 is formed of a photoresist material, the
remaining mask layer 701 may be removed using, for example, an
ashing process followed by a wet clean process. After completing
the main etch and over-etch processes, the openings 801 may have a
depth D.sub.3 between about 10 nm and about 200 nm. In some
embodiments, the depth D.sub.3 of the openings 801 may be greater
than the depth D.sub.2 of the openings 601 (see FIGS. 6A and 6B).
In other embodiments, the depth D.sub.3 of the openings 801 may
approximately equal to the depth D.sub.2 of the openings 601.
Referring to FIGS. 9A and 9B, a dielectric material 901 is formed
over the substrate 101 to fill the openings 401A and 801 (see FIGS.
8A and 8B). In some embodiments, the dielectric material 901
includes a liner oxide 903, and a dielectric material 905 over the
liner oxide 903. The liner oxide 903 may be formed as a conformal
layer, whose horizontal portions and vertical portions have
thicknesses close to each other. In some embodiments, the thickness
of the liner oxide 903 may be between about 5 .ANG. and about 100
.ANG..
In some embodiments, the liner oxide 903 is formed by oxidizing
exposed surfaces of the substrate 101, the active fins 403A and
403C, and the active bases 603A and 603C in an oxygen-containing
environment, for example, through Local Oxidation of Silicon
(LOCOS), wherein oxygen (O.sub.2) may be included in the respective
process gas. In other embodiments, the liner oxide 903 may be
formed using, for example, In-Situ Steam Generation (ISSG) with
water steam or a combined gas of hydrogen (H.sub.2) and oxygen
(O.sub.2) used to oxidize the exposed surfaces of the substrate
101, the active fins 403A and 403C, and the active bases 603A and
603C. The ISSG oxidation may be performed at an elevated
temperature. In yet other embodiments, the liner oxide 903 is
formed using a deposition technique, such as ALD, CVD, Sub
Atmospheric Chemical Vapor Deposition (SACVD), or the like, or a
combination thereof.
The dielectric material 905 is then formed to fill the remaining
portions of the openings 401A and 801 (see FIGS. 8A and 8B). The
dielectric material 905 may overfill the openings 401A and 801,
such that a portion of the dielectric material 905 extends above a
top surface of the patterned mask stack 109. In some embodiments,
the dielectric material 905 may comprise silicon oxide, silicon
carbide, silicon nitride, the like, or a combination thereof, and
may be formed using Flowable Chemical Vapor Deposition (FCVD),
spin-on coating, CVD, ALD, High-Density Plasma Chemical Vapor
Deposition (HDPCVD), LPCVD, the like, or a combination thereof. In
some embodiments where FCVD is used to form the dielectric material
905, a silicon-and nitrogen-containing precursor (for example,
trisilylamine (TSA) or disilylamine (DSA)) is used, and hence the
resulting dielectric material 905 is flowable (jelly-like). In
other embodiments, the flowable dielectric material 905 is formed
using an alkylamino silane based precursor. During the deposition
of the dielectric material 905, plasma is turned on to activate the
gaseous precursors for forming the flowable oxide. After dielectric
material 905 is deposited, an anneal/curing step is performed,
which converts flowable dielectric material 905 into a solid
dielectric material.
Referring to FIGS. 10A and 10B, the portions of the dielectric
material 901 (see FIGS. 9A and 9B) extending over the top surface
of the patterned mask stack 109 is removed. The remaining portions
of the dielectric material 901 form isolation regions that may be
also referred to as shallow trench isolation (STI) regions 1001. In
some embodiments, a chemical mechanical polishing (CMP) is
performed to remove the portions of the dielectric material 901
extending over the top surface of the patterned mask stack 109. In
such embodiments, the mask stack 109 may be used as a CMP stop
layer, and hence the top surface of the mask stack 109 is
substantially coplanar with the top surfaces of the STI regions
1001. In other embodiments, the portions of the dielectric material
901 extending over the top surface of the patterned mask stack 109
may be removed using grinding, etching, the like, or a combination
thereof. In FIGS. 10A and 10B, and in subsequent FIGS. 11A-19C, the
liner oxide 903 and the dielectric material 905 (see FIGS. 9A and
9B) may not be shown separately, although they still exist. An
interface between the liner oxide 903 and the dielectric material
905 may be distinguishable due to different material properties
such as different types of materials and/or different densities, or
may not be distinguishable.
Referring to FIGS. 11A and 11B, the patterned mask stack 109 (see
FIGS. 10A and 10B) is removed. In some embodiments where the first
mask layer 103 comprises silicon nitride and the second mask layer
105 comprises silicon oxide, the second mask layer 105 may be
removed in a wet process using buffered hydrofluoric acid (BHF) as
an etchant, and the first mask layer 103 may be removed in a wet
process using hot phosphoric acid (H.sub.3PO.sub.4) as an etchant.
Subsequently, the STI regions 1001 are recessed to expose the
active fins 403A and 403C. The STI regions 1001 may be recessed
using an isotropic or anisotropic etching process, which may be a
dry etch process or a wet etch process. In some embodiments, the
STI regions 1001 are recessed using a dry etch method, in which the
process gases including NH.sub.3 and NF.sub.3 are used. In other
embodiments, the STI regions 1001 are recessed using a wet etch
method, in which the etchant solution is a dilute HF solution,
which may have an HF concentration lower than about 1 percent. In
some embodiments wherein both the second mask layer 105 and the STI
regions 1001 are formed of silicon oxide, a same etching process
may remove the second mask layer 105 and recess the STI regions
1001.
After recessing the STI regions 1001, the active fins 403A and 403C
protrude over the top surfaces of STI regions 1001. In some
embodiments, the portions of STI regions 1001 directly over the
active bases 603A and 603C are fully removed, and the top surfaces
of remaining STI regions 1001 are substantially coplanar with, or
slightly lower than, top surfaces of the active bases 603A and
603C. In other embodiments, the portions of STI regions 1001
directly over the active bases 603A and 603C are partially removed,
and the top surfaces of remaining STI regions 1001 are higher than
the top surfaces of the active bases 603A and 603C.
FIGS. 12A-12E illustrate cross-sectional views of fin structures
1200A-1200E, respectively, in accordance with some embodiments.
FIGS. 12A-12E illustrate embodiments wherein the number of
protrusions in the bottom of the openings 801 is equal to the
number of removed dummy fins. FIG. 12A illustrates a
cross-sectional view of a fin structure 1200A in accordance with
some embodiments. The fin structure 1200A may be formed using
similar method as the fin structure illustrated in FIGS. 11A and
11B, described above with reference to FIGS. 1A-11B, and the
description is not repeated herein for the sake of brevity. Like
features of the fin structure 1200A and the fin structure of FIGS.
11A and 11B are labeled by like numerical references. The fin
structure 1200A comprises a substrate 101, active fins 403A and
403C, corresponding active bases 603A and 603C, and STI regions
1001 in the openings 401A and 801 (see FIGS. 9A and 9B). The active
fins 403A and 403C and the corresponding active bases 603A and 603C
are separated by the opening 801, which may be formed by removing
dummy fins 403B and a corresponding dummy base 603B using similar
methods as described above with reference to FIGS. 7A-8B, and the
description is not repeated herein for the sake of brevity. In the
illustrated embodiment, a bottom surface 801B of the opening 801 is
a non-planar surface. The bottom of the opening 801 comprises three
protrusions 1201A.sub.1, 1201A.sub.2 and 1201A.sub.3 (collectively
referred to as protrusions 1201A) separated by divots 1203A, such
that the number of protrusions 1201A is equal to the number of
removed dummy fins 403B (see FIGS. 7A and 7B). In the illustrated
embodiment, bottommost surfaces of the divots 1203A are portions of
the bottom surface 801B of the opening 801 that are disposed
farthest from the top surfaces of the STI regions 1001. The
protrusions 1201A may be vertically aligned to the removed dummy
fins 403B. In some embodiments, the number of the protrusions 1201A
may be altered by altering the number of the removed dummy fins
403B. In the illustrated embodiment, a height H.sub.1 of the
protrusion 1201A.sub.1 and a height H.sub.3 of the protrusion
1201A.sub.3 are substantially equal, while a height H.sub.2 of the
protrusion 1201A.sub.2 is less than the height H.sub.1 of the
protrusion 1201A.sub.1 and the height H.sub.3 of the protrusion
1201A.sub.3. The height H.sub.1 may be between about 10 nm and
about 200 nm, the height H.sub.2 may be between about 10 nm and
about 150 nm, and a difference between the height H.sub.1 and the
height H.sub.2 may be between about 1 nm and about 200 nm. In other
embodiments, the heights H.sub.1, H.sub.2, and H.sub.3 may be
substantially equal or may be different from each other depending
on the etching process recipes of the main etch process and the
over-etch process, and on the over-etch ratio. The illustrated
structure of the bottom of the opening 801 may be obtained by
tuning the process parameters of the main etch process and the
over-etch process. The tunable process parameters may include a
process gas mixture, temperature, pressure, an RF power, a bias
voltage, and/or an over-etch ratio. In the illustrated embodiment,
the over-etch ratio t.sub.over-etch/t.sub.etch is tuned to be
between about 0.1 and about 0.35.
FIG. 12B illustrates a cross-sectional view of a fin structure
1200B in accordance with some embodiments. The fin structure 1200B
may be formed using similar method as the fin structure illustrated
in FIGS. 11A and 11B, described above with reference to FIGS.
1A-11B, and the description is not repeated herein for the sake of
brevity. Like features of the fin structure 1200B and the fin
structure of FIGS. 11A and 11B are labeled by like numerical
references. The fin structure 1200B comprises a substrate 101,
active fins 403A and 403C, corresponding active bases 603A and
603C, and STI regions 1001 in the openings 401A and 801 (see FIGS.
9A and 9B). The active fins 403A and 403C and the corresponding
active bases 603A and 603C are separated by the opening 801, which
may be formed by removing dummy fins 403B and a corresponding dummy
base 603B using similar methods as described above with reference
to FIGS. 7A-8B, and the description is not repeated herein for the
sake of brevity. In the illustrated embodiment, a bottom surface
801B of the opening 801 is a non-planar surface. The bottom of the
opening 801 comprises three protrusions 1201B.sub.1, 1201B.sub.2
and 1201B.sub.3 (collectively referred to as protrusions 1201B)
separated by divots 1203B, such that the number of the protrusions
1201B is equal to the number of the removed dummy fins 403B (see
FIGS. 7A and 7B). In the illustrated embodiment, bottommost
surfaces of the divots 1203B are portions of the bottom surface
801B of the opening 801 that are disposed farthest from the top
surfaces of the STI regions 1001. The protrusions 1201B may be
vertically aligned to the removed dummy fins 403B. In some
embodiments, the number of the protrusions 1201B may be altered by
altering the number of the removed dummy fins 403B. In illustrated
embodiment, a height H.sub.4 of the protrusion 1201B.sub.1 and a
height H.sub.6 of the protrusion 1201B.sub.3 are substantially
equal, while a height H.sub.5 of the protrusion 1201B.sub.2 is less
than the height H.sub.4 of the protrusion 1201B.sub.1 and the
height H.sub.6 of the protrusion 1201B.sub.3. The height H.sub.4
may be between about 10 nm and about 250 nm, the height H.sub.5 may
be between about 1 nm and about 200 nm, and a difference between
the height H.sub.4 and the height H.sub.5 may be between about 10
nm and about 50 nm. In other embodiments, the heights H.sub.4,
H.sub.5, and H.sub.6 may be substantially equal or may be different
from each other depending on the etching process recipe of the main
etch process and the over-etch process, and on the over-etch ratio.
The illustrated structure of the bottom of the opening 801 may be
obtained by tuning the process parameters of the main etch process
and the over-etch process. The tunable process parameters may
include a process gas mixture, temperature, pressure, an RF power,
a bias voltage, and/or an over-etch ratio. In the illustrated
embodiment, the over-etch ratio t.sub.over-etch/t.sub.etch may be
between about 0.4 and about 0.8.
FIG. 12C illustrates a cross-sectional view of a fin structure
1200C in accordance with some embodiments. The fin structure 1200C
may be formed using similar method as the fin structure illustrated
in FIGS. 11A and 11B, described above with reference to FIGS.
1A-11B, and the description is not repeated herein for the sake of
brevity. Like features of the fin structure 1200C and the fin
structure of FIGS. 11A and 11B are labeled by like numerical
references. The fin structure 1200C comprises a substrate 101,
active fins 403A and 403C, corresponding active bases 603A and
603C, and STI regions 1001 in the openings 401A and 801 (see FIGS.
9A and 9B). The active fins 403A and 403C and the corresponding
active bases 603A and 603C are separated by the opening 801, which
may be formed by removing dummy fins 403B and a corresponding dummy
base 603B using similar methods as described above with reference
to FIGS. 7A-8B, and the description is not repeated herein for the
sake of brevity. In the illustrated embodiment, a bottom surface
801B of the opening 801 is a non-planar surface. The bottom of the
opening 801 comprises three protrusions 1201C.sub.1, 1201C.sub.2
and 1201C.sub.3 (collectively referred to as protrusions 1201C)
separated by divots 1203C, such that the number of the protrusions
1201C is equal to the number of the removed dummy fins 403B (see
FIGS. 7A and 7B). In the illustrated embodiment, bottommost
surfaces of the divots 1203C are higher than portions of the bottom
surface 801B of the opening 801 that are disposed farthest from the
top surfaces of the STI regions 1001. The protrusions 1201C may be
vertically aligned to the removed dummy fins 403B. In some
embodiments, the number of the protrusions 1201C may be altered by
altering the number of the removed dummy fins 403B. In illustrated
embodiment, a height H.sub.7 of the protrusion 1201C.sub.1 and a
height H.sub.9 of the protrusion 1201C.sub.3 are substantially
equal, while a height H.sub.8 of the protrusion 1201C.sub.2 is
greater than the height H.sub.7 of the protrusion 1201C.sub.1 and
the height H.sub.9 of the protrusion 1201C.sub.3. The height
H.sub.7 may be between about 5 nm and about 100 nm, the height
H.sub.8 may be between about 5 nm and about 80 nm, and the height
H.sub.9 may be between about 5 nm and about 200 nm. In other
embodiments, the heights H.sub.7, H.sub.8, and H.sub.9 may be
substantially equal or may be different from each other depending
on the etching process recipe of the main etch process and the
over-etch process, and on the over-etch ratio. The illustrated
structure of the bottom of the opening 801 may be obtained by
tuning the process parameters of the main etch process and the
over-etch process. The tunable process parameters may include a
process gas mixture, temperature, pressure, an RF power, a bias
voltage, and/or an over-etch ratio. In the illustrated embodiment,
the over-etch ratio t.sub.over-etch/t.sub.etch may be between about
0.5 and about 0.7.
FIG. 12D illustrates a cross-sectional view of a fin structure
1200D in accordance with some embodiments. The fin structure 1200D
may be formed using similar method as the fin structure illustrated
in FIGS. 11A and 11B, described above with reference to FIGS.
1A-11B, and the description is not repeated herein for the sake of
brevity. Like features of the fin structure 1200D and the fin
structure of FIGS. 11A and 11B are labeled by like numerical
references. The fin structure 1200D comprises a substrate 101,
active fins 403A and 403C, corresponding active bases 603A and
603C, and STI regions 1001 in the openings 401A and 801 (see FIGS.
9A and 9B). The active fins 403A and 403C and the corresponding
active bases 603A and 603C are separated by the opening 801, which
may be formed by removing dummy fins 403B and a corresponding dummy
base 603B using similar methods as described above with reference
to FIGS. 7A-8B, and the description is not repeated herein for the
sake of brevity. In the illustrated embodiment, a bottom surface
801B of the opening 801 is a non-planar surface. The bottom of the
opening 801 comprises three protrusions 1201D.sub.1, 1201D.sub.2
and 1201D.sub.3 (collectively referred to as protrusions 1201D)
separated by divots 1203D, such that the number of the protrusions
1201D is equal to the number of the removed dummy fins 403B (see
FIGS. 7A and 7B). In the illustrated embodiment, bottommost
surfaces of the divots 1203D are higher than portions of the bottom
surface 801B of the opening 801 that are disposed farthest from the
top surfaces of the STI regions 1001. The protrusions 1201D may be
vertically aligned to the removed dummy fins 403B. In some
embodiments, the number of the protrusions 1201D may be altered by
altering the number of the removed dummy fins 403B. In illustrated
embodiment, a height H.sub.10 of the protrusion 1201D.sub.1, a
height H.sub.11 of the protrusion 1201D.sub.2, and a height
H.sub.12 of the protrusion 1201D.sub.3 are substantially equal. The
height H.sub.10 may be between about 5 nm and about 150 nm, the
height H.sub.11 may be between about 5 nm and about 100 nm, and the
height H.sub.12 may be between about 5 nm and about 200 nm. In
other embodiments, the heights H.sub.10, H.sub.11, and H.sub.12 may
be different from each other depending on the etching process
recipe of the main etch process and the over-etch process, and on
the over-etch ratio. The illustrated structure of the bottom of the
opening 801 may be obtained by tuning the process parameters of the
main etch process and the over-etch process. The tunable process
parameters may include a process gas mixture, temperature,
pressure, an RF power, a bias voltage, and/or an over-etch ratio.
In the illustrated embodiment, the over-etch ratio
t.sub.over-etch/t.sub.etch may be between about 0.8 and about
1.2.
FIG. 12E illustrates a cross-sectional view of a fin structure
1200E in accordance with some embodiments. The fin structure 1200E
may be formed using similar method as the fin structure illustrated
in FIGS. 11A and 11B, described above with reference to FIGS.
1A-11B, and the description is not repeated herein for the sake of
brevity. Like features of the fin structure 1200E and the fin
structure of FIGS. 11A and 11B are labeled by like numerical
references. The fin structure 1200E comprises a substrate 101,
active fins 403A and 403C, corresponding active bases 603A and
603C, and STI regions 1001 in the openings 401A and 801 (see FIGS.
9A and 9B). The active fins 403A and 403C and the corresponding
active bases 603A and 603C are separated by the opening 801, which
may be formed by removing dummy fins 403B and a corresponding dummy
base 603B using similar methods as described above with reference
to FIGS. 7A-8B, and the description is not repeated herein for the
sake of brevity. In the illustrated embodiment, a bottom surface
801B of the opening 801 is a non-planar surface. The bottom of the
opening 801 comprises three protrusions 1201E.sub.1, 1201E.sub.2
and 1201E.sub.3 (collectively referred to as protrusions 1201E)
separated by divots 1203E, such that the number of the protrusions
1201E is equal to the number of the removed dummy fins 403B (see
FIGS. 7A and 7B). In the illustrated embodiment, bottommost
surfaces of the divots 1203E are portions of the bottom surface
801B of the opening 801 that are disposed farthest from the top
surfaces of the STI regions 1001. The protrusions 1201E may be
vertically aligned to the removed dummy fins 403B. In some
embodiments, the number of the protrusions 1201E may be altered by
altering the number of the removed dummy fins 403B. In illustrated
embodiment, a height H.sub.13 of the protrusion 1201E.sub.1, a
height H.sub.14 of the protrusion 1201E.sub.2, and a height
H.sub.15 of the protrusion 1201E.sub.2 are substantially equal. The
height H.sub.13 may be between about 10 nm and about 80 nm, the
height H.sub.14 may be between about 10 nm and about 60 nm, and the
height H.sub.15 may be between about 10 nm and about 150 nm. In
other embodiments, the heights H.sub.13, H.sub.14, and H.sub.15 may
be different from each other depending on the etching process
recipe of the main etch process and the over-etch process, and on
the over-etch ratio. The illustrated structure of the bottom of the
opening 801 may be obtained by tuning the process parameters of the
main etch process and the over-etch process. The tunable process
parameters may include a process gas mixture, temperature,
pressure, an RF power, a bias voltage, and/or an over-etch ratio.
In the illustrated embodiment, the over-etch ratio
t.sub.over-etch/t.sub.etch may be between about 0.2 and about
0.4.
FIGS. 13A-13C illustrate cross-sectional views of fin structures
1300A-1300C in accordance with some embodiments. FIGS. 13A-13C
illustrate embodiments wherein the number of protrusions in the
bottom of the openings 801 does not equal to the number of removed
dummy fins. FIG. 13A illustrates a cross-sectional view of a fin
structure 1300A in accordance with some embodiments. The fin
structure 1300A may be formed using similar method as the fin
structure illustrated in FIGS. 11A and 11B, described above with
reference to FIGS. 1A-11B, and the description is not repeated
herein for the sake of brevity. Like features of the fin structure
1300A and the fin structure of FIGS. 11A and 11B are labeled by
like numerical references. The fin structure 1300A comprises a
substrate 101, active fins 403A and 403C, corresponding active
bases 603A and 603C, and STI regions 1001 in the openings 401A and
801 (see FIGS. 9A and 9B). The active fins 403A and 403C and the
corresponding active bases 603A and 603C are separated by the
opening 801, which may be formed by removing dummy fins 403B and a
corresponding dummy base 603B using similar methods as described
above with reference to FIGS. 7A-8B, and the description is not
repeated herein for the sake of brevity. In the illustrated
embodiment, a bottom surface 801B of the opening 801 is a
non-planar surface. The bottom of the opening 801 comprises two
protrusions 1301A.sub.1 and 1301A.sub.2 (collectively referred to
as protrusions 1301A) separated by a divot 1303A, such that the
number of the protrusions 1301A is different from the number of the
removed dummy fins 403B (see FIGS. 7A and 7B). In the illustrated
embodiment, a bottommost surface of the divot 1303A is a portion of
the bottom surface 801B of the opening 801 that is disposed
farthest from the top surfaces of the STI regions 1001. In
illustrated embodiment, a height H.sub.16 of the protrusion
1301A.sub.1 and a height H.sub.17 of the protrusion 1301A.sub.2 are
substantially equal. Alternatively, the height H.sub.16 of the
protrusion 1301A.sub.1 may be different from the height H.sub.17 of
the protrusion 1301A.sub.2. In some embodiments, the height
H.sub.16 may be between about 1 nm and about 200 nm, and the height
H.sub.17 may be between about 1 nm and about 200 nm. The
illustrated structure of the bottom of the opening 801 may be
obtained by tuning the process parameters of the main etch process
and the over-etch process. The tunable process parameters may
include a process gas mixture, temperature, pressure, an RF power,
a bias voltage, and/or an over-etch ratio. In the illustrated
embodiment, the over-etch ratio t.sub.over-etch/t.sub.etch may be
between about 0.85 and about 1.5.
FIG. 13B illustrates a cross-sectional view of a fin structure
1300B in accordance with some embodiments. The fin structure 1300B
may be formed using similar method as the fin structure illustrated
in FIGS. 11A and 11B, described above with reference to FIGS.
1A-11B, and the description is not repeated herein for the sake of
brevity. Like features of the fin structure 1300B and the fin
structure of FIGS. 11A and 11B are labeled by like numerical
references. The fin structure 1300B comprises a substrate 101,
active fins 403A and 403C, corresponding active bases 603A and
603C, and STI regions 1001 in the openings 401A and 801 (see FIGS.
9A and 9B). The active fins 403A and 403C and the corresponding
active bases 603A and 603C are separated by the opening 801, which
may be formed by removing dummy fins 403B and a corresponding dummy
base 603B using similar methods as described above with reference
to FIGS. 7A-8B, and the description is not repeated herein for the
sake of brevity. In the illustrated embodiment, a bottom surface
801B of the opening 801 is a non-planar surface. The bottom of the
opening 801 comprises two protrusions 1301B.sub.1 and 1301B.sub.2
(collectively referred to as protrusions 1301B) separated by a
divot 1303B, such that the number of the protrusions 1301B is
different from the number of the removed dummy fins 403B (see FIGS.
7A and 7B). In the illustrated embodiment, a bottommost surface of
the divot 1303B is lower than portions of the bottom surface 801B
of the opening 801 that are disposed farthest from the top surfaces
of the STI regions 1001. In illustrated embodiment, a height
H.sub.18 of the protrusion 1301B.sub.1 and a height H.sub.19 of the
protrusion 1301B.sub.2 are substantially equal. Alternatively, the
height H.sub.18 of the protrusion 1301B.sub.1 may be different from
the height H.sub.19 of the protrusion 1301B.sub.2. In some
embodiments, the height H.sub.18 may be between about 10 nm and
about 100 nm, and the height H.sub.19 may be between about 10 nm
and about 130 nm. The illustrated structure of the bottom of the
opening 801 may be obtained by tuning the process parameters of the
main etch process and the over-etch process. The tunable process
parameters may include a process gas mixture, temperature,
pressure, an RF power, a bias voltage, and/or an over-etch ratio.
In the illustrated embodiment, the over-etch ratio
t.sub.over-etch/t.sub.etch may be between about 0.9 and about
1.3.
FIG. 13C illustrates a cross-sectional view of a fin structure
1300C in accordance with some embodiments. The fin structure 1300C
may be formed using similar method as the fin structure illustrated
in FIGS. 11A and 11B, described above with reference to FIGS.
1A-11B, and the description is not repeated herein for the sake of
brevity. Like features of the fin structure 1300C and the fin
structure of FIGS. 11A and 11B are labeled by like numerical
references. The fin structure 1300C comprises a substrate 101,
active fins 403A and 403C, corresponding active bases 603A and
603C, and STI regions 1001 in the openings 401A and 801 (see FIGS.
9A and 9B). The active fins 403A and 403C and the corresponding
active bases 603A and 603C are separated by the opening 801, which
may be formed by removing dummy fins 403B and a corresponding dummy
base 603B using similar methods as described above with reference
to FIGS. 7A-8B, and the description is not repeated herein for the
sake of brevity. In the illustrated embodiment, a bottom surface
801B of the opening 801 is a non-planar surface. The bottom of the
opening 801 comprises two protrusions 1301C.sub.1 and 1301C.sub.2
(collectively referred to as protrusions 1301C) separated by a
divot 1303C, such that the number of the protrusions 1301C is
different from the number of the removed dummy fins 403B (see FIGS.
7A and 7B). In the illustrated embodiment, a bottommost surface of
the divot 1303C is lower than portions of the bottom surface 801B
of the opening 801 that are disposed farthest from the top surfaces
of the STI regions 1001. In illustrated embodiment, a height
H.sub.2O of the protrusion 1301C.sub.1 and a height H.sub.21 of the
protrusion 1301C.sub.2 are substantially equal. Alternatively, the
height H.sub.2O of the protrusion 1301C.sub.1 may be different from
the height H.sub.21 of the protrusion 1301C.sub.2. In some
embodiments, the height H.sub.2O may be between about 20 nm and
about 120 nm, and the height H.sub.21 may be between about 15 nm
and about 150 nm. The illustrated structure of the bottom of the
opening 801 may be obtained by tuning the process parameters of the
main etch process and the over-etch process. The tunable process
parameters may include a process gas mixture, temperature,
pressure, an RF power, a bias voltage, and/or an over-etch ratio.
In the illustrated embodiment, the over-etch ratio
t.sub.over-etch/t.sub.etch may be between about 1 and about
1.5.
Referring further to FIGS. 12A-12E and 13A-13C, the various
structures of the bottom of the opening 801 illustrated in FIGS.
12A-12E and 13A-13C improve isolation of the active fin structures
and aid in reducing stress in the resulting FinFETs. Depending on
the isolation and/or stress requirements for the resulting FinFETs,
a suitable structure illustrated in FIGS. 12A-12E and 13A-13C may
be used to form the FinFETs.
FIGS. 14-18C illustrate cross-sectional views of various
intermediate stages of fabrication of a semiconductor device 1400
from the fin structure illustrated in FIGS. 11A and 11B in
accordance with some embodiments. Similar process steps may be also
applied to the fin structures illustrated in FIGS. 12A-12E and
13A-13C to form respective semiconductor devices. Referring to FIG.
14, a dummy gate dielectric 1401 is formed over the active fins
403A and 403C and the STI regions 1001, and a dummy gate electrode
1403 is formed over the dummy gate dielectric 1401. The dummy gate
dielectric 1401 may comprise silicon oxide, and may be formed using
oxidation, CVD, LPCD, the like, or a combination thereof. The dummy
gate electrode 1403 may comprise polysilicon, and may be formed
using CVD, LPCD, the like, or a combination thereof.
Referring to FIGS. 15A, 15B and 15C, the dummy gate dielectric 1401
and the dummy gate electrode 1403 are patterned to form dummy gate
stacks 1501A and 1501C over the active fins 403A and 403C,
respectively. FIG. 15B illustrates a cross-sectional view obtained
from a vertical plane containing a line B-B in FIG. 15A, and FIG.
15C illustrates a cross-sectional view obtained from a vertical
plane containing a line C-C in FIG. 15B. In some embodiments, the
dummy gate electrode 1403 and the dummy gate dielectric 1401 may be
patterned using suitable lithography and etching processes. As
illustrated in FIGS. 15A, 15B, and 15C, the dummy gate stack 1501A
is formed on sidewalls and top surfaces of middle portions of the
active fins 403A, such that end portions of the active fins 403A
are exposed. Similarly, the dummy gate stack 1501C is formed on
sidewalls and top surfaces of middle portions of the active fins
403C, such that end portions of the active fins 403C are
exposed.
Referring further to FIGS. 15A, 15B and 15C, gate spacers 1503 are
formed on sidewalls of the dummy gate stacks 1501A and 1501C. The
gate spacers 1503 may comprise an oxide (such a silicon oxide,
aluminum oxide, titanium oxide, or the like), a nitride (such as
silicon nitride, titanium nitride, or the like), an oxynitride
(such as silicon oxynitride, or the like), an oxycarbide (such as
silicon oxycarbide, or the like), a carbonitride (such as silicon
carbonitride, or the like), the like, or a combination thereof. In
some embodiments, a gate spacer layer may be formed on top surfaces
and sidewalls of the dummy gate stacks 1501A and 1501C using CVD,
PECVD, ALD, the like, or a combination thereof. Subsequently, the
gate spacer layer is patterned using, for example, an anisotropic
dry etch process to remove horizontal portions of the spacer layer
from the top surfaces of the dummy gate stacks 1501A and 1501C.
Portions of the gate spacer layer remaining on the sidewalls of the
dummy gate stacks 1501A and 1501C form the gate spacers 1503.
Referring to FIGS. 16A, 16B and 16C, the exposed end portions of
the active fins 403A and 403C are removed. FIG. 16B illustrates a
cross-sectional view obtained from a vertical plane containing a
line B-B in FIG. 16A, and FIG. 16C illustrates a cross-sectional
view obtained from a vertical plane containing a line C-C in FIG.
16B. Since the unremoved portions of the active fins 403A and 403C
are not in the illustrated plane of FIG. 16C, they are shown with
dashed lines in FIG. 16C. In some embodiments, the exposed end
portions of the active fins 403A and 403C are removed by a suitable
etching process using the dummy gate stacks 1501A and 1501C,
respectively, as etch masks. After the etching process, the
portions of the active fins 403A and 403C directly underling the
dummy gate stacks 1501A and 1501C, respectively, remain unremoved.
The unremoved portions of the active fins 403A and 403C form
channel regions of the resulting FinFETs. In some embodiments, the
exposed end portions of the active fins 403A and 403C may removed
by etching using any acceptable etch process, such as a RIE,
neutral beam etch (NBE), tetramethyalammonium hydroxide (TMAH),
ammonium hydroxide (NH.sub.4OH) the like, or a combination thereof.
In the illustrated embodiments, recesses 1601A and 1601C formed
after removing the exposed end portions of the active fins 403A and
403C have bottoms substantially level with the top surfaces of the
adjacent STI regions 1001. In other embodiments, the bottoms of the
recesses 1601A and 1601C may be below the top surfaces of the
adjacent STI regions 1001.
Referring to FIGS. 17A, 17B and 17C, source/drain regions 1701A and
1701C are formed in the recesses 1601A and 1601C (see FIGS. 16A,
16B and 16C), respectively. FIG. 17B illustrates a cross-sectional
view obtained from a vertical plane containing a line B-B in FIG.
17A, and FIG. 17C illustrates a cross-sectional view obtained from
a vertical plane containing a line C-C in FIG. 17B. The
source/drain regions 1701A and 1701C are formed in the recesses
1601A and 1601C, respectively, by epitaxially growing a material in
the recesses 1601A and 1601C, such as by metal-organic CVD (MOCVD),
molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), vapor
phase epitaxy (VPE), selective epitaxial growth (SEG), the like, or
a combination thereof. As illustrated in FIG. 17C, the source/drain
region 1701A is a common continuous source/drain region for the
active fins 403A, and the source/drain region 1701C is a common
continuous source/drain region for the active fins 403C. The
source/drain regions 1701A and 1701C may have upward facing facets
and downward facing facets in accordance with some embodiments, or
may have other shapes.
In some embodiments in which the resulting FinFETs are n-type
FinFETs, the source/drain regions 1701A and 1701C comprise silicon
carbide (SiC), silicon phosphorous (SiP), phosphorous-doped silicon
carbon (SiCP), or the like. In some embodiments in which the
resulting FinFETs are p-type FinFETs, the source/drain regions
1701A and 1701C comprise SiGe, and a p-type impurity such as boron
or indium. In some embodiments in which the resulting FinFETs are
both n-type FinFETs and p-type FinFETs, the source/drain regions
1701A comprise silicon carbide (SiC), silicon phosphorous (SiP),
phosphorous-doped silicon carbon (SiCP), or the like, and the
source/drain regions 1701C comprise SiGe, and a p-type impurity
such as boron or indium. In some embodiments, the source/drain
regions 1701A and 1701C may be implanted with suitable dopants
followed by an anneal. The implanting process may include forming
and patterning masks such as a photoresist to cover the regions of
the FinFET that are to be protected from the implanting process. In
other embodiments, the source/drain regions 1701A and 1701C may be
in situ doped during the epitaxial growth process.
Referring to FIGS. 18A, 18B and 18C, a plurality of process steps
is performed to complete the formation of FinFETs 1801A and 1801C.
FIG. 18B illustrates a cross-sectional view obtained from a
vertical plane containing a line B-B in FIG. 18A, and FIG. 18C
illustrates a cross-sectional view obtained from a vertical plane
containing a line C-C in FIG. 18B. In some embodiments, the dummy
gate stacks 1501A and 1501C (see FIGS. 17A, 17B and 17C) are
replaced with replacement gate stacks 1807A and 1807C,
respectively. In some embodiments, the formation of the replacement
gate stacks 1807A and 1807C may include deposition of an interlayer
dielectric (ILD) 1803 over the dummy gate stacks 1501A and 1501C,
planarization of the ILD 1803 by, for example, a CMP process until
a top surface of the ILD 1803 is substantially level with top
surfaces of the dummy gate stacks 1501A and 1501C, and removal of
the dummy gate stacks 1501A and 1501C by, for example, a suitable
etching process to form recesses in the ILD 1803. Subsequently, the
gate dielectrics 1809A and 1809C are formed in the respective
recesses, and the gate electrodes 1811A and 1811C are formed over
the gate dielectrics 1809A and 1809C, respectively. In some
embodiments, excess material overfilling the recesses in the
ILD1803 may be removed by, for example, a CMP process. In such
embodiments, the top surface of the ILD 1803 is coplanar with top
surfaces of the replacement gate stacks 1807A and 1807C.
The ILD 1803 is formed of a dielectric material such as
phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped
phosphosilicate Glass (BPSG), undoped silicate glass (USG), the
like, or a combination thereof and may be deposited by any suitable
method, such as CVD, PECVD, FCVD, the like, or a combination
thereof. In some embodiments, the gate dielectrics 1809A and 1809C
may comprise a dielectric material such as, for example, silicon
oxide, silicon nitride, multilayers thereof, or the like, and may
be deposited or thermally grown according to acceptable techniques.
In other embodiments, the gate dielectrics 1809A and 1809C may
comprise a high-k dielectric material such as, for example, a metal
oxide or a silicate of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, the like,
multilayers thereof, and combinations thereof, and may be formed
by, for example, molecular-beam deposition (MBD), ALD, PECVD, the
like, or a combination thereof. In some embodiments, the gate
dielectric 1809A and the gate dielectric 1809C comprise a same
dielectric material. In other embodiments, the gate dielectric
1809A and the gate dielectric 1809C comprise different dielectric
materials. The gate electrodes 1811A and 1811C may comprise a
metallic material such as gold, silver, aluminum, copper, tungsten,
molybdenum, nickel, titanium, or alloys thereof, and may be formed
using physical vapor deposition (PVD), ALD, plating, the like, or a
combination thereof. In some embodiments, the gate electrode 1811A
and the gate electrode 1811C comprise a same conductive material.
In other embodiments, the gate electrode 1811A and the gate
electrode 1811C comprise different conductive materials.
Referring further to FIGS. 18A, 18B and 18C, an ILD 1805 is formed
over the ILD 1803 and the replacement gate stacks 1807A and 1807C.
The ILD 1805 may be formed using similar materials and methods as
the ILD 1803 and the description is not repeated herein for the
sake of brevity. In some embodiments, the ILD 1803 and the ILD 1805
may comprise a same dielectric material, such that an interface
between the ILD 1803 and the ILD 1805 may not be distinguishable.
In other embodiments, the ILD 1803 and the ILD 1805 may comprise
different dielectric materials.
In some embodiments, gate contacts 1813A and 1813C, and
source/drain contacts 1817A and 1817C are formed in the ILD 1803
and the ILD 1805. The gate contacts 1813A and 1813C are physically
and electrically coupled to the replacement gate stacks 1807A and
1807C, respectively. The source/drain contacts 1817A and 1817C are
physically and electrically coupled to the source/drain regions
1701A and 1701C, respectively. In some embodiments, openings for
the gate contacts 1813A and 1813C and the source/drain contacts
1817A and 1817C are formed through the ILD 1803 and the ILD 1805.
The openings may be formed using suitable photolithography and
etching techniques. A liner (not shown), such as a diffusion
barrier layer, an adhesion layer, or the like, and a conductive
material are formed in the openings. The liner may include
titanium, titanium nitride, tantalum, tantalum nitride, the like,
or a combination thereof. The conductive material may be copper, a
copper alloy, silver, gold, tungsten, aluminum, nickel, the like,
or a combination thereof. A planarization process, such as a CMP
process, may be performed to remove excess materials from a top
surface of the ILD 1805. The remaining liner and conductive
material form the gate contacts 1813A and 1813C and the
source/drain contacts 1817A and 1817C in the respective openings.
An anneal process may be performed to form silicides 1815A and
1815C at interfaces between the source/drain regions 1701A and
1701C and the source/drain contacts 1817A and 1817C, respectively.
Although not explicitly shown, a person having ordinary skill in
the art will readily understand that further processing steps may
be performed on the structure in FIGS. 18A, 18B and 18C. For
example, various inter-metal dielectrics (IMD) and their
corresponding metallizations may be formed over the ILD 1805.
FIGS. 19A, 19B, and 19C illustrate cross-sectional views of a
semiconductor device 1900 in accordance with some embodiments. FIG.
19B illustrates a cross-sectional view obtained from a vertical
plane containing a line B-B in FIG. 19A, and FIG. 19C illustrates a
cross-sectional view obtained from a vertical plane containing a
line C-C in FIG. 19B. The semiconductor device 1900 is similar to
the semiconductor device 1400 (see FIGS. 18A, 18B, and 18C), with
like elements labeled with like numerical references. In some
embodiments, the semiconductor device 1900 may be formed using
similar materials and methods as the semiconductor device 1400,
described above with reference to FIGS. 1A-18C, and the description
is not repeated herein for the sake of brevity. In the illustrated
embodiment, the source/drain regions 1701A and 1701C are individual
source/drain regions for each of the active fins 403A and for each
of the active fins 403C, respectively. Accordingly, the
source/drain regions 1701A and 1701C do not form common
source/drain regions for the group of active fins 403A and the
group of active fins 403C, respectively.
FIG. 20 is a flow diagram illustrating a method 2000 of forming a
semiconductor device in accordance with some embodiments. The
method 2000 starts with step 2001, where a patterned mask stack
(such as the mask stack 109 illustrated in FIGS. 3A and 3B) is
formed over a substrate (such as the substrate 101 illustrated in
FIGS. 3A and 3B) as described above with reference to FIGS. 1A-3B.
In step 2003, the substrate is patterned to form active
crown-shaped fin structures (such as the active fins 403A and 403C
with the respective active bases 603A and 603C illustrated in FIGS.
6A and 6B) and dummy crown-shaped fin structures (such as the dummy
fins 403B with the respective dummy base 603B illustrated in FIGS.
6A and 6B) as described above with reference to FIGS. 4A-6B. In
step 2005, a first etch processes is performed to remove the dummy
crown-shaped fin structures as described above with reference to
FIGS. 7A-8B. In step 2007, a second etch process is performed to
overetch the substrate as described above with reference to FIGS.
8A and 8B. In step 2009, isolation regions (such as the STI regions
1001 illustrated in FIG. 10) are formed as described above with
reference to FIGS. 9A-10B. In step 2011, the isolation regions are
recessed to expose active fins of the active crown-shaped fin
structures as described above with reference to FIGS. 11A and 11B.
In step 2013, dummy gate stacks (such as the dummy gate stacks
1501A and 1501C illustrated in FIGS. 15A, 15B and 15C) are formed
over the expose active fins of the active crown-shaped fin
structures as described above with reference to FIGS. 14, 15A, 15B
and 15C. In step 2015, the active fins of the active crown-shaped
fin structures are recessed as described above with reference to
FIGS. 16A, 16B and 16C. In step 2017, source/drain regions (such as
the source/drain regions 1701A and 1701C illustrated in FIGS. 17A,
17B and 17C) are epitaxially formed as described above with
reference to FIGS. 17A, 17B and 17C. In step 2019, replacement gate
stacks (such as the replacement gate stacks 1807A and 1807C
illustrated in FIGS. 18A, 18B and 18C) are formed as described
above with reference to FIGS. 18A, 18B and 18C.
The embodiments of the present disclosure have some advantageous
features. Various embodiments described herein allow for enlarging
a fin etch process window, better critical dimension (CD) loading
for strained source and drain (SSD) epitaxial (EPI) process, CVD
stress effect (bending) improvement, better wafer acceptance test
(WAT) and reliability performance, and better circuit probe (CP)
yield performance.
According to an embodiment, a method includes forming a first
active fin structure and a second active fin structure on a
substrate. A dummy fin structure is formed on the substrate, the
dummy fin structure being interposed between the first active fin
structure and the second active fin structure. The dummy fin
structure is removed to expose a first portion of the substrate,
the first portion of the substrate being disposed directly below
the dummy fin structure. A plurality of protruding features is
formed on the first portion of the substrate. A shallow trench
isolation (STI) region is formed over the first portion of the
substrate, the STI region covering the plurality of protruding
features, at least a portion of the first active fin structure and
at least a portion of the second active fin structure extending
above a topmost surface of the STI region.
According to another embodiment, a method includes forming a first
active base and a second active base on a substrate. A dummy base
is formed on the substrate, the dummy base being interposed between
the first active base and the second active base. A plurality of
first active fins is formed on the first active base. A plurality
of second active fins is formed on the second active base. A
plurality of dummy fins is formed on the dummy base. A first
etching process is performed on the plurality of dummy fins and the
dummy base to remove the plurality of dummy fins and the dummy base
and form a recess in the substrate. A second etching process is
performed on a bottom of the recess to form a plurality of
protruding features on the bottom of the recess. A shallow trench
isolation (STI) region is formed in the recess, a topmost surface
of the STI region being below topmost surfaces of the plurality of
first active fins and topmost surfaces of the plurality of second
active fins.
According to yet another embodiment, a structure includes a
plurality of first fins on a substrate, adjacent first fins being
separated by a plurality of first recesses, and a plurality of
second fins on the substrate, adjacent second fins being separated
by a plurality of second recesses. The structure further includes a
third recess in the substrate, the third recess being interposed
between the plurality of first fins and the plurality of second
fins, a bottom of the third recess being lower than bottoms of the
plurality of first recesses and bottoms of the plurality of second
recesses, and a plurality of protruding features on the bottom of
the third recess.
The foregoing outlines features of several embodiments so that
those skilled in the art may better understand the aspects of the
present disclosure. Those skilled in the art should appreciate that
they may readily use the present disclosure as a basis for
designing or modifying other processes and structures for carrying
out the same purposes and/or achieving the same advantages of the
embodiments introduced herein. Those skilled in the art should also
realize that such equivalent constructions do not depart from the
spirit and scope of the present disclosure, and that they may make
various changes, substitutions, and alterations herein without
departing from the spirit and scope of the present disclosure.
* * * * *