U.S. patent number 10,230,397 [Application Number 15/060,111] was granted by the patent office on 2019-03-12 for construction method for (n,n(n-1),n-1) permutation group code based on coset partition and codebook generator thereof.
This patent grant is currently assigned to HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY. The grantee listed for this patent is HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY. Invention is credited to Gaofeng Li, Kun Liang, Li Peng, Jiaolong Wei, Bo Zhou.
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United States Patent |
10,230,397 |
Peng , et al. |
March 12, 2019 |
Construction method for (n,n(n-1),n-1) permutation group code based
on coset partition and codebook generator thereof
Abstract
A construction method for a (n,n(n-1),n-1) permutation group
code based on coset partition is provided. The presented
(n,n(n-1),n-1) permutation group code has an error-correcting
capability of d-1 and features a strong anti-interference
capability for channel interferences comprising multi-frequency
interferences and signal fading. As n is a prime, for a permutation
code family with a minimum distance of n-1 and a code set size of
n(n-1), the invention provides a method of calculating n-1 orbit
leader permutation codewords by
O.sub.n={.alpha.o.sub.1}.sub..alpha.=1.sup.n-1(mod n) and
enumerating residual codewords of the code set by
P.sub.n=C.sub.nO.sub.n={(l.sub.1).sup.n-1O.sub.n}={(r.sub.n).sup.n-1O.sub-
.n)}. Besides, a generator of the code set thereof is provided. The
(n,n(n-1),n-1) permutation group code of the invention is an
algebraic-structured code, n-1 codewords of the orbit leader array
can be obtained simply by adder and (mod n) calculator rather than
multiplication of positive integers. Composition operations of the
cyclic subgroup C.sub.n acting on all permutations o.sub..alpha. of
the orbit leader permutation array O.sub.n are replaced by
well-defined cyclic shift composite operation functions
(l.sub.1).sup.n-1 and (r.sub.n).sup.n-1 so that the action of the
cyclic group acting on permutations is realized by a group of
cyclic shift registers.
Inventors: |
Peng; Li (Hubei, CN),
Li; Gaofeng (Hubei, CN), Wei; Jiaolong (Hubei,
CN), Liang; Kun (Hubei, CN), Zhou; Bo
(Hubei, CN) |
Applicant: |
Name |
City |
State |
Country |
Type |
HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY |
Wuhan, Hubei |
N/A |
CN |
|
|
Assignee: |
HUAZHONG UNIVERSITY OF SCIENCE AND
TECHNOLOGY (Wuhan, Hubei, CN)
|
Family
ID: |
56302623 |
Appl.
No.: |
15/060,111 |
Filed: |
March 3, 2016 |
Prior Publication Data
|
|
|
|
Document
Identifier |
Publication Date |
|
US 20170214414 A1 |
Jul 27, 2017 |
|
Foreign Application Priority Data
|
|
|
|
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Jan 26, 2016 [CN] |
|
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2016 1 0051144 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H03M
13/15 (20130101); H03M 13/611 (20130101); H03M
13/033 (20130101); H03M 13/617 (20130101); H03M
13/1525 (20130101); H04L 49/3027 (20130101); H04B
3/542 (20130101) |
Current International
Class: |
H03M
13/15 (20060101); H03M 13/00 (20060101); H04L
12/935 (20130101); H04B 3/54 (20060101) |
Other References
A J. Han Vinck, "Coded Modulation for Power Line Communications,"
in AEU Journal, Jan. 2000, p. 45-49. cited by applicant.
|
Primary Examiner: Blair; April Y
Assistant Examiner: Tang; Rong
Attorney, Agent or Firm: Hamre, Schumann, Mueller &
Larson, P.C.
Claims
What is claimed is:
1. A generator of an (n,n(n-1),n-1) permutation group code based on
coset partition, comprising: an orbit leader array generator that
generates n-1 orbit leader permutations by performing an operation
of O.sub.n={.alpha.o.sub.1}.sub..alpha.=1.sup.n-1(modn); a flash
memory; and a cyclic-bidirectional-shift register group, wherein
the flash memory stores output results of the orbit leader array
generator and the cyclic-bidirectional-shift register group; the
cyclic-bidirectional-shift register group performs an operation of
(l.sub.1).sup.n-1 or (r.sub.n).sup.n-1 acting on a permutation by
calculating the orbit {(l.sub.1).sup.n-1o.sub..alpha.} or
{(r.sub.n).sup.n-1o.sub..alpha.} of an orbit leader permutation
o.sub..alpha. and a code set {(l.sub.1).sup.n-1O.sub.n} or
{(r.sub.n).sup.n-1O.sub.n}, where .alpha.=1, 2, . . . , n-1,
wherein the orbit leader array generator calculates n-1 orbit
leader permutations by
O.sub.n={.alpha.o.sub.1}.sub..alpha.=1.sup.n-1
(modn)={o.sub.1,2o.sub.1, . . . , (n-1)o.sub.1}(modn) as an initial
input permutation is an identity permutation expressed by
o.sub.1=e=[12 . . . n] and storing calculating results in ROM
thereof; and the orbit leader array generator further comprises n
parallel running input buffers, n parallel running positive integer
adders, n parallel running modn calculators, n parallel running
output buffers, an n-input single-output switch and an enable
signal generator, wherein the n parallel running input buffers are
formed by n m-bit binary registers, an input and an output of each
register are connected to m parallel data lines respectively, and
2.sup.m-1+1.ltoreq.n.ltoreq.2.sup.m; the n parallel running
positive integer adders are operable for performing an operation of
{.alpha.o.sub.1}.sub..alpha.=1.sup.n-1, each positive integer adder
is formed by m' binary full-adders and an m'-bit B register, with m
parallel input data lines and m' parallel output data lines, and
m<m'.ltoreq..left brkt-top.log.sub.2(n-1).sup.2.right brkt-bot.,
an input of the binary full-adder is operable for receiving data
from the input buffer, another input of the binary full-adder is
connected to an output of the B register, an output of the binary
full-adder is connected to an input of the B register, and the n
parallel running positive integer adders are enabled as an enable
signal E=1 and disabled as the enable signal E=0; the n parallel
running modn calculators are operable for performing an operation
of {.alpha.o.sub.1}.sub..alpha.=1.sup.n-1(modn), each modn
calculator is formed by a two-input single-output general modn
calculator, an m-bit C register and an m-bit D register, with m'
parallel input data lines and m parallel output data lines, an
input of the general modn calculator is connected to the output of
the m'-bit B register through m' parallel input data lines, another
input of the general modn calculator is connected to an output of
the m-bit C register through m parallel output data lines, an
output of the general modn calculator is facilitated with m
parallel output data lines, the m-bit C register is operable for
storing and maintaining an m-bit binary value corresponding to n ,
the m-bit D register is operable for storing output values of the
general modn calculator, and a data stored in the m-bit D register
is output as it is not 0, otherwise a data stored in the m-bit C
register is output; the n parallel running output buffers are
formed by n m-bit registers, an input and an output of each m-bit
register are connected to m parallel data lines respectively, and
as the (n-1)th buffer of the n parallel running output buffers is
prepared with current data, this buffer sends a signal to the first
switch of the n-input single-output switch; the n-input
single-output switch is operable for serially transmitting each of
the n data from the n parallel running output buffers to a bus, m
data lines of the output buffer are connected to an m-paralleled
bus by connecting a corresponding switch, a connecting signal of
the the first switch of the n-input single-output switch is a
control signal output from the (n-1)th buffer of the n parallel
running output buffers, and a high level signal is transmitted to
an input of the enable signal generator as the n th switch of the
n-input single-output switch is on; the enable signal generator is
operable for providing enable signals for the n parallel running
positive integer adders and formed by a binary plus 1 counter and a
monostable flip-flop, with an input signal line and an output
signal line of maintaining a low level at a normal state, an input
of the binary plus 1 counter is connected to an output signal line
of the n th switch of the n-input single-output switch and receives
a control signal as the n th switch is on, the binary plus 1
counter performs an add-one operation and the monostable flip-flop
generates a high level impulse with a width of a cp, and transmits
the impulse to enable terminals of said n parallel running positive
integer adders through the output line, and as the binary plus 1
counter performs n-1 add-one operations, the monostable flip-flop
generates no impulse and the enable signal generator outputs a low
level; and wherein the cyclic-bidirectional-shift register group is
operable for realizing an orbit {(l.sub.1).sup.n-1o.sub..alpha.} or
{(r.sub.n).sup.n-1o.sub..alpha.} and a code set
{(l.sub.1).sup.n-1O.sub.n} or {(r.sub.n).sup.n-1O.sub.n} and formed
by a flip-flop array of m rows and n columns, a bidirectional
register capable of cyclic-shifting to both the left and the right
is formed by n flip-flops in each row of m rows, each of m switches
is connected to each of the cyclic-left-shift loops, m switches
operates in parallel, m binary are cyclic-left-shifted in parallel
through closing m switches, and m binary are left-shifted to input
or output in parallel by opening m switches, and two ports REG-in
and REG-out are facilitated to provide four groups of control
signals 00, 01, 10 and 11 corresponding to four working states of
the cyclic-bidirectional -shift register group: left-shift-input,
left-shift-output, cyclic-left-shift and cyclic-right-shift.
Description
FIELD OF THE INVENTION
The invention relates to a technical field of channel coding in
communication transmission, and more particularly to a construction
method for a (n,n(n-1),n-1) permutation group code based on coset
partition and a codebook generator thereof.
BACKGROUND OF THE INVENTION
Multiple interferences comprising multipath fading, permanent
narrow-band noise, broadband impulse noise and colored background
noises may coexist in a power line channel, which is uncommon for
wireless and wired channels.
Therefore, information transmission reliability is hard to be
guaranteed by applying existing technology of wireless and wired
communications directly to power line carrier communication
channels, and it is necessary to propose a solution of
error-correcting codes with higher reliability to interferences of
multiple forms and multiple frequencies in power line carrier
communication.
Besides, error-correcting codes with higher reliability are still
needed for wider wireless transmission environment with
interferences of multiple forms and multiple frequencies.
In 2000, Vinck introduced permutation codes into power line carrier
communication, and a corresponding dissertation "`Coded modulation
for power line communications`, AEU int. J. Electron. Commun., vol.
54, no. 1, pp: 45-49, 2000" discloses a power line carrier coded
modulation method combining permutation code and M-dimension FSK
modulation, where time diversity and frequency diversity are
introduced simultaneously at a transmitter terminal according to
redundancy of permutation codes to increase capability of resisting
fading and interferences of multiple frequencies, and a receiving
signal is detected by a constant envelope demodulation algorithm at
a receiver terminal to form a simple non-coherent demodulation
method. It should be noted that Vinck came to a conclusion that
permutation codes have an error-correcting capability of d-1 rather
than .left brkt-bot.(d-1)/2.right brkt-bot. through analyzing a
permutation code with code length of 4. However, Vinck failed to
provide an effective construction method for permutation codes. At
present, permutation codes with an error-correcting capability of
d-1 develop slowly and are not applied in practice for design
methods for algebraic structures of permutation codes are rare and
more particularly, the problem of their executable circuits has not
been effectively solved yet.
SUMMARY OF THE INVENTION
In view of the above-mentioned problems, it is an objective of the
invention to provide a construction method of (n,n(n-1),n-1)
permutation group code based on coset partition and a codebook
generator thereof. More specifically, there is provided an
algebraic structural design method and a codebook enumerator for
permutation codes with a code length of n, a minimum distance of
n-1, a cardinality of n(n-1) and an error-correcting capability of
d-1=n-2. For multiple interferences comprising multipath fading,
permanent narrow-band noise, broadband impulse noise and colored
background noises may coexist in a power line channel, the
invention provides a design method for an error-correcting code
capable of resisting the mixed interferences. Besides, the
permutation group code of the invention features a strong
anti-interference capability for multi-frequency interferences in
wireless communication and malicious frequency interferences from a
human being, and is capable of protecting transmitted signals under
the circumstance with low requirement for data rate and coexisted
deep fading and various mixed frequency interferences.
To achieve the above objective, according to one embodiment of the
invention, there is provided a construction method of the
(n,n(n-1),n-1) permutation group codes based on coset partition,
wherein a construction of this permutation code with a code length
of n, a minimum distance of n-1 and a code size of n(n-1) is
expressed by
P.sub.n={{p.sub..beta..alpha.}.sub..beta.=1.sup.n}.sub..alpha.=1.sup.n-1=-
C.sub.nO.sub.n={{C.sub.no.sub.1}, {C.sub.no.sub.2}, . . . ,
{C.sub.no.sub.n-1}}={{c.sub..beta..smallcircle.o.sub..alpha.}.sub..beta.=-
1.sup.n}.sub..alpha.=1.sup.n-1, P.sub.n=C.sub.nO.sub.n represents
that C.sub.n is a coset of the subgroup O.sub.n and O.sub.n is also
a coset of the subgroup C.sub.n, P.sub.n={{C.sub.no.sub.1},
{C.sub.no.sub.2}, . . . , {C.sub.no.sub.n-1}} represents dividing
P.sub.n into n-1 cosets by the subgroup C.sub.n, each coset
{C.sub.no.sub..alpha.} forms an orbit or an cyclic Latin square
(C-LS) of a permutation o.sub..alpha.,
P.sub.n={{p.sub..beta..alpha.}.sub..beta.=1.sup.n}.sub..alpha.=1.sup.n-1=-
{{c.sub..beta..smallcircle.o.sub..alpha.}.sub..beta.=1.sup.n}.sub..alpha.=-
1.sup.n-1 represents a permutation code and each codeword
p.sub..beta..alpha. is generated by composition operation of a
permutation c.sub..beta. of the subgroup C.sub.n and a permutation
o.sub..alpha. of the subgroup O.sub.n, .alpha.=1, 2, . . . n-1, and
.beta.=1, 2, . . . n.
According to another embodiment of the invention, there is provided
a generator of the (n,n(n-1),n-1) permutation group code based on
coset partition, comprising an orbit leader array generator, a
flash memory and a cyclic-bidirectional-shift register group,
wherein
the orbit leader array generator is operable for performing an
operation of O.sub.n={.alpha.o.sub.1}.sub..alpha.=1.sup.n-1(mod n)
to generate n-1 orbit leader permutations;
the flash memory is operable for storing output results of the
orbit leader array generator and the cyclic-bidirectional-shift
register group; and
the cyclic-bidirectional-shift register group is operable for
performing the operation of (l.sub.1).sup.n-1 or (r.sub.n).sup.n-1
acting on a permutation by calculating an orbit
{(l.sub.1).sup.n-1o.sub..alpha.} or
{(r.sub.n).sup.n-1o.sub..alpha.} of an orbit leader permutation
o.sub..alpha. and a code set {(l.sub.1).sup.n-1O.sub.n} or
{(r.sub.n).sup.n-1O.sub.n}, where .alpha.=1, 2, . . . , n-1.
The (n,n(n-1),n-1) permutation group code based on coset partition
of the invention is an algebraic-structured code, the orbit leader
permutation codewords of the code set can be obtained simply by
adder and (mod n) calculator instead of complex composition
operations, and the whole code set can be realized by a group of
cyclic shift registers. As a non-binary error-correcting code, the
permutation code has an error-correcting capability of d-1, two
times that of non-binary error-correcting codes in prior art.
Demodulation can be realized simply by a noncoherent constant
envelop detecting technology at a receiver terminal combining
permutation code with MFSK modulation technology, and signal
transmission reliability can be guaranteed for communication
channels with deep fading and mixed frequency noises.
BRIEF DESCRIPTION OF THE ACCOMPANYING DRAWINGS
FIG. 1 is an overall block diagram of a generator for a
(n,n(n-1),n-1) permutation group code of the invention;
FIG. 2 is a schematic diagram of an orbit leader array generator of
the invention;
FIG. 3 is a schematic diagram of a flash memory of the invention;
and
FIG. 4 is a schematic diagram of a cyclic-bidirectional-shift
register group of the invention.
SPECIFIC EMBODIMENTS OF THE INVENTION
For clear understanding of the objectives, features and advantages
of the invention, detailed description of the invention will be
given below in conjunction with accompanying drawings and specific
embodiments. It should be noted that the embodiments are only meant
to explain the invention, and not to limit the scope of the
invention.
Basic Principles
Basic principles of a (n,n(n-1),n-1) permutation group code based
on coset partition of the invention are given below.
Code symbols can take values in two finite fields, namely,
Z.sub.n.sup.0={0, 1, . . . , n-1} represents a finite field of
order n containing element 0, and Z.sub.n.sup.1={1, 2, . . . , n}
represents a finite positive integer field of order n containing no
element 0, and is also a cyclic group of order n.
Calling a set formed by all n! permutations of n elements in
Z.sub.n.sup.0 or Z.sub.n.sup.1 a symmetric group
S.sub.n={.pi..sub.1, . . . , .pi..sub.k, . . . , .pi..sub.n!}, an
element of S.sub.n, can be represented by a permutation
.pi..sub.k=[a.sub.1, . . . a.sub.i, . . . , a.sub.n],elements of a
permutation by a.sub.1 . . . a.sub.i . . . a.sub.n.di-elect
cons.Z.sub.n.sup.0 or a.sub.1 . . . a.sub.i . . . a.sub.n.di-elect
cons.Z.sub.n.sup.1, degree (dimension) of a permutation is
|.pi..sub.k|=n, and cardinality (order) of the symmetric group is
|S.sub.n=n!. Let .pi..sub.0=e=[a.sub.1a.sub.2 . . . a.sub.n]=[01 .
. . n-1] or .pi..sub.0=e=[a.sub.1a.sub.2 . . . a.sub.n]=[12 . . .
n] represent an identity element of the symmetric group S.sub.n,
where [a.sub.1a.sub.2 . . . a.sub.n] represent a permutation in
S.sub.n, and (a.sub.1a.sub.2 . . . a.sub.n) represents a
permutation operator.
A group H is a cyclic permutation group if H can be generated by a
single element, i.e., there is an element x.di-elect cons.H such
that H={x.sup.1|i.di-elect cons.Z.sub.n.sup.1, x, x.sup.i.di-elect
cons.S.sub.n}. We shall write H=x and say that H is generated by x
or x is a generator of H.
Let .gamma.=.gamma..sub.2 be a cyclic permutation group of n
permutation operators, its generator is
.gamma..sub.2=(a.sub.2a.sub.3 . . . a.sub.na.sub.1), and its
cardinality is |.gamma.|=n. If making the operator set
.gamma.=.gamma..sub.2 act on a permutation .pi.=[a.sub.1 . . .
a.sub.i . . . a.sub.n], we get {.gamma..pi.}={{.gamma..sub.2,
.gamma..sub.3, . . . , .gamma..sub.n, .gamma..sub.1}[a.sub.1 . . .
a.sub.i . . . a.sub.n]}={.gamma..sub.2.pi.}={{.gamma..sub.2,
.gamma..sub.2.sup.2, . . . ,
.gamma..sub.2.sup.n-1.gamma..sub.2.sup.n}[a.sub.1 . . . a.sub.i . .
. a.sub.n]}, then {.gamma..pi.} is regarded as an orbit containing
permutation .pi. under the action of cyclic permutation group 7 and
element number of the orbit {.gamma..pi.} is |{.gamma..pi.}|=n.
Basic structure of the (n,n(n-1),n-1) permutation group code based
on coset partition is provided by the following two Theorems and a
Lemma without a proof.
Lemma 1 [construction of c.sub.n]: C.sub.n={c.sub.1, c.sub.2, . . .
, c.sub.n}=c.sub.2 is a subgroup of S.sub.n and also a cyclic
permutation group with minimum distance d.sub.C.sub.n=n and
cardinality |C.sub.n|=n if and only if (i)
C.sub.n={.gamma..pi.}={.gamma..sub.2[a.sub.1a.sub.2 . . .
a.sub.n]}; (ii) its subscript is specified to keep consistent with
the value of the first element of each permutation in C.sub.n,
i.e.,
c.sub.1=.gamma..sub.1.pi.=c.sub.2.sup.n=.gamma..sub.2.sup.n.pi.=(a.sub.2a-
.sub.3 . . . a.sub.na.sub.1).sup.n[a.sub.1a.sub.2 . . .
a.sub.na.sub.1]=[a.sub.1a.sub.2 . . . a.sub.n],
c.sub.2=.gamma..sub.2.pi.=[a.sub.2a.sub.3 . . . a.sub.na.sub.1],
c.sub.3=.gamma..sub.3.pi.=c.sub.2.sup.2=.gamma..sub.2.sup.2.pi.=(a.sub.2a-
.sub.3 . . . a.sub.na.sub.1).sup.2[a.sub.1a.sub.2 . . .
a.sub.n]=[.sub.3a.sub.4 . . . a.sub.na.sub.1a.sub.2], . . . ,
c.sub.n=.gamma..sub.n.pi.=c.sub.2.sup.n-1=.gamma..sub.2.sup.n-1.pi.=(a.su-
b.2a.sub.3 . . . a.sub.na.sub.1).sup.n-1[a.sub.1a.sub.2 . . .
a.sub.n]=[a.sub.na.sub.1a.sub.2 . . . a.sub.n-1].
Theorem 2 [construction of O.sub.n]: Let O.sub.n, be a
(n-1).times.n permutation array or a set formed by n-1
permutations, and construct
O.sub.n={{o.sub..alpha.}.sub..alpha.=1.sup.n-1}={(.alpha.o.sub.1}.sub..al-
pha.=1.sup.n-1, where o.sub.1=[12 . . . n] is an identity
permutation, and .alpha.=1, 2, . . . , n-1 is the row index of
permutation array O.sub.n, also as an index of the number of
permutations in the set O.sub.n. If and only if i) n is a prime;
ii) for all .alpha.=1, 2, . . . , n-1, we have (.alpha.n)(mod n)=n;
then the set O.sub.n is a subgroup of S.sub.n, all elements of the
nth column in the array O.sub.n are n, and the minimum distance of
O.sub.n is d.sub.O.sub.n=n-1 and its cardinality is
|O.sub.n|=n-1.
Theorem 3 [constructing a permutation group code P.sub.n by C.sub.n
and O.sub.n]: For any prime n, let P.sub.n=({p.sub.11, . . . ,
p.sub..beta..alpha., . . . p.sub.n(n-1)} be a nontrivial subgroup
of S.sub.n, we use the composition of C.sub.n and O.sub.n to
construct P.sub.n, i.e.,
P.sub.n={{p.sub..beta..alpha.}.sub..beta.=1.sup.n}.sub..alpha.=1.sup.n-1=-
C.sub.nO.sub.n={{(c.sub..beta..smallcircle.o.sub..alpha.}.sub..beta.=1.sup-
.n}.sub..alpha.=1.sup.n-1, where
c.sub..beta..smallcircle.o.sub..alpha. denotes a composition
operation between a permutation c.sub..beta..di-elect cons.C.sub.n
and a permutation o.sub..alpha..di-elect cons.O.sub.n. If
C.sub.n.andgate.O.sub.n=e=[12 . . . n], then P.sub.n is a
permutation group code with the minimum Hamming distance
d.sub.P.sub.n=n-1 and cardinality |P.sub.n|=n(n-1) in which C.sub.n
is a left coset of O.sub.n and O.sub.n is a right coset of
C.sub.n.
EXAMPLE 1
Let n=5, and C.sub.5 is obtained by Lemma 1 as follows:
.gamma..times..pi..gamma..times..pi..gamma..times..pi..gamma..times..pi..-
gamma..times..pi..gamma..times..pi..times..times..times..times..function..-
times..times..times..times..times..times..times..times..function..times..t-
imes..times..times..times..times..times..times..function..times..times..ti-
mes..times..times..times..times..times..function..times..times..times..tim-
es..times..times..times..times..function..times..times..times..times..time-
s..times..times..times..times..times..times..times..times..times..times..t-
imes..times..times..times..times..times..times..times..times.
##EQU00001##
O.sub.5 in a form of permutation array is obtained by Theorem 2 as
follows:
.times..times..times..times. ##EQU00002##
.times..times..times..times..times. ##EQU00002.2##
So that O.sub.5 in a form of set is obtained as follows:
.times..times..times..times..times..times..times..times..times..times..ti-
mes..times..times..times..times..times. ##EQU00003##
Let c.sub.1=o.sub.1=e=[12345], and P.sub.5 is obtained by Theorem 3
as follows:
.beta..times..times..alpha..beta..alpha..times..times..times..times..beta-
..alpha..beta..alpha..times..times..times..times..times..times..times..tim-
es..times..times..times..times..times..times..times..times..times..times..-
times..times..times..times..times..times..times..times..times..times..time-
s..times..times..times..times..times..times..times..times..times..times..t-
imes..times..times..times..times..times..times..times..times..times..times-
..times..times..times..times..times..times..times..times..times..times..ti-
mes..times..times..times..times..times..times..times..times..times..times.-
.times..times..times..times..times..times..times..times..times.
##EQU00004##
Example 1 illustrates P.sub.5 is a permutation group code with a
code length of 5, a minimum distance of 4, a code set size of 20
and an error-correcting capability of 3, and it can be seen that
P.sub.5 is formed by four orbits {C.sub.5o.sub.1},
{C.sub.5o.sub.2}, {C.sub.5o.sub.3}, {C.sub.5o.sub.4}.
Technical Solution
It is formed by two parts. The first part covers a construction
method for a (n, n(n-1),n-1) permutation group code based on coset
partition, and the second part covers a generator of this
permutation group code thereof.
Part 1: A Construction Method for a (n,n(n-1),n-1) Permutation
Group Code Based on Coset Partition.
In terms of Lemma 1 and Theorems 2 and 3, in the construction
method for a (n,n(n-1),n-1) permutation group code based on coset
partition, all codewords in the code set are calculated by
P.sub.n={{p.sub..beta..alpha.}.sub..beta.=1.sup.n}.sub..alpha.=1.sup.n-1=-
C.sub.nO.sub.n={{C.sub.no.sub.1}, {C.sub.no.sub.2}, . . . ,
{C.sub.no.sub.n-1}}={{c.sub..beta..smallcircle.o.sub..alpha.}.sub..alpha.-
=1.sup.n-1}.sub..beta.=1.sup.n, where P.sub.n is a non-trivial
subgroup of a symmetric group S.sub.n, with a size of
|P.sub.n|=n(n-1) and a minimum distance of
d.sub.|P.sub.n.sub.|=n-1, C.sub.n={c.sub.1, . . . , c.sub..beta., .
. . , c.sub.n}=c.sub.2 is a subgroup of P.sub.n and also a cyclic
group with a size of |C.sub.n|=n and a minimum distance of
d.sub.|C.sub.n.sub.|=n, .beta.=1, 2, . . . , n, O.sub.n={o.sub.1, .
. . , o.sub..alpha., . . . , o.sub.n-1} is another subgroup of
P.sub.n different from C.sub.n and also called as an orbit leader
array of the (n,n(n-1),n-1) permutation group code, with a size of
|O.sub.n|=n-1 and a minimum distance of d.sub.|O.sub.n.sub.|=n-1,
.alpha.=1, 2, . . . , n-1, and intersection of C.sub.n and O.sub.n
is an identity permutation (C.sub.n.andgate.O.sub.n=e). The code
set P.sub.n is divided into n-1 cosets by the subgroup C.sub.n
(={C.sub.no.sub.1, C.sub.no.sub.2, . . . , C.sub.no.sub.n-1}), each
coset {C.sub.no.sub..alpha.} forms an orbit or an cyclic Latin
square (C-LS) of a permutation o.sub..alpha..
Each codeword of the code set is calculated by
P.sub..beta..alpha.=c.sub..beta..smallcircle.o.sub..alpha.
representing a composition operation between a permutation
c.sub..beta..di-elect cons.C.sub.n and a permutation
o.sub..alpha..di-elect cons.O.sub.n, which is unfavorable for
hardware realization, and therefore a circuit executable
permutation operation function should be constructed. Since C.sub.n
is a cyclic group, it is possible to substitute cyclic shift
operation of a permutation for the action of C.sub.n, so that
composition operation of two permutations are equivalently
transferred to cyclic shift operation of being able to be performed
by basic unit circuit namely cyclic shift register. Therefore,
operation function and composite operation function are defined
first as follows.
Construction of Operation Function
Let T be a set of all operation functions available acting on a
permutation, construct a right-shift operation function set
T.sub.right={r.sub.2, r.sub.3, . . . , r.sub.n-1, r.sub.n}.OR
right.T, where each element r.sub.i.di-elect cons.T.sub.right is a
function r.sub.i:S.sub.n.fwdarw.S.sub.n defined by
r.sub.i.pi.=r.sub.i[a.sub.1 . . . a.sub.i . . .
a.sub.n]=[a.sub.ia.sub.1 . . . a.sub.i-1a.sub.i+1 . . .
a.sub.n].di-elect cons.S.sub.n, and r.sub.i.di-elect
cons.T.sub.right is called as a partial cyclic right-shift
operation function of a permutation. Especially for i=n, we have
r.sub.n.pi.=r.sub.n[a.sub.1a.sub.2 . . .
a.sub.n]=[a.sub.na.sub.1a.sub.2 . . . a.sub.n-1].di-elect
cons.S.sub.n and r.sub.n is called as a cyclic-right-shift
operation function of a permutation. Similarly, construct a
left-shift operation function set T.sub.left={l.sub.1, l.sub.2, . .
. , l.sub.n-1}.OR right.T, where each element l.sub.j.di-elect
cons.T.sub.left is a function l.sub.j:S.sub.n.fwdarw.S.sub.n
defined by l.sub.j.pi.=l.sub.j[a.sub.1 . . . a.sub.j . . .
a.sub.n]=[a.sub.1 . . . a.sub.j-1 a.sub.j+1 . . .
a.sub.na.sub.j].di-elect cons.S.sub.n, and l.sub.j.di-elect
cons.T.sub.left is called as a partial cyclic left-shift operation
function of a permutation. Especially for j=1, we have
l.sub.1.pi.=l.sub.1[a.sub.1a.sub.2 . . . a.sub.n]=[a.sub.2a.sub.3 .
. . a.sub.n-1a.sub.na.sub.1].di-elect cons.S.sub.n and l.sub.1 is
called as a cyclic-left-shift operation function of a
permutation.
Construction of Cyclic Shift Composite Operation Function
Arrange part or all operation functions of the set T.sub.left or
T.sub.right in a string or consecutive multiplication of powers of
different functions, so that the operation function string or the
product of function powers forms a composite operation function
represented as f.sub.CF (u, .LAMBDA.), where u is the number of
operation functions in the composite operation function f.sub.CF(u,
.LAMBDA.), and .LAMBDA. is an arranging rule of the operation
functions, which is: some a function is repeatedly used for
.lamda.-1 times, and as .lamda.=n, a left cycle composite operation
function is constructed as
.function..LAMBDA..times..times..times..times. ##EQU00005## and a
right cycle composite operation function is constructed as
.function..LAMBDA..times..times..times..times..times. ##EQU00006##
Performing the two composite operation functions on a permutation
.pi.=[a.sub.1a.sub.2 . . . a.sub.n] respectively, two sets of n
permutations are obtained as {(l.sub.1).sup.n-1.pi.}{.pi.,
l.sub.1.pi., l.sub.1.sup.2.pi., . . . , l.sub.1.sup.n-1.pi.} and
{(r.sub.n).sup.n-1.pi.} {.pi., r.sub.n.pi., r.sub.n.sup.2.pi., . .
. , r.sub.n.sup.n-1 .pi.}. {(l.sub.1).sup.n-1.pi.} and
{(r.sub.n).sup.n-1.pi.} are two orbits of the permutation .pi. as
the orbit {C.sub.n.pi.}, we have
{C.sub.n.pi.}={(l.sub.1).sup.n-1.pi.}={(r.sub.n).sup.n-1.pi.},
namely, three orbits obtained by the three different operations
form equivalence class but corresponding C-LSs are not equal each
other because of different arrangement of permutations in these
orbits.
As a result, the cyclic group C.sub.n of the code set
P.sub.n={C.sub.nO.sub.n} can be replaced by the left cycle
composite operation function (l.sub.1).sup.n-1 or the right cycle
composite operation function (r.sub.n).sup.n-1, each orbit
{C.sub.no.sub..alpha.} is obtained by
{C.sub.no.sub..alpha.}={(r.sub.n).sup.n-1o.sub..alpha.}={(l.sub.1).sup.n--
1o.sub..alpha.}, the expression enumerating all codewords is,
P.sub.n=C.sub.nO.sub.n={(r.sub.n).sup.n-1O.sub.n}={{(r.sub.n).sup.n-1o.su-
b.1}, {(r.sub.n).sup.n-1o.sub.2}, . . . ,
{(r.sub.n).sup.n-1o.sub.n-1}}={(l.sub.1).sup.n-1O.sub.n}={{(l.sub.1).sup.-
-1o.sub.1}, {(l.sub.1).sup.n-1o.sub.2}, . . . ,
{(l.sub.1).sup.n-1o.sub.n-1}}. Structure features of the orbit
leader array O.sub.n provided by Theorem 2 are analyzed below and
several different design methods are provided thereafter.
Structure Features of the Orbit Leader Array O.sub.n:
An orbit leader array of the presented (n,n(n-1),n-1) permutation
group code has the following features: first, it is an array of
(n-1).times.n, each row thereof is a permutation of S.sub.n, and an
unique column thereof contains a same element a.sub.k=k, where k,
a.sub.k.di-elect cons.Z.sub.n.sup.0 or k, a.sub.k.di-elect
cons.Z.sub.n.sup.1; second, removing the column containing the same
element, residual rows and columns constitute a Latin square with a
size of (n-1).times.(n-1); and third, each row of the orbit leader
array O.sub.n has n different adjacent pairs
(.alpha..sub..mu.,a.sub.v) containing cyclic adjacent pairs, and
the orbit leader array O.sub.n itself contains n(n-1) different
adjacent (or cyclic adjacent) pairs, .mu., v, a.sub..mu.,
a.sub.v.di-elect cons.Z.sub.n.sup.0 or .mu., v, a.sub..mu.,
a.sub.v.di-elect cons.Z.sub.n.sup.1, a.sub..mu..noteq.a.sub.v, and
.mu..noteq.v. Generally, n(n-1) different pairs in a form of
(a.mu., a.sub.v) can be obtained as constructed by n positive
integers, which is a sufficient condition for the orbit leader
array containing n(n-1) different adjacent pairs.
Design Method of the Orbit Leader Array O.sub.n:
An orbit leader array meeting the above three structure features
can be calculated by explicit expressions, and the following two
design methods can be realized by hardwares for Theorem 2.
Method 1: A Permutation Contains Element 0
Let a.sub..alpha..sub.1.sub.,.beta..sub.1.di-elect
cons.Z.sub.n.sup.0={0, 1, . . . , n-1} denote an element in the
.alpha..sub.1th row and the .beta..sub.1th column of an array
O.sub.n1, where .alpha..sub.1=0, 1, . . . , n-2 denotes the row
index of the array O.sub.n1, .beta..sub.1=0, 1, . . . , n-1 denotes
the column index of the array O.sub.n1, and k.sub.1=0, 1, . . . ,
n-1 denotes that all elements in the k.sub.1th column of the array
O.sub.n1 equal k.sub.1; as n is a prime, let a modular n of xn
equal 0 if .alpha..sub..alpha..sub.1.sub.,.beta..sub.1 is a
multiple of n, namely a.sub..alpha..sub.1.sub.,.beta..sub.1=xn(mod
n)=0, where x could be any integer, and calculate each element of
each permutation of the orbit leader array O.sub.n1 by:
a.sub..alpha..sub.1.sub.,.beta..sub.1(k.sub.1)=[(.alpha..sub.1+1).times.(-
.beta..sub.1-k)+k.sub.1](mod n) (i)
O.sub.n1(k.sub.1)={o.sub.0,o.sub.1, . . .
,o.sub.n-2}={{a.sub..alpha..sub.1.sub.,.beta..sub.1(k.sub.1)}.sub..al-
pha..sub.1.sub.=0.sup.n-2}.sub..beta..sub.1.sub.=0.sup.n-1(k.sub.1=0,1,
. . . ,n-1) (ii) Method 2: A Permutation Contains No Element 0
Let a.sub..alpha..sub.2.sub.,.beta..sub.2.di-elect
cons.Z.sub.n.sup.1={1, 2, . . . , n} denote an element in the
.alpha..sub.2th row and the .beta..sub.2th column of an array
O.sub.n2, where .alpha..sub.2=1, 2, . . . , n-1 denotes the row
index of the array O.sub.n2, .beta..sub.2=1, 2, . . . , n denotes
the column index of the array O.sub.n2, and k.sub.2=1, 2, . . . , n
denotes that all elements in the k.sub.2th column of the array
O.sub.n2 equal k.sub.2; as n is a prime, let a modular n of xn
equal n if a.sub..alpha..sub.2.sub.,.beta..sub.2 is a multiple of
n, namely a.sub..alpha..sub.2.sub.,.beta..sub.2=xn(mod n)=n, where
x could be any integer, and calculate an element of a permutation
of the orbit leader array O.sub.n2 by:
a.sub..alpha..sub.2.sub.,.beta..sub.2(k.sub.2)=[(.alpha..sub.2(.beta..sub-
.2-k.sub.2)+k.sub.2](mod n) (iii)
O.sub.n2(k.sub.2)={o.sub.1,o.sub.2, . . .
,o.sub.n-1}={{a.sub..alpha..sub.2.sub.,.beta..sub.2(k.sub.2)}.sub..alph-
a..sub.2.sub.=1.sup.n-1}.sub..beta..sub.2.sub.=0.sup.n(k.sub.2=0,1,
. . . ,n-1) (iv)
As k.sub.2=n, equations (iii) and (iv) in method 2 can be
simplified as: a.sub..alpha.,.beta.(n)=[.alpha..beta.](mod n) for
.alpha.=1,2, . . . ,n-1 and .beta.=1,2, . . . ,n (v)
O.sub.n={o.sub.1,o.sub.2, . . .
,o.sub.n-1)}={{a.sub..alpha.,.beta.(n)}.sub..beta.=1.sup.n}.sub..alpha.=1-
.sup.n-1=[[.alpha..beta.].sub..beta.=1.sup.n].sub..alpha.=1.sup.n-1(mod
n)={.alpha.o.sub.1}.sub..alpha.=1.sup.n-1(mod n) (vi)
Calculation of equation (vi) is the same as that of O.sub.n in
Theorem 2.
EXAMPLE 2
Let n=5, according to the design method 1, if
a.sub..alpha..sub.1.sub.,.beta..sub.1.di-elect cons.Z.sub.n.sup.0,
c.sub.0=o.sub.0=e=[01234], and each element of each permutation of
O.sub.n1(k.sub.n) is calculated by
a.sub..alpha..sub.1.sub.,.beta..sub.1(k.sub.1)=[(.alpha..sub.1+1).times.(-
.beta..sub.1-k.sub.1)+k](mod n), different orbit leader arrays can
be calculated by O.sub.n1(k.sub.1) in equation (ii) as follows as
k.sub.1=0, 1, 2, 3, 4:
.times..times..times. ##EQU00007## ##EQU00007.2##
Performing a cyclic-left-shift composite operation function
(l.sub.1).sup.4 or a cyclic-right-shift composite operation
function (r.sub.5).sup.4 on the above five orbit leader arrays of
O.sub.n1(k.sub.1) (k.sub.1=0, 1, 2, 3, 4) respectively, ten
equivalent permutation code sets can be obtained.
Let n=5, according to the design method 2 and a corresponding
simplified alternative, if
a.sub..alpha..sub.2.sub.,.beta..sub.2.di-elect cons.Z.sub.n.sup.1,
c.sub.1=o.sub.1=e=[12345], and each element of each permutation is
calculated by (iii)
a.sub..alpha..sub.2.sub.,.beta..sub.2(k.sub.2)=[.alpha..sub.2(.beta..sub.-
2-k.sub.2)+k.sub.2] (mod n) or (v)
a.sub..alpha.,.beta.(n)=[.alpha..beta.](mod n), different orbit
leader arrays can be calculated by O.sub.n2(k.sub.2) in equation
(iv) and O.sub.n in equation (vi) as follows as k.sub.2=1, 2, 3, 4,
5:
.times..times..times. ##EQU00008## .times..times.
##EQU00008.2##
Performing a cyclic-left-shift composite operation function
(l.sub.1).sup.4 or a cyclic-right-shift composite operation
function (r.sub.5).sup.4 on five orbit leader arrays of
O.sub.n2(k.sub.2) (k.sub.2=1, 2, 3, 4, 5) and a simplified orbit
leader array O.sub.5 respectively, 12 permutation code sets
obtained are equivalent to the code set of the (n,n(n-1),n-1)
permutation group code obtained by composition operations, namely,
for k=1, 2, 3, 4, 5,
.times..times..function..times..function..times..times.
##EQU00009## Part 2: Structure Design of a Generator of the
(n,n(n-1),n-1) Permutation Group Code Based on Coset Partition
Illustration of the generator comprises 4 parts: generator
architecture, orbit leader array generator, flash memory and
cyclic-bidirectional-shift register group.
Binary Expression of a Permutation:
If m-bit binary data are used to express elements of a permutation
with a length of n, the permutation can be described by a binary
array of m.times.n, and 2.sup.m-1+1.ltoreq.n.ltoreq.2.sup.m.
Generator Architecture of the Presented Code Set
As in FIG. 1, the generator architecture of the presented code set
is formed by 3 parts: an orbit leader array generator, a flash
memory and a cyclic-bidirectional-shift register group. A schematic
circuit of the orbit leader array generator is designed based on
equations (i).about.(vi), a specific working process is performing
an operation of {.alpha.o.sub.1}.sub..alpha.=1.sup.n-1(mod n) to
generate an orbit leader array O.sub.n={o.sub.1, o.sub.2, . . . ,
o.sub.n-1} containing n-1 permutations. The flash memory is
operable for storing an output result O.sub.n={o.sub.1, o.sub.2, .
. . , o.sub.n-1} of the orbit leader array generator and an output
result P.sub.n={{(l.sub.1).sup.n-1o.sub.1},
{(l.sub.1).sup.n-1o.sub.2}, . . . , {(l.sub.1).sup.n-1o.sub.n-1}}
or P.sub.n={{(r.sub.n).sup.n-1o.sub.1}, {(r.sub.n).sup.n-1o.sub.2},
. . . , {(r.sub.n).sup.n-1o.sub.n-1}} of the
cyclic-bidirectional-shift register group. The
cyclic-bidirectional-shift register group is operable for
performing an operation on a permutation by a cyclic-left-shift
composite operation function (l.sub.1).sup.n-1 or a
cyclic-right-shift composite operation function (r.sub.n).sup.n-1
(specifically, performing cyclic shift on a permutation
o.sub..alpha. to a left or right direction for n-1 times)
calculating an orbit {(l.sub.1).sup.n-1o.alpha.} or
{(r.sub.n).sup.n-1o.sub..alpha.} of an orbit leader permutation
o.sub..alpha., where .alpha.=1, 2, . . . , n-1. For an orbit
{(l.sub.1).sup.n-1o.sub..alpha.} or
{(r.sub.n).sup.n-1o.sub..alpha.} contains n permutations, a
(n,n(n-1),n-1) permutation group code based on coset partition can
be generated by repeating generating process of each orbit for n-1
times, and a specific calculating equation thereof is:
P.sub.n=C.sub.nO.sub.n={(l.sub.1).sup.n-1O.sub.n}={{(l.sub.1).sup.n-1o.su-
b.1}, {(l.sub.1).sup.n-1o.sub.2}, . . . ,
{(l.sub.1).sup.n-1o.sub.n-1}} or P.sub.n=C.sub.n
O.sub.n={{(r.sub.n).sup.n-1O.sub.n}, {(r.sub.n).sup.n-1o.sub.1},
{(r.sub.n).sup.n-1o.sub.2}, . . . ,
{(r.sub.n).sup.n-1o.sub.n-1}}.
The orbit leader array generator is shown in FIG. 2 and structural
parameters thereof are designed as follows with an optimum circuit
structure. To avoid amplitude values attenuating to 0 under fading
interference conflicting with code element 0 in a code, set
a.sub..alpha.,.beta..di-elect cons.Z.sub.n.sup.1 to ensure absence
of element 0 in each permutation code, where n is an arbitrary
prime. To facilitate code element tracking, let k.sub.2=n which
means that all elements of the last column of the orbit leader
array are the same with a value of n, so that equation (iii) can be
simplified to an equation (v):
a.sub..alpha.,.beta.(n)=[.alpha..beta.] (mod n), and calculation of
the orbit leader array O.sub.n can be simplified to
O.sub.n={o.sub.1, o.sub.2, . . . ,
o.sub.n-1}={.alpha.o.sub.1}.sub..alpha.=1.sup.n-1(mod n), where
.alpha.=1, 2, . . . , n-1 representing that n-1 permutations are
contained in the orbit leader array, and .beta.=1, 2, . . . , n
representing that n elements are contained in each permutation.
The orbit leader array generator is operable for performing an
operation of O.sub.n={.alpha.o.sub.1}.sub..alpha.=1.sup.n-1(mod
n)={o.sub.1, 2o.sub.1, . . . , (n-1)o.sub.1}(mod n) to generate n-1
orbit leader permutations as an initial permutation is
o.sub.1=e=[12 . . . n], and transmitting each of the permutations
to the flash memory right after it is generated.
The orbit leader array generator further comprises 5 parts: n
parallel running input buffers (10), n parallel running positive
integer adders (11), n parallel running mod n calculators (12), n
parallel running output buffers (13), an n-input single-output
switch (14) and an enable signal generator (15). Working principle
of each part is described below.
The n parallel running input buffers (10) are formed by n m-bit
binary registers, each binary register stores one of n input data
as an m-bit binary data, an input and an output of each register
are connected to m parallel data lines respectively, and the orbit
leader generator starts to work after inputting the initial
permutation o.sub.1=e=[12 . . . n] into the n parallel running
input buffers (10). The n parallel running positive integer adders
are operable for converting multiple operations in
O.sub.n={.alpha.o.sub.1}.sub..alpha.=1.sup.n-1={o.sub.1, 2o.sub.1,
. . . , (n-1)o.sub.1} to accumulating operations on each element of
the initial permutation o.sub.1=[12 . . . n], namely, mainly
performing an operation of {.alpha.o.sub.1}.sub..alpha.=1.sup.n-1.
Initial identity permutation requires no accumulation and can be
transmitted directly to an output buffer, so that calculation of
the set {.alpha.o.sub.1}.sub..alpha.=1.sup.n-1 needs n-2
accumulations. Each positive integer adder is formed by m' binary
full-adders and an m'-bit B register, with m parallel input data
lines and m' parallel output data lines, and m<m'.ltoreq..left
brkt-top.log.sub.2(n-1).sup.2.right brkt-bot., an input of the
binary full-adder is operable for receiving data from the input
buffer, another input of the binary full-adder is connected to an
output of the B register, and an output of the binary full-adder is
connected to an input of the B register. As an enable signal E=1,
each adder performs an addition between a last summation result
(data in the B register) and an input of a corresponding parallel
running input buffer (10), stores a result thereof in the B
register and transmits the result to a corresponding parallel
running mod n calculator (12); as the enable signal E=0, the n
parallel running positive integer adders do not work.
The n parallel running mod n calculators (12) are operable for
performing an operation of
{.alpha.o.sub.1}.sub..alpha.=1.sup.n-1(mod n), namely, performing
mod n operations on data from the B register in the n parallel
running positive integer adders, each mod n calculator is formed by
a two-input single-output general mod n calculator, an m-bit C
register and an m-bit D register, with m' parallel input data lines
and m parallel output data lines, an input of the general mod n
calculator is connected to the output of the m'-bit B register
through m' parallel input data lines, another input of the general
mod n calculator is connected to an output of the m-bit C register
through m parallel output data lines, an output of the general mod
n calculator is facilitated with m parallel output data lines, the
m-bit C register is operable for storing and maintaining an m-bit
binary value corresponding to n, the m-bit D register is operable
for storing output values of said general mod n calculator, and a
data |x| stored in the m-bit D register is output as it is not 0,
otherwise a data stored in the m-bit C register is output.
The n parallel running output buffers (13) are formed by n m-bit
registers, with the same structure as the n parallel running input
buffers (10), operable for storing current orbit leader
permutation, and as the (n-1)th buffer of the n parallel running
output buffers (13) is prepared with current data, a signal is
transmitted the first switch of the n-input single-output switch
(14) so that this first switch is on.
The n-input single-output switch (14) is operable for serially
transmitting each of the n data from the n parallel running output
buffers (13) to a bus. m data lines of each output buffer are
connected to an m-paralleled bus by a corresponding turn-on switch,
the signal of closing a switch is transmitted to the first switch
of the n-input single-output switch (14) as the (n-1)th buffer of
the n parallel running output buffers is prepared with current
data, and as the nth switch of the n-input single-output switch is
on, the final data of a codeword is transmitted to the flash memory
by the bus and a high level signal is transmitted to an input of
the enable signal generator (15).
The enable signal generator (15) is operable for providing enable
signals for the n parallel running positive integer adders (11) and
formed by a binary plus 1 counter and a monostable flip-flop, with
an input line and an output line which outputs a low level at a
normal state, an input of the enable signal generator is connected
to an output controlling signal line of the nth switch of the
n-input single-output switch (14), an output of the enable signal
generator is connected to enable terminals of the n parallel
running positive integer adders (11), as the nth switch of the
n-input single-output switch (14) is on, the enable signal
generator (15) is enabled, the binary plus 1 counter performs an
add-one operation, the monostable flip-flop generates a high level
impulse with a width of a cp and transmits it to enable terminals
of the n parallel running positive integer adders (11) to set E=1,
and as the nth switch of the n-input single-output switch (14) is
off, the enable signal generator (15) is disabled and E=0 is
maintained. As the binary plus 1 counter performs n-1 add-one
operations, the enable signal generator (15) outputs a low
level.
The flash memory is shown in FIG. 3, which may be a read only
(ROM), programmable read-only memory (PROM), an erasable
programmable read-only memory (EPROM) or an electrically erasable
programmable read-only memory (E.sup.2PROM).
In the flash memory (16), each element of a permutation is
represented by an m-bit binary data, e.g. the first element of a
permutation is represented by an m-bit binary data b.sub.1,1,
b.sub.2,1, . . . , b.sub.m-1,1, b.sub.m,1, the last element of a
permutation is represented by an m-bit binary data b.sub.1,n,
b.sub.2,n, . . . , b.sub.m-1,n, b.sub.m,n, b.sub.i,j is binary 0 or
1, i=0, 1, . . . , m-1, and j=0, 1, . . . , n-1. m-bit binary data
of an element of a permutation occupies m memory cells defined as
an element storage word, a permutation occupies n element storage
words, n-1 orbit leader permutations occupy n(n-1) element storage
words, and n(n-1) permutation codewords occupy n.sup.2(n-1) element
storage words. The flash memory (16) is facilitated with an m-bit
parallel data input and an m-bit parallel data output. An m-bit
data of an element storage word are input in parallel as Wr=1, an
m-bit data of an element storage word are output in parallel as
Rd=1, and the flash memory (16) is disabled as Wr=0 and Rd=0.
The cyclic-bidirectional-shift register group is shown in FIG. 4.
The cyclic-bidirectional-shift register group (17) is operable for
performing an operation on a permutation by a cyclic-left-shift
composite operation function (l.sub.1).sup.n-1 or a
cyclic-right-shift composite operation function (r.sub.n).sup.n-1
calculating an orbit {(l.sub.1).sup.n-1o.sub..alpha.} or
{(r.sub.n).sup.n-1o.sub..alpha.} of an orbit leader permutation
o.sub..alpha., and a code set {(l.sub.1).sup.n-1O.sub.n} or
{(r.sub.n).sup.n-1O.sub.n}. Each element of an n-dimensional
permutation vector can be expressed by an m-dimensional binary
sequence and an n-dimensional permutation vector can be mapped into
an m.times.n-dimensional binary array, corresponding to an
m.times.n flip-flop array. A bidirectional register capable of
shifting in both a left direction and a right direction cyclically
is formed by n flip-flops in each of the m rows, namely, n
flip-flops form a cyclic-bidirectional-shift register, m
cyclic-bidirectional-shift registers are needed to form a
cyclic-bidirectional-shift register group, e.g. the first
cyclic-bidirectional-shift register is operable for storing an
n-bit binary data b.sub.1,1, b.sub.1,2, . . . , b.sub.1,n-1,
b.sub.1,n and the mth cyclic-bidirectional-shift register is
operable for storing an n-bit binary data b.sub.m,1, b.sub.m,2, . .
. , b.sub.m,n-1, b.sub.m,n (it should be noted that the array
herein is m.times.n dimensional, and the flash memory (16)
corresponds to an array of n.times.m). A switch (18) is serially
connected to each of the cyclic-left-shift loops, in switches
operates in parallel, a cyclic-left-shift operation is performed on
in data in parallel by connecting the m switches, and a left-shift
input operation and a left-shift output operation are performed on
in data in parallel by disconnecting the in switches, and two
inputs REG-in and REG-out are facilitated to provide four groups of
control signals 00, 01, 10 and 11 corresponding to four working
states of the cyclic-bidirectional-shift register group: left-shift
input, left-shift output, cyclic-left-shift and cyclic-right-shift.
Working process of the cyclic-bidirectional-shift register group
(17) is described below.
Process a: input a permutation. As REG-in=0, REG-out=0 and Rd=1,
the in parallel switches (18) of the cyclic-left-shift loops are
disconnected, the first orbit leader permutation of the flash
memory (16) is transmitted to the cyclic-bidirectional-shift
register group (17), namely, the cyclic-bidirectional-shift
register group performs an left-shift-input operation on m-bit
binary in parallel in n times.
Process b: generate a new permutation by cyclic-left-shift. As
REG-in=O and REG-out=1, the m parallel switches (18) of the
cyclic-left-shift loops are connected, and the
cyclic-bidirectional-shift register group (17) performs a
cyclic-left-shift operation on m-bit binary in parallel in n times
to generate a new permutation.
Process c: output a permutation. As REG-in=1, REG-out=O and Wr=1,
the m parallel switches (18) of the cyclic-left-shift loops are
connected, the cyclic-bidirectional-shift register group (17)
performs the following two operations: transmitting a current
permutation generated by Process b to the flash memory (16) by the
left-shift-output operation on m-bit binary in parallel in n times,
and performing a cyclic-left-shift operation on m-bit binary in
parallel in n times, so that a permutation generated by Process b
may be reserved.
Process d: generate an orbit {(l.sub.1).sup.n-1o.sub..alpha.}. It
is formed by a combination of Process b and Process c with the m
parallel switches (18) closed. Process b and Process c work
alternately: this is that during an impulse of cp, REG-in=O and
REG-out=1, the cyclic-bidirectional-shift register group (17)
performs a cyclic-left-shift operation of m-bit in parallel to
generate a new permutation, and during each of the following n
impulses of cp, REG-in=1, REG-out=O and Wr=1, the
cyclic-bidirectional-shift register group (17) simultaneously
performs a left-shift operation to output a current permutation to
the flash memory (16) for storage and a cyclic-left-shift operation
to maintainthis permutation by m-bit in parallel in n times.
Process d is equivalent to performing an operation of
(l.sub.1).sup.n-1 on an orbit leader permutation o.sub..alpha. to
generate an orbit {(l.sub.1).sup.n-1o.sub..alpha.}, and storing n-1
permutations generated by the orbit
{(l.sub.1).sup.n-1o.sub..alpha.} in the flash memory (16).
Process e: generate a code set {(l.sub.1).sup.n-1o.sub..alpha.}. It
is formed by a combination of Process a and Process d, and a code
set {(l.sub.1).sup.n-1O.sub.n} of a (n,n(n-1),n-1) permutation
group code based on coset partition is generated by repeating
Process e for n-1 times.
Process b': generate a new permutation by cyclic-right-shift. As
REG-in=1 and REG-out=1, the m parallel switches (18) of the
cyclic-left-shift loops are disconnected, and the
cyclic-bidirectional-shift register group (17) performs a
cyclic-right-shift operation on m-bit in parallel of length n to
generate a new permutation.
Process d': generate an orbit {(r.sub.n).sup.n-1o.sub..alpha.}. It
is formed by a combination of Process b' and Process c, equivalent
to generating an orbit {(r.sub.n).sup.n-1o.sub..alpha.} of a
permutation o.sub..alpha. and storing the orbit
{(r.sub.n).sup.n-1o.sub.a} in the flash memory (16).
Process e': generate a code set {(r.sub.n).sup.n-1o.sub..alpha.}.
It is formed by a combination of Process a and Process d', and a
code set {(r.sub.n).sup.n-1O.sub.n} of a (n,n(n-1),n-1) permutation
group code based on coset partition is generated by repeating
Process e' for n-1 times.
While preferred embodiments of the invention have been described
above, the invention is not limited to disclosure in the
embodiments and the accompanying drawings. Any changes or
modifications without departing from the spirit of the invention
fall within the scope of the invention.
* * * * *